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Part Manufacturer Description Datasheet Download Buy Part
SN7445NSR Texas Instruments TTL/H/L SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16
SN7445NSRE4 Texas Instruments TTL/H/L SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16
SN7445NSRG4 Texas Instruments TTL/H/L SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16
SN7445NE4 Texas Instruments BCD-To-Decimal Decoders/Drivers 16-PDIP 0 to 70
SN7445N Texas Instruments BCD-To-Decimal Decoders/Drivers 16-PDIP 0 to 70
SN7445J Texas Instruments TTL/H/L SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, CDIP16

TLP 7445 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
dllp

Abstract: pci express dllp pci express serial parallel port circuit diagram PCI express switch pci express tlp ORT42G5 ORT82G5
Text: Diagram PHYSICAL LAYER Electrical Block PHYSICAL LAYER Logical Block DATA LINK LAYER TLP and , Control Status Interface TLP and DLLP Receive Block Descrambler and Deframer Receive User , the mechanism which uses special symbols like K28.2 (SDP) to start a DLLP, K27.7 (STP) to start a TLP , and K29.7 (END) to mark the end of either a TLP or a DLLP. When no packet information or special , at the start of the TLP and an END Symbol or EDB Symbol at the end of the TLP . DLLPs are framed by


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PDF ipug25 1-800-LATTICE dllp pci express dllp pci express serial parallel port circuit diagram PCI express switch pci express tlp ORT42G5 ORT82G5
Not Available

Abstract: No abstract text available
Text: Block DATA LINK LAYER TLP and DLLP Transmission Block SERDES, 8b/10b System Bus of , TRANSACTION LAYER Credit Available Control Status Interface TLP and DLLP Receive Block , DLLP, K27.7 (STP) to start a TLP , and K29.7 (END) to mark the end of either a TLP or a DLLP. When no , TLPs are framed by placing a STP Symbol at the start of the TLP and an END Symbol or EDB Symbol at the end of the TLP . DLLPs are framed by placing an SDP Symbol at the start of the DLLP and an END Symbol


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PDF ipug25 PCI-EXP-T42G5-N1.
2008 - example ml605

Abstract: XAPP1052 ML605 UCF FILE virtex-6 ML605 user guide FPGA based dma controller using vhdl asus motherboard xapp1052 document ML555 asus p5b ML605
Text: Master Enable bit (Bit 2 of PCI Command Register) must be set to initiate TLP traffic upstream. No , www.xilinx.com 8 Exploring the Bus Master Design The first TLP contains the start address, which is specified in the Write DMA TLP Address (see "Write DMA TLP Address (WDMATLPA) (008H, R/W)," page 31 , TLP size defined in the Write DMA TLP Size register (see "Write DMA TLP Size (WDMATLPS) (00CH, R/W , sent onto the link matches the value inside the Write DMA TLP Count (see "Write DMA TLP Count


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PDF XAPP1052 example ml605 XAPP1052 ML605 UCF FILE virtex-6 ML605 user guide FPGA based dma controller using vhdl asus motherboard xapp1052 document ML555 asus p5b ML605
2003 - PCI-EXP-T42G5-N1

Abstract: pci express dllp serdes tutorial pci express tlp ORT42G5 ORT82G5 parallel scrambler PCI dllp phy interface for the PCI Express
Text: Transmit User Interface Block TX USR Interface Credit calcualtion block TLP and DLLP , Control Status Interface Descrambler and Deframer TLP and DLLP Receive Block Receive User , uses special symbols like K28.2 (SDP) to start a DLLP, K27.7 (STP) to start a TLP , and K29.7 (END) to mark the end of either a TLP or a DLLP. When no packet informa- 2 Lattice Semiconductor PCI , set will continue to be transmitted. TLPs are framed by placing a STP Symbol at the start of the TLP


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PDF 8b/10b ORT42G5-2BM484. PCI-EXP-T42G5-N1. PCI-EXP-T42G5-N1 pci express dllp serdes tutorial pci express tlp ORT42G5 ORT82G5 parallel scrambler PCI dllp phy interface for the PCI Express
2011 - Not Available

Abstract: No abstract text available
Text: AND9007/D Understanding TLP Datasheet Parameters Prepared by: Robert Ashton ON Semiconductor , duration for the pulses are similar and the initial rise time for the TLP pulse is comparable to the rise , introduction to TLP measurements and explain the datasheet parameters extracted from TLP for ON Semiconductor's protection products. For more information on TLP measurements please see application note AND9006/D, "Using , Pulse ( TLP ) is a measurement technique used in the Electrostatic Discharge (ESD) arena to characterize


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PDF AND9007/D AND9006/D,
2008 - asus motherboard

Abstract: design of dma controller using vhdl ML605 UCF FILE TLP 3616 XILINX/SPARTAN 3E STARTER BOARD "Asus P5B-VM" sp605 virtex-6 ML605 user guide XBMD virtex ucf file 6
Text: Master Enable bit (Bit 2 of PCI Command Register) must be set to initiate TLP traffic upstream. No , www.xilinx.com 8 Exploring the Bus Master Design The first TLP contains the start address, which is specified in the Write DMA TLP Address (see "Write DMA TLP Address (WDMATLPA) (008H, R/W)," page 30 , TLP size defined in the Write DMA TLP Size register (see "Write DMA TLP Size (WDMATLPS) (00CH, R/W , sent onto the link matches the value inside the Write DMA TLP Count (see "Write DMA TLP Count


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PDF XAPP1052 asus motherboard design of dma controller using vhdl ML605 UCF FILE TLP 3616 XILINX/SPARTAN 3E STARTER BOARD "Asus P5B-VM" sp605 virtex-6 ML605 user guide XBMD virtex ucf file 6
653c

Abstract: No abstract text available
Text: ) Q TLP653CIW _7881 D W hite Q T LP 653C IG _7876D True Green Q TLP 653C E B _7877D Blue Q TLP 653C S _7880D Super Red Q TLP 653C O _7879D Y ellow O range Q TLP 653C M _7878D A m ber Q TLP 653C A G , Inner Lens) Q TLP653CIW _7881 D W hite Q T LP 653C IG _7876D True Green Q TLP 653C E B _7877D Blue Q TLP 653C S _7880D Super Red Q T L P 653C O _7879D Y ellow O range Q TLP 653C M J7878D A m ber Q T L P , hite Q T LP 653C IG _7876D True Green Q TLP 653C E B _7877D Blue Q TLP 653C S _7880D Super Red Q T L


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PDF TLP653CIW 7876D 7877D 7880D 7879D 7878D 7875D 653c
2008 - XAPP1052

Abstract: asus motherboard FPGA based dma controller using vhdl virtex 2 pro XAPP1002 dell power edge "Asus P5B-VM" asus p5b asus motherboard data sheet XC5VLX50T-1FFG1136
Text: time. The Bus Master Enable bit (Bit 2 of PCI Command Register) must be set to initiate TLP traffic , registers specify the address, size, payload content, and number of TLPs to be sent. The first TLP contains the start address, which is specified in the Write DMA TLP Address (WDMATLPA; see "Appendix A , TLP size defined in the Write DMA TLP Size (WDMATLPS) register. The initiator sends Memory Writes , sent onto the link matches the value inside the Write DMA TLP Count (WDMATLPC) register. Figure 3


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PDF XAPP1052 32-bit XAPP1052 asus motherboard FPGA based dma controller using vhdl virtex 2 pro XAPP1002 dell power edge "Asus P5B-VM" asus p5b asus motherboard data sheet XC5VLX50T-1FFG1136
2014 - Not Available

Abstract: No abstract text available
Text: 25.0 V RDYN Typ 13.3 V TLP tp=100ns, I/O to GND , Ipp Min tp=8/20µs , guaranteed by design and/or device characterization. Transmission Line Pulse ( TLP ) with 100ns width and , 22.0 V IPP=5A, tp=8/20µs, Fwd Ipp 30.0 TLP tp=100ns, I/O to GND , tp=8/20µs CI , . Transmission Line Pulse ( TLP ) with 100ns width and 200ps rise time. © 2014 Littelfuse, Inc. Specifications , 1 V tp=8/20µs Peak Pulse Current ESD Withstand Voltage1 Typ 26.7 TLP tp=100ns, I


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PDF IEC61000-4-2 SPHV12-01ETG-C) IEC61000-4-5, OD882
2014 - Not Available

Abstract: No abstract text available
Text: V 13.3 V tp=8/20µs CD-GND 1 Typ TLP tp=100ns, I/O to GND , Ipp 2 Min , design and/or device characterization. Transmission Line Pulse ( TLP ) with 100ns width and 200ps rise , 2 Peak Pulse Current ESD Withstand Voltage1 Diode Capacitance 1 RDYN TLP tp=100ns, I/O , . Transmission Line Pulse ( TLP ) with 100ns width and 200ps rise time. © 2014 Littelfuse, Inc. Specifications , ±30 kV CI/O-GND 1 V TLP tp=100ns, I/O to GND , Peak Pulse Current ESD Withstand Voltage1


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PDF IEC61000-4-2 SPHV12-01ETG) IEC61000-4-5, OD882
2013 - Not Available

Abstract: No abstract text available
Text: IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 2) See Figures 5 through 8 VC IPP = 8 , Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to , ˆ’20 10 EQUIVALENT VIEC (kV) 8 −14 14 TLP CURRENT (A) −16 EQUIVALENT VIEC (kV) TLP CURRENT (A) 8 16 6 12 −12 6 −10 10 4 8 6 2 4 −8 4 , (V) 16 18 0 0 20 0 2 Figure 5. Positive TLP I−V Curve NOTE: 4 6 8


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PDF ESD8104 ESD8104 ESD8104/D
2007 - XAPP1002

Abstract: PCIe Endpoint dllp ChipScope X1002 XAPP1022 FF00000000
Text: solutions for PCIe to track incoming and outgoing Transaction Layer Packets ( TLP ), as received and , ICON cores into the PCIe cores to capture TLP and Data Link Layer Packet (DLLP) link traffic; thus , 32 TLP , Memory Read 64 TLP , or IO Read TLP request presented to it by the core. In addition, the PIO design returns a completion without data with successful status for IO Write TLP request. The PIO design processes a Memory or IO Write TLP with 1 DWORD payload by updating the payload into the target address in


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PDF XAPP1002 XAPP1002 PCIe Endpoint dllp ChipScope X1002 XAPP1022 FF00000000
2013 - Not Available

Abstract: No abstract text available
Text: Pins) Clamping Voltage TLP (Note 4) See Figures 4 through 7 Cut-off frequency ZSOURCE = 50 W, ZLOAD = , Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W , (A) VOLTAGE (V) Figure 4. Positive TLP I-V Curve Transmission Line Pulse ( TLP ) Measurement Figure 5. Negative TLP I-V Curve Transmission Line Pulse ( TLP ) provides current versus voltage (I-V , transmission line. A simplified schematic of a typical TLP system is shown in Figure 6. TLP I-V curves of ESD


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PDF EMI9404 pF-35 EMI9404/D
asus p5rd1-vm motherboard diagram

Abstract: Desktop motherboard asus MOTHERBOARD troubleshooting pci express tlp asus a6 asus motherboard block diagram UG01 SC80 p5rd1 Asus p5rd1-vm
Text: the size of the TLP in which to perform the transfer. Background Knowledge This demo assumes the , . This block converts PCI Express TLP Memory Requests into Wishbone bus cycles. Both BAR0 and BAR1 are , providing an inter TLP gap (IPG). · Ca ­ This module is responsible for checking if credits are available to send the current TLP . · Ta ­ This module is responsible for checking if the tag is available for , the system to send more completions. Each CPLD TLP is stored along with a timestamp to mark the


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PDF Windows2000, Server2003) D975XBX D975XBX 975/ICH7 DL145 asus p5rd1-vm motherboard diagram Desktop motherboard asus MOTHERBOARD troubleshooting pci express tlp asus a6 asus motherboard block diagram UG01 SC80 p5rd1 Asus p5rd1-vm
2014 - Not Available

Abstract: No abstract text available
Text: Clamping Voltage TLP (Note 2) VC IPP = 8 A IEC 61000−4−2 Level 2 equivalent (±4 kV Contact , ESD8451N2T5G Clamping Voltage TLP (Note 2) VC V V V ESD8451MUT5G Dynamic Resistance RDYN , Sensitivity Testing using Transmission Line Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 , TYPICAL CHARACTERISTICS 20 20 10 18 16 12 TLP CURRENT (A) 14 6 10 8 4 6 , 14 16 18 20 VC, VOLTAGE (V) Figure 7. ESD8451MUT5G Positive TLP I−V Curve â


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PDF ESD8451 152AF 711AM ESD8451/D
2014 - Not Available

Abstract: No abstract text available
Text: ) VC IEC61000−4−2, ±8 KV Contact ESD8451MUT5G Clamping Voltage TLP (Note 2) VC IPP = , equivalent (±4 kV Contact, ±4 kV Air) 16.0 ESD8451N2T5G Clamping Voltage TLP (Note 2) VC V , ( TLP ) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = , 10 18 16 12 TLP CURRENT (A) 14 6 10 8 4 6 4 2 2 0 0 2 4 , , VOLTAGE (V) Figure 7. ESD8451MUT5G Positive TLP I−V Curve −20 Figure 8. ESD8451N2T5G Positive


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PDF ESD8451, SZESD8451 ESD8451 152AF ESD8451/D
2014 - Not Available

Abstract: No abstract text available
Text: V 6.0 V tp=8/20µs VESD Max 5.0 TLP tp=100ns, I/O to Ground , Ipp Min , 1.0 μA IPP=1A, tp=8/20µs, Fwd 18.5 V 23.0 V TLP tp=100ns, I/O to Ground , μA 24.0 V IPP=10A, tp=8/20µs, Fwd 31.0 TLP tp=100ns, I/O to Ground , tp=8/20µs , Capacitance1 RDYN Test Conditions CI/O-GND Typ 26.7 TLP tp=100ns, I/O to Ground , Ipp , TLP tp=100ns, I/O to Ground , tp=8/20µs CI/O-GND 0.68 ±30 IEC61000-4-2 (Air Discharge


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PDF SD05C) IEC61000-4-5) IEC61000-4-2, OD323
footprint te 0606

Abstract: No abstract text available
Text: BRIGHT 0606 Q TLP 600C -R A G Red/Yellow-G reen PACKAGE DIM ENSIONS Yellow / Yellow-Green / Blue , Corporation Page 1 of 7 1/14/03 0ÆRJLIGHT Q TLP 600C -R Y Red/Yellow Q TLP 600C -R E B Red/Blue SURFACE MOUNT LED LAMP SUPER BRIGHT 0606 Q TLP 600C -R A G R ed/Yellow-G reen ABSOLUTE M AXIMUM , TLP 600C -R E B Red/Blue SURFACE MOUNT LED LAMP SUPER BRIGHT 0606 Q TLP 600C -R A G Red/Yellow-G , SUPER BRIGHT 0606 Q TLP 600C -R A G Red/Yellow-G reen Fig. 5 Relative L u m in o u s In te n sity vs


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2011 - EMI9404

Abstract: No abstract text available
Text: Pins) Clamping Voltage TLP (Note 4) See Figures 4 through 7 Cut-off frequency ZSOURCE = 50 W, ZLOAD = , Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W , (A) VOLTAGE (V) Figure 4. Positive TLP I-V Curve Transmission Line Pulse ( TLP ) Measurement Figure 5. Negative TLP I-V Curve Transmission Line Pulse ( TLP ) provides current versus voltage (I-V , transmission line. A simplified schematic of a typical TLP system is shown in Figure 6. TLP I-V curves of ESD


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PDF EMI9404 pF-35 EMI9404/D
2013 - SM05-02HTG

Abstract: No abstract text available
Text: ESD Withstand Voltage1 VESD 13.0 TLP tp=100ns, I/O to GND , 0.19 V Ω 24.0 A , Typ 13.3 TLP tp=100ns, I/O to GND , Peak Pulse Current (8/20µs)1 Min V 0.25 â , Current (8/20µs)1 Ipp tp=8/20µs ESD Withstand Voltage1 VESD 30.0 TLP tp=100ns, I/O to , 42.0 TLP tp=100ns, I/O to GND , 0.50 V Ω 7 .0 A IEC61000-4-2 (Contact Discharge , ESD Withstand Voltage1 VESD Dynamic Resistance Diode Capacitance1 2 Typ 40.0 TLP


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PDF IEC61000-4-2 8/20us IEC61000-4-5) IEC61000-4-2, IEC61000-4-4, 5/50ns) IEC61000-4-5, AEC-Q101 180mm SM05-02HTG
2008 - ML605 UCF FILE

Abstract: XAPP1052 asus motherboard virtex-6 ML605 user guide TLP 3616 xapp1052 document dell power edge Xilinx Spartan-6 FPGA Kits "Asus P5B-VM" XBMD
Text: Master Enable bit (Bit 2 of PCI Command Register) must be set to initiate TLP traffic upstream. No , www.xilinx.com 8 Exploring the Bus Master Design The first TLP contains the start address, which is specified in the Write DMA TLP Address (see "Write DMA TLP Address (WDMATLPA) (008H, R/W)," page 31 , TLP size defined in the Write DMA TLP Size register (see "Write DMA TLP Size (WDMATLPS) (00CH, R/W , sent onto the link matches the value inside the Write DMA TLP Count (see "Write DMA TLP Count


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PDF XAPP1052 ML605 UCF FILE XAPP1052 asus motherboard virtex-6 ML605 user guide TLP 3616 xapp1052 document dell power edge Xilinx Spartan-6 FPGA Kits "Asus P5B-VM" XBMD
2012 - Not Available

Abstract: No abstract text available
Text: . 18 Transmit TLP Interface. 18 Transmit TLP Interface Waveforms for x1 . 23 Receive TLP Interface , buffer Transaction Layer • Transmit and Receive Flow control • Malformed and poisoned TLP detection • Optional ECRC generation/checking • INTx message TLP decoding and interrupt signaling to


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PDF IPUG85 12L-1
2014 - Not Available

Abstract: No abstract text available
Text: Clamping Voltage TLP (Note 3) VC IPP = 16 A IPP = −16 A Clamping Voltage 8/20 ms Waveform per , . ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns , 10 14 12 6 10 4 8 6 TLP Current[A] 8 16 EQUIVALENT VIEC (kV) −20 18 TLP Current [A] 12 −24 −18 −14 −10 0 2 4 6 8 10 12 14 4


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PDF ESD5481MUT5G ESD5481 ESD5481/D
650c

Abstract: No abstract text available
Text: OÆRJLIGHT Q TLP 650C -R Y Red/Yellow SURFACE MOUNT LED LAMP SUPER BRIGHT 1210 Q TLP 650C -R A , /01 1 OF 6 www .fairchildsem i.com 6 ÆRUGHT Q TLP 650C -R Y Red/Yellow SURFACE MOUNT LED LAMP SUPER BRIGHT 1210 Q TLP 650C -R A G Red/Yellow-Green ABSOLUTE M AXIM UM RATINGS P a ra m e , /30/01 DS300097 &ÆRJLIGHT Q TLP 650C -R Y Red/Yellow SURFACE MOUNT LED LAMP SUPER BRIGHT 1210 Q TLP 650C -R A G Red/Yellow-Green TYPICAL PERFORMANCE CURVES Fig. 1 F o rw a rd C u rre n


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PDF DS300097 650c
2013 - Not Available

Abstract: No abstract text available
Text: ˆ’4−2, ±8 KV Contact Clamping Voltage TLP (Note 2) See Figures 7 through 10 VC IPP = 8 A IPP = , Transmission Line Pulse ( TLP ) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = , ESD8008 −20 18 −18 8 TLP CURRENT (A) 14 −14 6 12 6 −12 −10 10 4 8 6 4 VC = VHOLD + (IPP * RDYN) 2 0 8 −16 EQUIVALENT VIEC (kV) TLP CURRENT , VC, VOLTAGE (V) Figure 7. Positive TLP I−V Curve NOTE: EQUIVALENT VIEC (kV) 20 Figure


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PDF ESD8008 ESD8008 8008M UDFN14 517CN ESD8008/D
Supplyframe Tracking Pixel