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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC4050EMS-4.1 Linear Technology LTC4050 - Lithium-Ion Linear Battery Charger Controller with Thermistor Interface; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4061EDD Linear Technology LTC4061 - Standalone Linear Li-Ion Battery Charger with Thermistor Input; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LTC4069EDC-4.4#TRM Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature: Extended
LTC4061EDD-4.4#TRPBF Linear Technology LTC4061-4.4 - Standalone Linear Li-Ion Battery Charger with Thermistor Input; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LTC4069EDC#PBF Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC-4.4#TR Linear Technology LTC4069-4.4 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C

TDC 310 thermistor Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2009 - TDC 310 thermistor

Abstract: TDC 310 NTC thermistor TDC 310 NTC smd code LE npn IR3521MTRPBF TDC+310+thermistor 315mV U-345 CVCC11 CCP22
Text: CCP22 RFB11 CCP12 Load Line NTC Thermistor ; Locate close to VDD Power Stage VDD SENSE + VDD , Temperature Compensation A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature compensation. The thermistor should be placed close to the output1 inductors and , thermistor is used to reduce the nonlinearity of the thermistor . Remote Voltage Sensing VOSENX+ and VOSENX


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PDF IR3521 IR3521 TDC 310 thermistor TDC 310 NTC thermistor TDC 310 NTC smd code LE npn IR3521MTRPBF TDC+310+thermistor 315mV U-345 CVCC11 CCP22
TDC 310 NTC thermistor

Abstract: TDC 310 thermistor
Text: CCP12 RFB13 Load Line NTC Thermistor ; Locate close to VDD Power Stage To VDD Remote Sense , Temperature Compensation A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature compensation. The thermistor should be placed close to the output1 inductors and , thermistor is used to reduce the nonlinearity of the thermistor . Remote Voltage Sensing VOSENX+ and VOSENX


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PDF IR3521 IR3521 TDC 310 NTC thermistor TDC 310 thermistor
2003 - overvoltage protection using lm393

Abstract: LM393 rpu nths0603n02n6801jr Intel socket 478 PIN LAYOUT 478 SOCKET PIN LAYOUT computer pentium 4 MOTHERBOARD CIRCUIT diagram mobile 478 SOCKET PIN LAYOUT intel processor transistor count pentium 4 motherboard CIRCUIT diagram ATX12V
Text: Supporting Hyper-Threading Technology Power Delivery Specifications Iccmax VR TDC Dynamic Icc 91A 80A , thermistor in the feedback network, tuned with a resistor network to negate the effects of the increased , regulator at VR TDC for 30 to 45 minutes. This is to ensure the board is thermally saturated and system , Icc max specifications and robust cooling solutions to support 80 A thermal design current (VR TDC ) indefinitely within the envelope of system operating conditions Intel processor's VR TDC is the sustained (DC


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2011 - TDC 310 NTC thermistor

Abstract: TDC 310 NTC TDC 210 NTC TDC 310 thermistor MAX17511 1/TDC 310 NTC thermistor GFX 2AA IMVP7 Ps3 MOTHERBOARD CIRCUIT diagram
Text: , IMAXA = 39A 27.0 30.0 33.0 RSENSE = 0.75mI, IMAXA = 36A 25.0 28.0 31.0 RSENSE = , RSENSE = 0.85mI, IMAXA = 39A 30.0 33.0 36.0 RSENSE = 0.85mI, IMAXA = 36A 28.0 31.0 , 31.0 34.0 37.0 RSENSE = 0.95mI, IMAXA = 30A 25.0 28.0 31.0 RSENSE = 0.95mI, IMAXA , 33.0 RSENSE = 0.75mI, IMAXB = 36A 25.0 28.0 31.0 RSENSE = 0.75mI, IMAXB = 23A 15.0 , 30.0 33.0 36.0 RSENSE = 0.85mI, IMAXB = 36A 28.0 31.0 34.0 RSENSE = 0.85mI, IMAXB


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PDF VR12/IMVP7 MAX17411/MAX17511/MAX17511C/MAX17511N/ MAX17511T VR12/IMVP-7 MAX17411 MAX17511/MAX17511C/MAX17511N/MAX17511T MAX17411/MAX17511/ MAX17511C/MAX17511N/MAX17511T TDC 310 NTC thermistor TDC 310 NTC TDC 210 NTC TDC 310 thermistor MAX17511 1/TDC 310 NTC thermistor GFX 2AA IMVP7 Ps3 MOTHERBOARD CIRCUIT diagram
VMEbus Handbook

Abstract: LEMO VME COnnector lemo 9 pin connector VME64X STR 8124 SIS3400 0x22C LEMO 7 pin Harting 02 01
Text: SIS Documentation SIS3400 CDMSII TDC /Time Stamper SIS3400 CDMS II VME TDC /Time Stamper , 20.03.02 Page 1 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper Revision Table , CDMSII TDC /Time Stamper 1 Table of contents 1 2 3 Table of contents , .33 Page 3 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper 10.1 Single Wire mode , .46 Page 4 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper 2 Introduction The


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PDF SIS3400 SIS3400 VME64x. VME64xP rs485 VMEbus Handbook LEMO VME COnnector lemo 9 pin connector VME64X STR 8124 0x22C LEMO 7 pin Harting 02 01
mc710

Abstract: JA06 MC710-12X ITT A05 b13j
Text: 3.8 4.3 ns Dout, CoutO tDC Phase Difference of Dout to CoutO -50 0 50 ps Power Supply Iss Power , DEFINITIONS OF trD, tfD, tSEd, tHEd, td, tDC (1) trD (Data Output Rise Time), tfD (Data Output Fall Time , C16in C16out -/50% td -Z-50% / (4) tDC (Phase Difference of Dout to CoutO) Dout CoutO -¥- 50% tDC + •^50% X -8- NEL MC710-12X Jitter performance example (Condition : Input Sequence - PRBS , TcMON pin is connected to a chip thermistor mounted on the MUX )C package. The temperature of the


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PDF MC710-12X MC710-12x 2495-Gb/s 2495Gb/s 100ppm. mc710 JA06 ITT A05 b13j
tdc 310

Abstract: HP9000 RS6000 tpl 624
Text: 1,107,072 1, 310 ,035 MG7xPB26 548 804 2,680 2,154,720 969,624 1,249,738 1 , 984 3,280 3,227,520 1,355,558 1,678, 310 2,001,062 MG7xPB34 708 1,044 3,480 , Data Check (CDC) · Delay Processor · Test Data Check ( TDC ) Oki Test Data Check program ( TDC ) verifies test vector rules. Sun and HP9000/7xx Sun and PC TDC TPL / EDIF Tester Interface


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PDF MG113P/114P/115P/73P/74P/75P MG113P/73P MG114P/74P MG115P/75P MG7xPB08 MG7xPB10 MG7xPB12 MG7xPB14 MG7xPB16 HP9000/7xx, tdc 310 HP9000 RS6000 tpl 624
1999 - ATM machine using microcontroller

Abstract: No abstract text available
Text: TCK TMS TRSTB OE JTAG TAP TUDATA[ 31.0 ] TUPRTY TUSOC TUENB* TUFULL*/TUCLAV TUCLK TUCLKO RUDATA[ 31.0 , Interface Symbol fRLCLK Tdc , RLCLK Tr/f, RLCLK Ts, RLIN Th, RLIN Tp, RXRC fRXRCLK Tdc , RXRCLK , Interface Symbol fTLCLK Tdc , TLCLK STS-48 Physical Layer ATM UNI/NNI Device Description TLCLK+/- clock frequency (nominal) TLCLK+/- duty cycle Min 40 Tdc , TLCLK - (550ps x fTLCL K) 1.0 1.0 0 30 Max 155.52 60 Unit MHz % Tdc , TLCLKO TLCLKO+/- duty cycle % Tr/f, TLCLK Tp, TLOUT Tp


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PDF VSC9110 STS-48c STM-16c STS-48 GR-253-CORE VSC9110 G52198-0, ATM machine using microcontroller
Not Available

Abstract: No abstract text available
Text: 17 18 19 20 21 Symbol TcC TwCh TIC TrC TwCI TsAD(C) TsCS(C) TdC (DO) TsDI(C) TdRD(DOz) TdlO(DOI) TsM1(C) TslEI(IO) TdM1(IEO) TdlEI(IEOr) TdlEI(IEOf) TdC (INT) TdlO(W/RWf) TdC (W/RR) TdC (W/RWz) Th , 860 540 510 760 380 380 510 760 310 390 0 0 210 200 300 150 150 200 300 120 150 470 410 610 610 50 230


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PDF Z8340 40-pin Z8340-1 Z8340-3
1995 - TDC 310

Abstract: 6D120 MC145426 MC145425P MC145425DW MC145425 MC145422 MC145421P MC145421DW MC145421
Text: 18 TDC /RDC D2I 7 18 XTL DCLK 8 17 CCI DCLK 8 17 CCI D1O , 3 LI D1I RE2 Rx RE1 B CHANNEL BUFFERS 12 VD D2I D2O DCLK D1O TDC /RDC , CCI Clock Frequency - - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* TDC 310 6D120 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW
1995 - Nippon capacitors

Abstract: ADI1251 MC145426 MC145425P MC145425DW MC145425 MC145422 MC145421P MC145421DW MC145421
Text: 18 TDC /RDC D2I 7 18 XTL DCLK 8 17 CCI DCLK 8 17 CCI D1O , 3 LI D1I RE2 Rx RE1 B CHANNEL BUFFERS 12 VD D2I D2O DCLK D1O TDC /RDC , CCI Clock Frequency - - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* Nippon capacitors ADI1251 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW
1995 - MC145421

Abstract: 6D120 MC145426 MC145425P MC145425DW MC145425 MC145422 MC145421P MC145421DW Nippon capacitors
Text: RE1 D1I 6 19 CLKOUT D2I 7 18 TDC /RDC D2I 7 18 XTL DCLK 8 , D2O DCLK D1O TDC /RDC B2 13 15 B CHANNEL BUFFERS DEMODULATOR 14 Tx TE1 TE2 , MHz TDC /RDC Data Clocks (for Master) - 0.128 - 4.1 MHz - 0.016 - 4.1 , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , B channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* 6D120 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW Nippon capacitors
LINE FEED ISDN

Abstract: MC145421 MC145422 MC145425
Text: CHANNEL BUFFERS 20 21 19 10 18 >1, 14 D2I D1I RE2 Rx RE1 -D20 DCLK -010 - TDC /RDC Tx -TEI , Clock Frequency - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - 0.128 - 4.1 MHz DCLK - 0.016 4.1 , the TDC /RDC data clock input pin. CCI —HIGH-SPEED CLOCK INPUT (PIN 17) An 8.192 MHz clock should , channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) MOTOROLA 4 , ) B channel data is input on this pin and is controlled by the RE1, RE2, and TDC /RDC pins. (See RE1


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PDF MC146421/D MC145421 MC145425 MK145BP, MC145421Â MC145425 A19596 C41268 LINE FEED ISDN MC145422
32 pins qfn 5x5 footprint

Abstract: 20 pins qfn 5x5 footprint chl8214 CHL822 CHL8225 programmable digital pwm I2C multiphase CHL8212 qfn 20 PACKAGE footprint CHL8213 QFN 36 footprint
Text: Digital Multi-Phase Buck Controller CHL8203/12/13/14 FEATURES Dual output 2/3/4+1-phase PWM Controller (CHL8212/13/14) and single output 3-phase PWM Controller (CHL8203) Easiest layout and fewest pins in the industry Footprint compatible with CHL8225 (CHL8213/14) for analog and power signals Up to 3 VID select lines for dynamic voltage transitions Slow OCP for Thermal Design Current ( TDC ) protection , CHL8203/13/14 includes thermistor based temperature sensing with VRHOT signal. The CHL8203/12/13/14


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PDF CHL8203/12/13/14 CHL8212/13/14) CHL8203) CHL8225 CHL8213/14) CHL8203/13/14) 200kHz CHL8203 CHL8212 32 pins qfn 5x5 footprint 20 pins qfn 5x5 footprint chl8214 CHL822 CHL8225 programmable digital pwm I2C multiphase qfn 20 PACKAGE footprint CHL8213 QFN 36 footprint
CHL8225

Abstract: No abstract text available
Text: ‚· Slow OCP for Thermal Design Current ( TDC ) protection  Programmable ICRITICAL signal The CHL8212 , thermistor based temperature sensing with VRHOT signal.  Compatible with IR ATL and 3.3V tri-state


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PDF CHL8203/12/13/14 CHL8212/13/14) CHL8203) CHL8225 CHL8213/14) CHL8212/13/14 CHL8203 CHL8212 CHL8203 CHL8225
Not Available

Abstract: No abstract text available
Text: 18 ] TDC /RDC 17 ] CCI 16 ] MSI 15 ] TE1 14 ] TE2 13 ] Tx MC145425 - SLAVE (PLASTIC AND SOG , Note) CCI Clock Frequency TDC /RDC Data Clocks (for Master) DCLK Modulation Baud Rate (CCI/16) Pins vdd , during the previous frame. MSI should be approximately leading edge aligned with the TDC /RDC data clock , device. The B channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel data is input on this pin and is controlled by the RE1, RE2, and TDC


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PDF MC145421 MC145425 MC145421 b3b72S3
Not Available

Abstract: No abstract text available
Text: 140 590 860 540 510 760 380 380 510 760 310 390 0 0 210 200 300 150 150 200 300 120 150 50 230 340 , TwCh TfC TrC TwCI TsAD(C) TsCS(C) TdC (DO) TsDI(C) TdRD(DOz) TdlO(DOI) TsM1(C) TslEI(IO) TdM1(IEO) TdlEI(IEOr) TdlEI(IEOf) TdC (INT) TdlO(W/RWf) TdC (W/RR) TdC (W/RWz) Th Parameter Clock Cycle Time Clock


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PDF QQG5M05 T-75-37-07 0D0S40t, 40-pln Z8340-1
programmable digital pwm I2C multiphase

Abstract: No abstract text available
Text: ‚· Slow OCP for Thermal Design Current ( TDC ) protection  Programmable ICRITICAL signal  I2C , and the CHL8203/13/14 includes thermistor based temperature sensing with VRHOT signal. ï


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PDF CHL8203/12/13/14 CHL8212/13/14) CHL8203) CHL8225 CHL8213/14) CHL8203/13/14) CHL8203 CHL8212 CHL8203 programmable digital pwm I2C multiphase
tdc 310

Abstract: Z80A Z80L
Text: ) 380 150 16 TdlEI(IEOf) IEI ito IEO J Delay 380 150 17 TdC (INT) Clock ttoÌNTI Delay 510 200 18 TdlO(W/RWf) ÌORQ * or CE i toW/RDY 1 Delay (Wait Mode) 760 300 19 TdC (W/RR) Clock t toWRDY I Delay (Ready Mode) 310 120 20 TdC (W/RWz) Clock * toW/RDY Float Delay (Wait Mode) 390 150 21 Th Any


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PDF Z8340 40-pin Z8340-1 Z8340-3 tdc 310 Z80A Z80L
2003 - motherboard power delivery

Abstract: motherboard vrm timing diagram Intel socket 478 PIN LAYOUT 478 SOCKET PIN LAYOUT start socket-478 motherboard socket-478 motherboard circuit mobile 478 SOCKET PIN LAYOUT socket-478 motherboard start socket-478 motherboard VRD10
Text: Voltage Requirements R Table 4. Vcc Regulator Design Parameters Iccmax VR TDC Dynamic Icc , ability to support 80 A of VR TDC , 91 A of electrical peak current, satisfy overshoot requirements of , the regulator. This is accomplished by placing a thermistor in the feedback network (tuned with a , . The thermal compensation circuit is to be validated by running the regulator at VR TDC for 30 to 45 , above VR TDC can easily result in component failure and/or board damage. VRD Design Guide 23


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2005 - Not Available

Abstract: No abstract text available
Text: ( TDC ) mark on the timing tab. See a service manual for these locations. NOTE: Removing the spark , ) with the TDC mark on the timing tab. NOTE: Once you are finished with Step 4, DO NOT turn the , ) with the TDC mark on the timing tab, to allow the distributor to seat fully. Step 3 Rotate the , 42 Series 609 208M 307M 29349 50 Series 609 209M 309 2091M 29349 57 Series 609 209M 310 , Odd-Fire Engines) 50 Series 609 270 309 29349 57 Series 609 270 310 29349 29332 4 Cylinder


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PDF pre-1966 pre-1968 2094M
1999 - Not Available

Abstract: No abstract text available
Text: Definitions Signal POS Mode: TDAT[ 31.0 ] ATM Mode: TUDATA[ 31.0 ] STS-48c Physical Layer Packet/ATM Over , ] is MSB. POS Mode: TPRTY is the odd/even (programmable, default odd) parity bit over TDAT[ 31.0 ]. The , (programmable, default odd) parity bit over TUDATA[ 31.0 ], driven by the ATM layer. The signal is only valid , / Transmit Clock Looped Receive Packet Data Bus / Receive Cell Data Bus O TTL POS Mode: RDAT[ 31.0 ] ATM Mode: RUDATA[ 31.0 ] O TTL POS Mode: Four-octet true data driven from PHY to packet layer


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PDF VSC9112 STS-48c /STM-16c STS-192/STM-64 G52210-0,
2008 - adp3121

Abstract: No abstract text available
Text: 1500 pF X7R 69.8 k 4.7 uF 4.99 k 35.7 k 82.5 k ADP3121 10 nF 100 k Thermistor 1 , IMON Total Current Output Pin. 10 TTSENSE VR Temperature Sense Input. An NTC thermistor , objectives of the system, as follows: • Output inductor DCR sensing without a thermistor for lowest cost. • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor , 900 mV at the TDC current of the processor. This means that the RIMON resistor should be chosen as


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PDF ADP4100 ADP4100 ADP4100/D adp3121
2006 - LV23200T

Abstract: No abstract text available
Text: 310 mVrms Signal-to-noise ratio 1 S/N1 VIN = 23dBµV 15 20 Signal-to-noise ratio 2 , data output (OUT) tSU, tHD, tEL, tES, tEH0.75µs tDC , tDH<0.35µs CL : Normally Hi tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC I2 DO I1 , B1 B2 B3 A0 A1 A2 A3 tDC DO tDC I2 I1 tDH UL C3 C2 C1 C0 (Note) DO pin is an Nch open drain pin, so that the data varying time ( tDC and tDH) differs depending on


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PDF ENN8301 LV23200T LV23200T
1995 - ALK 3213

Abstract: Nippon capacitors ADI1251 MC145426 MC145425P MC145425DW MC145425 MC145422 MC145421P MC145421DW
Text: 19 CLKOUT D2I 7 18 TDC /RDC D2I 7 DCLK 8 17 CCI D1O 9 16 , CONTROL 11 16 19 D2O DCLK D1O TDC /RDC Tx 14 TE1 TE2 D2 2 7 D2 6 21 , O IC M E- TDC /RDC Data Clocks (for Master) C IN 4.5 5.0 , - OR8.0 T -C - U D , the input signal to the device with no dcE offset. edge aligned with the TDC /RDC data clock input , data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Freescale


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* ALK 3213 Nippon capacitors ADI1251 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW
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