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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC4069EDC#PBF Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC#TRPBF Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC#TR Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC#TRMPBF Linear Technology LTC4069 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC-4.4#PBF Linear Technology LTC4069-4.4 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC4069EDC-4.4#TR Linear Technology LTC4069-4.4 - Standalone 750mA Li-Ion Battery Charger in 2 x 2 DFN with NTC Thermistor Input; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C

TDC 310 NTC Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2011 - TDC 310 NTC thermistor

Abstract:
Text: , IMAXA = 39A 27.0 30.0 33.0 RSENSE = 0.75mI, IMAXA = 36A 25.0 28.0 31.0 RSENSE = , RSENSE = 0.85mI, IMAXA = 39A 30.0 33.0 36.0 RSENSE = 0.85mI, IMAXA = 36A 28.0 31.0 , 31.0 34.0 37.0 RSENSE = 0.95mI, IMAXA = 30A 25.0 28.0 31.0 RSENSE = 0.95mI, IMAXA , 33.0 RSENSE = 0.75mI, IMAXB = 36A 25.0 28.0 31.0 RSENSE = 0.75mI, IMAXB = 23A 15.0 , 30.0 33.0 36.0 RSENSE = 0.85mI, IMAXB = 36A 28.0 31.0 34.0 RSENSE = 0.85mI, IMAXB


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PDF VR12/IMVP7 MAX17411/MAX17511/MAX17511C/MAX17511N/ MAX17511T VR12/IMVP-7 MAX17411 MAX17511/MAX17511C/MAX17511N/MAX17511T MAX17411/MAX17511/ MAX17511C/MAX17511N/MAX17511T TDC 310 NTC thermistor TDC 310 NTC TDC 210 NTC TDC 310 thermistor 1/TDC 310 NTC thermistor MAX17511 GFX 2AA IMVP7 Ps3 MOTHERBOARD CIRCUIT diagram
2009 - TDC 310 thermistor

Abstract:
Text: CCP22 RFB11 CCP12 Load Line NTC Thermistor; Locate close to VDD Power Stage VDD SENSE + VDD , Temperature Compensation A negative temperature coefficient ( NTC ) thermistor can be used for output1 inductor


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PDF IR3521 IR3521 TDC 310 thermistor TDC 310 NTC thermistor TDC 310 NTC smd code LE npn IR3521MTRPBF TDC+310+thermistor 315mV U-345 CVCC11 CCP22
usb 3g modem circuit

Abstract:
Text: TDC Development Support Board for Siemens Wireless Modules Introduction The TDC Development , a time. Last update - 17th April 2008 TDC Development Support Board for Siemens Wireless , installed inside the computer being used. Last update - 10th May 2007 TDC Development Support Board for , circuit which allows for a certain amount of experimentation including the use of super caps. TDC , counterparts. To make it easy to find the signals required TDC have included as many useful labels onto the


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PDF G60-ML usb 3g modem circuit 6 pin sim holder pinout siemens mc55i mc55i CTS153 siemens TC65 Siemens MC75 TC63 modem siemens mc55i manual siemens regulator power supply dc volt output
TDC 310 NTC thermistor

Abstract:
Text: CCP12 RFB13 Load Line NTC Thermistor; Locate close to VDD Power Stage To VDD Remote Sense , Temperature Compensation A negative temperature coefficient ( NTC ) thermistor can be used for output1 inductor


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PDF IR3521 IR3521 TDC 310 NTC thermistor TDC 310 thermistor
VMEbus Handbook

Abstract:
Text: SIS Documentation SIS3400 CDMSII TDC /Time Stamper SIS3400 CDMS II VME TDC /Time Stamper , 20.03.02 Page 1 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper Revision Table , CDMSII TDC /Time Stamper 1 Table of contents 1 2 3 Table of contents , .33 Page 3 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper 10.1 Single Wire mode , .46 Page 4 of 47 SIS Documentation SIS3400 CDMSII TDC /Time Stamper 2 Introduction The


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PDF SIS3400 SIS3400 VME64x. VME64xP rs485 VMEbus Handbook LEMO VME COnnector lemo 9 pin connector VME64X STR 8124 0x22C LEMO 7 pin Harting 02 01
tdc 310

Abstract:
Text: 1,107,072 1, 310 ,035 MG7xPB26 548 804 2,680 2,154,720 969,624 1,249,738 1 , 984 3,280 3,227,520 1,355,558 1,678, 310 2,001,062 MG7xPB34 708 1,044 3,480 , Data Check (CDC) · Delay Processor · Test Data Check ( TDC ) Oki Test Data Check program ( TDC ) verifies test vector rules. Sun and HP9000/7xx Sun and PC TDC TPL / EDIF Tester Interface


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PDF MG113P/114P/115P/73P/74P/75P MG113P/73P MG114P/74P MG115P/75P MG7xPB08 MG7xPB10 MG7xPB12 MG7xPB14 MG7xPB16 HP9000/7xx, tdc 310 HP9000 RS6000 tpl 624
1999 - ATM machine using microcontroller

Abstract:
Text: TCK TMS TRSTB OE JTAG TAP TUDATA[ 31.0 ] TUPRTY TUSOC TUENB* TUFULL*/TUCLAV TUCLK TUCLKO RUDATA[ 31.0 , Interface Symbol fRLCLK Tdc , RLCLK Tr/f, RLCLK Ts, RLIN Th, RLIN Tp, RXRC fRXRCLK Tdc , RXRCLK , Interface Symbol fTLCLK Tdc , TLCLK STS-48 Physical Layer ATM UNI/NNI Device Description TLCLK+/- clock frequency (nominal) TLCLK+/- duty cycle Min 40 Tdc , TLCLK - (550ps x fTLCL K) 1.0 1.0 0 30 Max 155.52 60 Unit MHz % Tdc , TLCLKO TLCLKO+/- duty cycle % Tr/f, TLCLK Tp, TLOUT Tp


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PDF VSC9110 STS-48c STM-16c STS-48 GR-253-CORE VSC9110 G52198-0, ATM machine using microcontroller
2012 - GFX DIODE

Abstract:
Text: graphics (GFX) or system agent (VSA) Single NTC design for TM, LL and IMON thermal compensation (for each , L6758A Contents 8 Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . , ENDRV ST L6758A PWM1 CS1P CS1N EN PWM NTC (NTHS0805N02N6801) Place close to SPhase inductor VRRDY SVRRDY VR_HOT VCC5 VCC NTC (NTHS0805N02N6801) BOOT CHF UGATE PHASE LGATE GND RG LS2 R HS2 L2 RG LS1 R HS1 L1 , with proper network embedding NTC to the single-phase power section. The IC senses the power section


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PDF L6758A GFX DIODE NTHS0805N02N6801 single phase SPWM IC L6758A diode gfx L6758 intel IMVP7 IMVP7 GFX diode 610 gfx 68
2013 - Not Available

Abstract:
Text: (GFX) or system agent (VSA) • Single NTC design for TM, LL and IMON thermal compensation (for each , Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . 30 8.1 8.2 Thermal , PHASE LGATE LS1 R C GND CSREF RSREF NTC (NTHS0805N02N6801) Place close to SPhase , SVRRDY VR_HOT TM CSI RG +12V CDEC VCC5 VCC RSFB RSI BOOT NTC , monitor sensor. Connect with proper network embedding NTC to the single-phase power section. The IC


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PDF L6758A L6758A VFQFPN48 DocID023298
Not Available

Abstract:
Text: 17 18 19 20 21 Symbol TcC TwCh TIC TrC TwCI TsAD(C) TsCS(C) TdC (DO) TsDI(C) TdRD(DOz) TdlO(DOI) TsM1(C) TslEI(IO) TdM1(IEO) TdlEI(IEOr) TdlEI(IEOf) TdC (INT) TdlO(W/RWf) TdC (W/RR) TdC (W/RWz) Th , 860 540 510 760 380 380 510 760 310 390 0 0 210 200 300 150 150 200 300 120 150 470 410 610 610 50 230


OCR Scan
PDF Z8340 40-pin Z8340-1 Z8340-3
1995 - TDC 310

Abstract:
Text: 18 TDC /RDC D2I 7 18 XTL DCLK 8 17 CCI DCLK 8 17 CCI D1O , 3 LI D1I RE2 Rx RE1 B CHANNEL BUFFERS 12 VD D2I D2O DCLK D1O TDC /RDC , CCI Clock Frequency - - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* TDC 310 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW LINE FEED ISDN
1995 - Nippon capacitors

Abstract:
Text: 18 TDC /RDC D2I 7 18 XTL DCLK 8 17 CCI DCLK 8 17 CCI D1O , 3 LI D1I RE2 Rx RE1 B CHANNEL BUFFERS 12 VD D2I D2O DCLK D1O TDC /RDC , CCI Clock Frequency - - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* Nippon capacitors MC145425DW MC145422 MC145421P MC145421DW LINE FEED ISDN DSA005307 ADI1251
1995 - 6D120

Abstract:
Text: RE1 D1I 6 19 CLKOUT D2I 7 18 TDC /RDC D2I 7 18 XTL DCLK 8 , D2O DCLK D1O TDC /RDC B2 13 15 B CHANNEL BUFFERS DEMODULATOR 14 Tx TE1 TE2 , MHz TDC /RDC Data Clocks (for Master) - 0.128 - 4.1 MHz - 0.016 - 4.1 , approximately leading edge aligned with the TDC /RDC data clock input pin. CCI High­Speed Clock Input (Pin 17 , B channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* 6D120 MC145426 MC145425P MC145425DW MC145422 MC145421P MC145421DW Nippon capacitors
LINE FEED ISDN

Abstract:
Text: CHANNEL BUFFERS 20 21 19 10 18 >1, 14 D2I D1I RE2 Rx RE1 -D20 DCLK -010 - TDC /RDC Tx -TEI , Clock Frequency - 8.192 8.29 MHz TDC /RDC Data Clocks (for Master) - 0.128 - 4.1 MHz DCLK - 0.016 4.1 , the TDC /RDC data clock input pin. CCI —HIGH-SPEED CLOCK INPUT (PIN 17) An 8.192 MHz clock should , channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) MOTOROLA 4 , ) B channel data is input on this pin and is controlled by the RE1, RE2, and TDC /RDC pins. (See RE1


OCR Scan
PDF MC146421/D MC145421 MC145425 MK145BP, MC145421Â MC145425 A19596 C41268 LINE FEED ISDN MC145422
Not Available

Abstract:
Text: 18 ] TDC /RDC 17 ] CCI 16 ] MSI 15 ] TE1 14 ] TE2 13 ] Tx MC145425 - SLAVE (PLASTIC AND SOG , Note) CCI Clock Frequency TDC /RDC Data Clocks (for Master) DCLK Modulation Baud Rate (CCI/16) Pins vdd , during the previous frame. MSI should be approximately leading edge aligned with the TDC /RDC data clock , device. The B channel data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Rx Receive Data Input (Pin 21) B channel data is input on this pin and is controlled by the RE1, RE2, and TDC


OCR Scan
PDF MC145421 MC145425 MC145421 b3b72S3
Not Available

Abstract:
Text: 140 590 860 540 510 760 380 380 510 760 310 390 0 0 210 200 300 150 150 200 300 120 150 50 230 340 , TwCh TfC TrC TwCI TsAD(C) TsCS(C) TdC (DO) TsDI(C) TdRD(DOz) TdlO(DOI) TsM1(C) TslEI(IO) TdM1(IEO) TdlEI(IEOr) TdlEI(IEOf) TdC (INT) TdlO(W/RWf) TdC (W/RR) TdC (W/RWz) Th Parameter Clock Cycle Time Clock


OCR Scan
PDF QQG5M05 T-75-37-07 0D0S40t, 40-pln Z8340-1
tdc 310

Abstract:
Text: ) 380 150 16 TdlEI(IEOf) IEI ito IEO J Delay 380 150 17 TdC (INT) Clock ttoÌNTI Delay 510 200 18 TdlO(W/RWf) ÌORQ * or CE i toW/RDY 1 Delay (Wait Mode) 760 300 19 TdC (W/RR) Clock t toWRDY I Delay (Ready Mode) 310 120 20 TdC (W/RWz) Clock * toW/RDY Float Delay (Wait Mode) 390 150 21 Th Any


OCR Scan
PDF Z8340 40-pin Z8340-1 Z8340-3 tdc 310 Z80A Z80L
2012 - L6751

Abstract:
Text: graphics (GFX), system agent (VSA) or Northbridge (VDDNB) Single NTC design for TM, LL and Imon thermal , . . . . . . . . . . . . . . . 39 8 Single NTC thermal monitor and compensation . . . . . . . . , SVRRDY VR_HOT CDEC VCC BOOT CHF VCC5 NTC (NTH S0805N02N6 801) (Clo se to the hotspot) TM L6747 UGATE PHASE LGATE HS2 L2 R EN PWM LS2 C VCC5 NTC (NTH S0805N02N6 801) (Clo se to , monitor sensor. Connect with proper network embedding NTC to the multi-phase power section. The IC senses


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PDF L6751 L6751 DPM12 DPM23 GFX SE DIODE intel IMVP7 Northbridge tm-12v alarm
2012 - L6759

Abstract:
Text: controller: ­ 3-phase for VDDQ ­ 1-phase for VTT Single NTC design for TM, LL and Imon thermal compensation , . . . . . . . . . . . . . . . 31 8 Single NTC thermal monitor and compensation . . . . . . . . , IMON ALERT# SVDATA SCSN SCSP SPWM NTC (NTHS0805N02N6801) VR_RDY SVR_RDY VR_HOT TM VRRDY SVRRDY VR_HOT , UGATE EN SLS ( NTC Optional) LGATE PWM RG VR12 LOAD UNCORE CORE CSOUT CSMLCC , # SCSN SCSP SPWM VR_RDY SVR_RDY VR_HOT TM VRRDY SVRRDY VR_HOT VCC5 NTC (NTHS0805N02N6801) CIMON


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PDF L6759D L6759 rg86 L6759D intel drMOS 4.0 intel IMVP7
2012 - intel IMVP7

Abstract:
Text: graphics (GFX), system agent (VSA) or Northbridge (VDDNB) Single NTC design for TM, LL and Imon thermal , . . . . . . . . . . . . . . . . 37 8 Single NTC thermal monitor and compensation . . . . . . . , PHASE LGATE GND RG LS2 R HS2 L2 VCC5 NTC (NTHS0805N02N6801) (Close to the hot spot) TM EN PWM C VCC5 NTC (NTHS0805N02N6801) (Close to the hot spot) STM +12V SIMON RSIMON PWM3 , positive offset to the regulation. Thermal monitor sensor. Connect with proper network embedding NTC to the


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PDF L6751B intel IMVP7
2013 - DPM23

Abstract:
Text: (GFX), system agent (VSA) or Northbridge (VDDNB)  Single NTC design for TM, LL and IMON thermal , . . . . . . . . . . . . . . . . . . . . . . . 37 Single NTC thermal monitor and compensation . . , NTC to the multi-phase power section. The IC senses the power section temperature and uses the , . Thermal monitor sensor. Connect with proper network embedding NTC to the single-phase power section. The


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PDF L6751C WPLGA72 DocID025037 DPM23
2005 - Not Available

Abstract:
Text: ( TDC ) mark on the timing tab. See a service manual for these locations. NOTE: Removing the spark , ) with the TDC mark on the timing tab. NOTE: Once you are finished with Step 4, DO NOT turn the , ) with the TDC mark on the timing tab, to allow the distributor to seat fully. Step 3 Rotate the , 42 Series 609 208M 307M 29349 50 Series 609 209M 309 2091M 29349 57 Series 609 209M 310 , Odd-Fire Engines) 50 Series 609 270 309 29349 57 Series 609 270 310 29349 29332 4 Cylinder


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PDF pre-1966 pre-1968 2094M
1999 - Not Available

Abstract:
Text: Definitions Signal POS Mode: TDAT[ 31.0 ] ATM Mode: TUDATA[ 31.0 ] STS-48c Physical Layer Packet/ATM Over , ] is MSB. POS Mode: TPRTY is the odd/even (programmable, default odd) parity bit over TDAT[ 31.0 ]. The , (programmable, default odd) parity bit over TUDATA[ 31.0 ], driven by the ATM layer. The signal is only valid , / Transmit Clock Looped Receive Packet Data Bus / Receive Cell Data Bus O TTL POS Mode: RDAT[ 31.0 ] ATM Mode: RUDATA[ 31.0 ] O TTL POS Mode: Four-octet true data driven from PHY to packet layer


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PDF VSC9112 STS-48c /STM-16c STS-192/STM-64 G52210-0,
2006 - LV23200T

Abstract:
Text: 310 mVrms Signal-to-noise ratio 1 S/N1 VIN = 23dBµV 15 20 Signal-to-noise ratio 2 , data output (OUT) tSU, tHD, tEL, tES, tEH0.75µs tDC , tDH<0.35µs CL : Normally Hi tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC I2 DO I1 , B1 B2 B3 A0 A1 A2 A3 tDC DO tDC I2 I1 tDH UL C3 C2 C1 C0 (Note) DO pin is an Nch open drain pin, so that the data varying time ( tDC and tDH) differs depending on


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PDF ENN8301 LV23200T LV23200T
1995 - ALK 3213

Abstract:
Text: 19 CLKOUT D2I 7 18 TDC /RDC D2I 7 DCLK 8 17 CCI D1O 9 16 , CONTROL 11 16 19 D2O DCLK D1O TDC /RDC Tx 14 TE1 TE2 D2 2 7 D2 6 21 , O IC M E- TDC /RDC Data Clocks (for Master) C IN 4.5 5.0 , - OR8.0 T -C - U D , the input signal to the device with no dcE offset. edge aligned with the TDC /RDC data clock input , data is under the control of TE1, TE2, and TDC /RDC. (See TE1, TE2 description.) Freescale


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PDF MC145421/D MC145421 MC145425 MC145421 MC145425 MC145421/D* ALK 3213 Nippon capacitors MC145425P MC145425DW MC145422 MC145421P MC145421DW ADI1251
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