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UltraSparc T1

Abstract: No abstract text available
Text: STP1030A S un M ic r o e l e c t r o n ic s July 1997 UltraSPARC"-! DATA SHEET First Generation SPARC v9 64-Bit M icroprocessor With VIS D e s c r ip t io n The STP1030A , -bit RISC architecture. The STP1030A is capable of sustaining the execution of up to four instructions per , branch) can be issued in the same group. The STP1030A supports 2D as well as 3D graphics, image , "! First Generation SPARC v9 64-Bit Microprocessor With VIS STP1030A Prefetch and Dispatch Unit (PDU


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PDF STP1030A 64-Bit STP1030A, STP1030A 256-Pin STP1030ABGA-167 UltraSparc T1
1997 - GIGABYTE G31

Abstract: SPARC v9 architecture BLOCK DIAGRAM stream register cache coherency snoop filter AF10 AH22 "64-Bit Microprocessor" STP1030 d4ta
Text: STP1030A July 1997 UltraSPARCTM-I DATA SHEET First Generation SPARC v9 64-Bit Microprocessor With VIS DESCRIPTION The STP1030A , UltraSPARC­I, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030A is capable of , STP1030A supports 2D as well as 3D graphics, image processing, video compression and decompression, and , STP1030A Prefetch and Dispatch Unit (PDU) Memory Management Unit (MMU) Instruction Cache and


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PDF STP1030A 64-Bit STP1030A, STP1030A 256-Pin GIGABYTE G31 SPARC v9 architecture BLOCK DIAGRAM stream register cache coherency snoop filter AF10 AH22 "64-Bit Microprocessor" STP1030 d4ta
supersparc

Abstract: STP2003QFP STP3010PGA 805-0086-02 lcd cross reference PMC cross reference STP2013 ATM622-S STP3010 STP2014QFP
Text: S un M icroelectronics July 1997 Data Sheets listed by Marketing Part Cross Reference List M a r k e t in g P a r t 501-4126 501-4127 SME1040BGA SME2411BGFA SME4050BGA STP1012PGA-85, -110 STP1021APGA STP1030A STP1031 LGA-250 STP1080A STP1081 STP1091 STP1100BGA STP2000QFP STP2001QFP STP2002QFP STP2003QFP STP2011PGA-50 STP2012QFP STP2013PGA-50 STP2014QFP STP2016QFP STP2018TAB-50 STP2021PLCC STP2024QFP STP2200ABGA STP2202ABGA STP2210QFP Fast Frame Buffer (3D) Fast Frame Buffer (2D) UltraSPARC-ll/ 300 MHz


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PDF SME1040BGA SME2411BGFA SME4050BGA STP1012PGA-85, STP1021APGA STP1030A STP1031 LGA-250 STP1080A STP1081 supersparc STP2003QFP STP3010PGA 805-0086-02 lcd cross reference PMC cross reference STP2013 ATM622-S STP3010 STP2014QFP
lcd cross reference

Abstract: SME2411BGA SuperSPARC STP2003QFP PMC cross reference 805-0086-02 ATM622-S STP3010 STP2014QFP STP2024QFP
Text: Controller (USC) UPA to PCI Bus Interface (U2P) UPA to SBus Interface (U2S) Video Buffer-50 MHz STP1030A


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PDF ATM622-S 85/110MHz UltraSPARC-1167 UltraSPARC-11 UltraSPARC-ll/300 Buffer-50 STP1030A STP5111A-200 STP5110A-167 lcd cross reference SME2411BGA SuperSPARC STP2003QFP PMC cross reference 805-0086-02 STP3010 STP2014QFP STP2024QFP
SRAM

Abstract: ultrasparc
Text: allow for upgrades to higher speed mod ules. The estimated maximum power consumption of the STP1030A is , Bus, 83 MHz UPA module with UltraSPARC-i ( STP1030A ), 0.5 MB SRAMs, and UDBs. Document Part Number


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PDF 32kx36 32kx36 MC100LVE111 STP5110AUPA-167 STP1030A) STP5110A SRAM ultrasparc
STP51

Abstract: No abstract text available
Text: modules. The estimated m axim um pow er consumption of the STP1030A is 30 Watts @ 200 MHz. July 1997 , CPU, 100 MHz UPA · +- 200 MHz CPU Bus, 100 MHz UPA module with UltraSPARC-l ( STP1030A ), 1 MB SRAMs


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PDF 32kx36 MC10ELV111 STP5111AU PA-200 STP1030A) STP51
STP5111

Abstract: No abstract text available
Text: for upgrades to higher speed modules. The estimated maximum power consumption of the STP1030A is 30 , module with UltraSPARC-I ( STP1030A ), 1 MB SRAMs, and UDBs. Document Part Number: 802-7433-02 July


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PDF 32kx36 64kxl8 MC10ELV111 5111AUPA-200 STP1030A) STP5111
1997 - MC100LVE111

Abstract: SPARC v9 architecture BLOCK DIAGRAM
Text: . The estimated maximum power consumption of the STP1030A is 30 Watts @ 167 MHz. 12 July 1997 , MHz UPA module with UltraSPARC-I ( STP1030A ), 0.5 MB SRAMs, and UDBs. Document Part Number: STP5110A


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PDF STP5110A 32kx36 32kx36 MC100LVE111 STP5110AUPA-167 STP1030A) SPARC v9 architecture BLOCK DIAGRAM
Not Available

Abstract: No abstract text available
Text: ption of the STP1030A is 30 Watts @ 167 MHz. 12 S un M icroelectronics July 1997 , MHz CPU, 83 MHz UPA Description 167 MHz CPU Bus, 83 MHz UPA m odule with UltraSPARC-l ( STP1030A


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PDF STP5110A 32kx36 32kx36 MC100LVE111 5110AUPA-167 STP1030A)
1997 - 64KX1

Abstract: No abstract text available
Text: . The estimated maximum power consumption of the STP1030A is 30 Watts @ 200 MHz. ±100 July 1997 , 200 MHz CPU Bus, 100 MHz UPA module with UltraSPARC-I ( STP1030A ), 1 MB SRAMs, and UDBs. Document


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PDF STP5111A 32kx36 64kx18 MC10ELV111 STP5111AUPA-200 STP1030A) 64KX1
UltraSPARC ii

Abstract: No abstract text available
Text: od ules. The estimated m axim um pow er consumption of the STP1030A is 30 Watts @ 167 MHz. 12 S , ( STP1030A ), 0.5 MB SRAMs, and UDBs. Document Part Number: STP5110A 18 S un M ic r o e le c


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PDF STP5110A 32kx36 32kx36 MC100LVE111 STP511 STP51 OAUPA-167 STP1030A) UltraSPARC ii
Not Available

Abstract: No abstract text available
Text: consumption of the STP1030A is 30 Watts @ 200 MHz. July 1997 S un M icroelectronics STP5111A T , , 100 MHz UPA Description 200 MHz CPU Bus, 100 MHz UPA m odule w ith UltraSPARC-l ( STP1030A ), 1 MB


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PDF STP5111A 32kx36 MC10ELV111 PA-200 STP1030A)
GIGABYTE G31

Abstract: SPARC v9 architecture BLOCK DIAGRAM gigabyte p31 187U UltraSPARC ii TP1030A
Text: S un M icro electro nics July 1997 U l t r a S P A R C "-! DATA SHEET D e s c r ip t io n First Generation SPARC v9 64-Bit Microprocessor With VIS The STP1030A , -bit RISC architecture. The STP1030A is capable of sustaining the execution of up to four instructions per , branch) can be issued in the same group. The STP1030A supports 2D as well as 3D graphics, image , provides STP1030A with its primary clock source and is the positive differential clock input. This pin


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PDF 64-Bit STP1030A, STP1030A 256-Pin STP1030ABGA-167 STP1030ABGA-200 GIGABYTE G31 SPARC v9 architecture BLOCK DIAGRAM gigabyte p31 187U UltraSPARC ii TP1030A
UltraSPARC IIIi

Abstract: UltraSPARC iie ultrasparc AF5A
Text: ( HighrPer)ormance, 167 & 200 MHz, 64-bit RISC Processor Data Sheet O c t o b e r 1 996 STP1030A S un , -bit RISC architecture. T he STP1030A is capable of sustaining the execution o f up to four instructions p , and after a conditional branch) can be issued in the sam e group. T he STP1030A supports 2D as w ell , Reference - Clock Interface CLKA I This pin provides STP1030A with its prim ary clock source and is the positive differential clock input. This pin provides STP1030A with its prim ary clock source and


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PDF 64-bit STP1030A P1030A STP1030A UltraSPARC IIIi UltraSPARC iie ultrasparc AF5A
1997 - SME2411BGA-66

Abstract: X1059A SEU1L-170-0 PCMCIA SRAM Memory Card 512k SPEC95 STP1080ABGA100 Sun Ultra AX STP3010PGA STP1030ABGA167 STP2024QFP
Text: P roduct line Card SPARC Processors Processor Part Number Speed SPEC95 int/fp UltraSPARC-I STP1030ABGA-167 167MHz 7.1/11.0 STP1030ABGA-200 200MHz 8.4/12.8 STP1080ABGA-83 83MHz N/A STP1080ABGA-100 100MHz N/A SME1040BGA-266 266MHz 9.9/12.6 (est.) SME1040BGA-300 300MHz 11/14 (est.) microSPARC-II STP1012PGA-110 110MHz 1.6/2.0 (est.) microSPARC-IIep* STP1100BGA-100 100MHz N/A STP1100BGA-133 133MHz 276K Drystones 156 DMIPS


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PDF SPEC95 STP1030ABGA-167 167MHz STP1030ABGA-200 200MHz STP1080ABGA-83 83MHz STP1080ABGA-100 100MHz SME1040BGA-266 SME2411BGA-66 X1059A SEU1L-170-0 PCMCIA SRAM Memory Card 512k STP1080ABGA100 Sun Ultra AX STP3010PGA STP1030ABGA167 STP2024QFP
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