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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
74SSTL16837ADGGRG4 74SSTL16837ADGGRG4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC, TSSOP-64
74SSTL16857DGGRG4 74SSTL16857DGGRG4 ECAD Model Texas Instruments SSTL SERIES, 14-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
SN74SSTL16837ADGGR SN74SSTL16837ADGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16837ADGGRE4 74SSTL16837ADGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
SN74SSTL16837DGGR SN74SSTL16837DGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, SSOP-64
74SSTL16847DGGRE4 74SSTL16847DGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

SSTL_18 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Text: PLLs use pseudo-differential SSTL_18 signaling for the address bus (series stub terminated logic, 1.8 , 1D C1 R DODT 1D C1 R DCS 1D C1 R QCKEA } 1.8 -V typical supply voltage } SSTL_18 , quality. } 1.8 -V typical supply voltage } SSTL_18 signaling } Double Data Rate (DDR) } 400- to 667 , voltage } SSTL_18 signaling } Double Data Rate (DDR) } 400- to 800-MT/s data rates } 200- to 400 , 25 x 1.8 0.5 0.5 0 to +70 basic DDR2 register LFBGA-96 HVQFN-56 SSTL_18 SSTL_18


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PDF PC100 PC133 PCK2509 PCK2510 DDR200 DDR266 DDR333 DDR400 PCKVF857 DDR2-400 DDR2 SSTL class SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 hp SSTU32866
HSTL standards

Abstract: DDR2 sstl_18 class I 15-V SSTL-18
Text: Terminated Logic for 1.8 -V ( SSTL_18 ). The SSTL- 18 I/O standard is a 1.8 -V memory bus standard used for , Series Terminated Logic for 1.8 -V ( SSTL_18 ). The differential SSTL- 18 I/O standard is a 1.8 -V standard , Application LVTTL General purpose LVCMOS General purpose 2.5 V General purpose 1.8 V , and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL- 18 Class I DDR2 SDRAM SSTL- 18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8


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PDF SII52004-4 HSTL standards DDR2 sstl_18 class I 15-V SSTL-18
CMOS applications handbook

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Text: devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL- 18 , SSTL-2, and LVDS , 3.3 V/ 2.5 V 2.5 V v v v v v 1.8 -V LVTTL and LVCMOS Single ended 1.8 V/ 1.5 V 1.8 V v v v v v 1.5-V LVCMOS Single ended 1.8 V/ 1.5 V 1.5 V v , SSTL-2 class II Voltage referenced 2.5 V 2.5 V v v v v v SSTL- 18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL- 18 class II Voltage referenced


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PDF CII51010-2 SSTL-18, CMOS applications handbook ttl to mini-lvds EP2C20 EP2C35 EP2C50 SSTL-18
2009 - SSTL-18

Abstract: EPM2210F256FBGA DDR2 SSTL class g22 touch 3C120F780 AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
Text: : 713,764 / 3,981,312 ( 18 %) Processor Nios II/f processor core Nominal metrics: 113 DMIPS , ) Input 2.5 V top_clkin_125 A14 125-MHz crystal oscillator Input Input 1.8 V top_clkin_50 AH15 50-MHz crystal oscillator Input Input 1.8 V Nios II 3C120 Microprocessor , ) Output 1.8 V top_we_n_to_the_max2 C15 Write enable (active low) Output 1.8 V top_oe_n_to_the_max2 E25 Output enable (active low) Output 1.8 V Bidirectional SSTL- 18 Class I Top


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PDF 3C120 DS-01002-1 3C120F780 3C120 SSTL-18 EPM2210F256FBGA DDR2 SSTL class g22 touch AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
HSTL standards

Abstract: SSTL-18 class sstl 15-V AGX52008-1 APEX20KC
Text: JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V ( SSTL_18 ). The SSTL- 18 I/O standard , standard is formulated under the JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V ( SSTL_18 , purpose 1.8 V General purpose 1.5 V General purpose 3.3-V PCI PC and embedded system , SSTL- 18 Class I DDR2 SDRAM SSTL- 18 Class II DDR2 SDRAM 1.8 -V HSTL Class I SRAM interfaces 1.8 -V HSTL Class II SRAM interfaces 1.5-V HSTL Class I SRAM interfaces 1.5-V HSTL


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PDF AGX52008-1 HSTL standards SSTL-18 class sstl 15-V APEX20KC
1999 - A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , -BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003 description/ordering


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
2005 - PC2-5300P-555-12

Abstract: pc2-5300p DDR2 pin out 5300P DDR2-400 HYS72T256322HP PC2-5300
Text: High Temperature Self Refresh All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance , Description SSTL Serial Stub Terminated Logic ( SSTL_18 ) CMOS CMOS Levels OD Open Drain. The , 17 17 18 18 19 23 24 27 28 Rev. 1.0, 2005-11 11102005-QKC8-JBW4 240-Pin Dual-Die , Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply All speed grades , 72 2 ECC 18 14/2/11 Table 4 Components on Modules 1) W Product Type2) DRAM


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PDF HYS72T256322HP 240-Pin DDR2-800 DDR2-667 DDR2-533 DDR2-400 11102005-QKC8-JBW4 PC2-5300P-555-12 pc2-5300p DDR2 pin out 5300P PC2-5300
2003 - A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , -BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003 description/ordering


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Unterminated Line Supports SSTL_18 Data Inputs • • • • • Differential Clock (CLK and CLK , are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The , Incorporated SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Unterminated Line Supports SSTL_18 Data Inputs • • • • • Differential Clock (CLK and CLK , are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The , Incorporated SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864D operates from a differential clock (CLK and CLK). Data , Incorporated SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES623A


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit
2005 - A115-A

Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs · · · , loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 ­ JULY 2005 DESCRIPTION/ORDERING


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PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit A115-A C101 SN74SSTU32864E SN74SSTU32864EZKER
2005 - A115-A

Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER ddr2 DIMM PCB
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs · · · , loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 ­ JULY 2005 DESCRIPTION/ORDERING


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PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit A115-A C101 SN74SSTU32864E SN74SSTU32864EZKER ddr2 DIMM PCB
2004 - A115-A

Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES542 - , Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs D D D Control and , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , SN74SSTU32864C 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES542 - JANUARY 2004


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PDF SN74SSTU32864C 25BIT SCES542 25-Bit 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Unterminated Line Supports SSTL_18 Data Inputs • • • • • Differential Clock (CLK and CLK , are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
Not Available

Abstract: No abstract text available
Text: . Programming flash. Figure 2–8 Programming flash 18 8. Programming complete. Figure 2–9 , pairs CDR-based transceivers, 19 pairs LVDS transmitter channels, and 18 pairs LVDS receiver channels , transmitter channels, and 18 pairs LVDS receiver channels. Additionally, both ports A and B of the HSMC , Description I/O Standard 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 , 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.8 -V(*) 1.8 -V(*) 2.5-V 2.5


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PDF 64-bit
1999 - dimm pcb layout

Abstract: No abstract text available
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CLK and , inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864 , SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit SN74SSTU32864GKER SN74SSTU32864 SCEM343, dimm pcb layout
HSTL standards

Abstract: 15-V SSTL-18
Text: JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V ( SSTL_18 ). The SSTL- 18 I/O standard , Series Terminated Logic for 1.8 -V ( SSTL_18 ). The differential SSTL- 18 I/O standard is a 1.8 -V standard , Application LVTTL General purpose LVCMOS General purpose 2.5 V General purpose 1.8 V , and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL- 18 Class I DDR2 SDRAM SSTL- 18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8


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PDF
2005 - HYS72T512020HR-5-A

Abstract: DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
Text: Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic ( SSTL_18 , Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply , Refresh All inputs and outputs SSTL_ 1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and , Buffer Type Type Function 18 RESET I CMOS Register Reset The RESET pin is connected to , /O Reference Voltage Reference voltage for the SSTL- 18 inputs. 13 Rev. 1.1, 2005-08 02012005


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PDF HYS72T512020HR­ 240-Pin DDR2-667C DDR2-667D DDR2-533C DDR2-400B 02012005-N6JU-ZWV6 HYS72T512020HR-5-A DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
class sstl

Abstract: HSTL standards 15-V AGX52008-1 APEX20KC SSTL-18
Text: JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V ( SSTL_18 ). The SSTL- 18 I/O standard , standard is formulated under the JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V ( SSTL_18 , purpose LVCMOS General purpose 2.5 V General purpose 1.8 V General purpose 1.5 V , -2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL- 18 Class I DDR2 SDRAM SSTL- 18 Class II DDR2 SDRAM 1.8 -V HSTL Class I SRAM interfaces 1.8 -V HSTL Class II SRAM interfaces


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PDF AGX52008-1 class sstl HSTL standards 15-V APEX20KC SSTL-18
2004 - A115-A

Abstract: C101
Text: 74SSTU32864CZKERJ 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES621 - , Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs D D D Control and , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , DALLAS, TEXAS 75265 1 74SSTU32864CZKERJ 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS


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PDF 74SSTU32864CZKERJ 25BIT SCES621 25-Bit 14-Bit A115-A C101
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs · · · · · · · , SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864E , SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCAS802 ­ JULY 2005


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PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit
Supplyframe Tracking Pixel