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2009 - SSTL-18

Abstract: EPM2210F256FBGA DDR2 SSTL class g22 touch 3C120F780 AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
Text: top_oe_n_to_the_max2 E25 Output enable (active low) Output 1.8 V Bidirectional SSTL-18 Class I Top , Negative differential clock Input Bidirectional SSTL-18 Class I top_ddr2top_a[0] J13 Address Output SSTL-18 Class I top_ddr2top_a[1] G18 Address Output SSTL-18 Class I top_ddr2top_a[2] E8 Address Output SSTL-18 Class I top_ddr2top_a[3] D24 Address Output SSTL-18 Class I top_ddr2top_a[4] D7 Address Output SSTL-18 Class I top_ddr2top_a[5


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PDF 3C120 DS-01002-1 3C120F780 3C120 SSTL-18 EPM2210F256FBGA DDR2 SSTL class g22 touch AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
2008 - SM5545

Abstract: MT47H32M8BP-3
Text: No file text available


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PDF SJ/T11363-2006 SM5545 MT47H32M8BP-3
2008 - K1B3216B2E

Abstract: Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
Text: No file text available


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PDF 3SL150 K1B3216B2E Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
2009 - K1B3216B2E

Abstract: Marvell 88e111 schematic 20 pin lcd laptop LTI-SASF546-P26-X1 LDQ-M2212R1 HSMC debug header breakout board for Cyclone III board LCM-S01602DSR/C lcd 30 pin diagram lvds Marvell 88E1111 trace layout guidelines K1B3216B2E-BI70
Text: No file text available


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PDF 3C120 K1B3216B2E Marvell 88e111 schematic 20 pin lcd laptop LTI-SASF546-P26-X1 LDQ-M2212R1 HSMC debug header breakout board for Cyclone III board LCM-S01602DSR/C lcd 30 pin diagram lvds Marvell 88E1111 trace layout guidelines K1B3216B2E-BI70
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
Not Available

Abstract: No abstract text available
Text: No file text available


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PDF 64-bit
CMOS applications handbook

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Text: devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS , SSTL-2 class II Voltage referenced 2.5 V 2.5 V v v v v v SSTL-18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL-18 class II Voltage referenced , SSTL-2 class I or Pseudo class II differential (3) (5) Differential SSTL-18 class I or class II , ) (8) These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs. PCI-X does not


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PDF CII51010-2 SSTL-18, CMOS applications handbook ttl to mini-lvds EP2C20 EP2C35 EP2C50 SSTL-18
1999 - A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , -BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003 description/ordering


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Text: PLLs use pseudo-differential SSTL_18 signaling for the address bus (series stub terminated logic, 1.8 , 1D C1 R DODT 1D C1 R DCS 1D C1 R QCKEA } 1.8-V typical supply voltage } SSTL_18 , quality. } 1.8-V typical supply voltage } SSTL_18 signaling } Double Data Rate (DDR) } 400- to 667 , voltage } SSTL_18 signaling } Double Data Rate (DDR) } 400- to 800-MT/s data rates } 200- to 400 , 25 x 1.8 0.5 0.5 0 to +70 basic DDR2 register LFBGA-96 HVQFN-56 SSTL_18 SSTL_18


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PDF PC100 PC133 PCK2509 PCK2510 DDR200 DDR266 DDR333 DDR400 PCKVF857 DDR2-400 DDR2 SSTL class SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 hp SSTU32866
1999 - dimm pcb layout

Abstract: No abstract text available
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CLK and , inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864 , SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit SN74SSTU32864GKER SN74SSTU32864 SCEM343, dimm pcb layout
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864D operates from a differential clock (CLK and CLK). Data , Incorporated SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES623A


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
2005 - A115-A

Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Supports SSTL_18 Data Inputs · · · · · Differential Clock (CLK and CLK) Inputs Supports LVCMOS , devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset , unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864D operates from a differential clock , WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A ­ FEBRUARY 2005 ­ REVISED APRIL 2005


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit A115-A C101 SN74SSTU32864D SN74SSTU32864DGKER
2005 - SSTL18

Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864D operates from a differential clock (CLK and CLK). Data , Incorporated SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES623A


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit SSTL18
2002 - EN10B

Abstract: No abstract text available
Text: -bit parallel I/O Interface conforms to SSTL_18 Class 1 (also interfaces to 1.8V HSTL or 1.8V LVCMOS) On-chip 8b , -0.250 +50 +10 Typ (1) 0.90 Max 0.97 VDDQ +0.300 Units V V V V V µA µA SSTL_18 DC , SEPTEMBER 2002 ­ REVISED APRIL 2013 TERMINATION AT THE PARALLEL I/O INTERFACE Figure 12. SSTL_18 Class , J2 J1 H4 H2 H1 M3 M2 N3 N2 N1 P2 P1 R4 R2 R1 AA11 AB11 W10 Y10 AA10 AA9 W8 Y8 AA8 AB8 A8 G2 I, SSTL_18 , PullLow I, SSTL_18 , PullLow I, SSTL_18 , PullLow Transmit data word for channel C. In the 10


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PDF DS25C400 SNLS155B DS25C400 10-bit 8b/10b EN10B
2004 - A115-A

Abstract: C101
Text: 74SSTU32864CZKERJ 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES621 - , Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs D D D Control and , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , DALLAS, TEXAS 75265 1 74SSTU32864CZKERJ 25BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS


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PDF 74SSTU32864CZKERJ 25BIT SCES621 25-Bit 14-Bit A115-A C101
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs · · · · · · · , SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864E , SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCAS802 ­ JULY 2005


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PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
2004 - A115-A

Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Supports SSTL_18 Data Inputs · · · · · Differential Clock (CLK and CLK) Inputs Supports LVCMOS , devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset , unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock , BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B ­ JANUARY 2004 ­ REVISED APRIL 2005


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER
2005 - A115-A

Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Supports SSTL_18 Data Inputs · · · · · Differential Clock (CLK and CLK) Inputs Supports LVCMOS , devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset , unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864D operates from a differential clock , WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A ­ FEBRUARY 2005 ­ REVISED APRIL 2005


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PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit A115-A C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
2005 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs · · · · · · · , SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864E , SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCAS802 ­ JULY 2005


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PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit
2003 - A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ , Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential , drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 , -BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 ­ MARCH 2003 description/ordering


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PDF SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER
2004 - Not Available

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit
2004 - S864C

Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line Supports SSTL_18 Data Inputs , required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset (RESET) and LVCMOS , meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data , Instruments Incorporated SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit S864C
2004 - A115-A

Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com , Supports SSTL_18 Data Inputs · · · · · Differential Clock (CLK and CLK) Inputs Supports LVCMOS , devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18 , except the LVCMOS reset , unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock , BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B ­ JANUARY 2004 ­ REVISED APRIL 2005


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PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER
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