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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
74SSTL16847DGGRE4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16847DGGRG4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
SN74SSTL16847DGGR Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16857DGGRG4 Texas Instruments SSTL SERIES, 14-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
SN74SSTL16837ADGGR Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16837ADGGRE4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

SSTL-3 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - GTLP16612

Abstract: SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 sstl lvttl Translator SSTV16857
Text: ® White Paper MAX 7000B I/O MAX 7000B SDRAM GTL+SSTL-2 SSTL-3 I/O GTL+SSTL-2 SSTL-3 I/O LVCMOS LVTTL GTL+ PLD LVTTL I/O MAX 7000B I/O White Paper I/O I/O , http://www.altera.com Literature GTL+ SSTL-2 SSTL-3 Class I Class II M-WP-MAX7000B-01/J , Drivers 2 SSTL-2SSTL-3 Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 universal bus driver class I outputs 20-bit SSTL-3 universal bus driver class II outputs 20-bit SSTL-3


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PDF 7000B 7000B M-WP-MAX7000B-01/J GTLP16612 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 sstl lvttl Translator SSTV16857
SSTL-2

Abstract: LP2994 M08A
Text: SO-8 SSTL-2 SSTL-3 , DS200459 24060 19980108 LP2994 JEDEC SSTL-2 SSTL-3 DDR-SDRAM , RT 1 Class II Figure 2 LP2994 JEDEC SSTL-2 SSTL-3 DDR-SDRAM , VTT SSTL-3 SSTL-2 VDDQ 0.5 1 TT VSENSE V Figure 910 , 3 VSENSE 4 SD VTT LOW 5 VDDQ VDDQ/2


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PDF DS200459-02-JP LP2994 LP2994 DS200459 CSP-9-111C2 SSTL-2 M08A
2006 - PSD01

Abstract: 1523AN4
Text: enough to drive a single load of LVTTL inputs. VDD 330 150 Single LVTTL Load ICS1524 SSTL-3 , SSTL-3 Outputs (DPACLK, CLK, FUNC, LOCK/REF) PA R A ME T E R Output Resistance Maximum Output , Integrated Circuit Systems, Inc. DATA SHEET ICS1524 ICS1524 Dual Output Phase Controlled SSTL_ 3 /PECL Clock Generator Dual Output Phase Controlled SSTL_ 3 /PECL Clock Generator General Description The , DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_ 3 single-ended


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PDF ICS1524 ICS1524 199707558G PSD01 1523AN4
2013 - platform environment control interface

Abstract: CJ41 BR17
Text: ) . 21 3 Technologies , Datasheet 3 4.2 4.3 4.4 Processor Core / Package Power Management , . 44 PCI Express* Port 3 Signals , Port 3 ) may negotiate down to x8, x4, x2, or x1 — x8 port (Port 1) may negotiate down to x4, x2, or , . Terminology (Sheet 1 of 3 ) Term Description ACPI Advanced Configuration and Power Interface ASPM


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PDF LGA2011 i7-4960X i7-49xx i7-48xx platform environment control interface CJ41 BR17
2002 - GTLP16612

Abstract: GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Text: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 transceiver GTLP8T306 SN74GTLPH306 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A (2) 2 20-bit SSTL-3


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PDF 7000B GTLP16612 GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
2006 - SSTL-2

Abstract: LP2994 M08A
Text: SO-8 SSTL-2 SSTL-3 , DS200459 24060 19980108 LP2994 JEDEC SSTL-2 SSTL-3 DDR-SDRAM , RT 1 Class II Figure 2 LP2994 JEDEC SSTL-2 SSTL-3 DDR-SDRAM , VTT SSTL-3 SSTL-2 VDDQ 0.5 1 TT VSENSE V Figure 910 , 3 VSENSE 4 SD VTT LOW 5 VDDQ VDDQ/2


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PDF DS200459-02-JP LP2994 LP2994 DS200459 SSTL-2 M08A
2011 - LGA 2011 Socket diagram

Abstract: LGA2011 LGA 2011 Socket transistors F6 DD52 3930k ddr3 controller BJ13 VCCD01 i7-3930 pcie gen 2 payload
Text: . 27 2 3 4 Datasheet, Volume 1 3 4.2 4.3 4.4 5 6 4.1.3 Integrated Memory , . 43 PCI Express* Port 3 Signals , to narrower widths is supported, see Figure 1-2 - x16 port (Port 2 & Port 3 ) may negotiate down to , Interface Gen 2 (DMI2) Port 0 DMI Port 1 (IOU2) PCIe Port 2 (IOU0) PCIe Port 3 (IOU1) PCIe , Terminology (Sheet 1 of 3 ) Term ASPM Cbo DDR3 DMA DMI DMI2 DTS ECC Enhanced Intel® SpeedStep® Technology


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PDF LGA-2011 i7-3960X i7-39xxK i7-38xx LGA 2011 Socket diagram LGA2011 LGA 2011 Socket transistors F6 DD52 3930k ddr3 controller BJ13 VCCD01 i7-3930 pcie gen 2 payload
2005 - altera EPM7032B

Abstract: GTLP16612 GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Text: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 transceiver GTLP8T306 SN74GTLPH306 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A (2) 2 20-bit SSTL-3


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PDF 7000B altera EPM7032B GTLP16612 GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
2009 - L2998

Abstract: LP2955 LP2998 M08A SSTL-18
Text: -18 SSTL-2 SSTL-3 HSTL 20080422 © National Semiconductor Corporation , LP2998 2 ( ) DDR-SDRAM (DDR II) SSTL-3 HSTL I/F , www.national.com/jpn/ 12 Figure 1011 Figure 10 2 VDDQ/2 VTT SSTL-3 SSTL , -8 Layout SO-8 PSOP-8 1 GND 2 SD 3 VSENSE VTT , ) PVINAVINVDDQ GND AVIN PSOP-8 ( JA) ESD (Note 2) - 65 150 (Note 3 ) 150


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PDF LP2998 SSTL-2SSTL-18 LP2998 SSTL-18 DS300269-02-JP L2998 LP2955 M08A SSTL-18
2002 - SSTL-3

Abstract: No abstract text available
Text: -V VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need , resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The series , Supported I/O Standards SSTL-3 class I VCCIO (V) 3.3 SSTL-3 class II 3.3 SSTL-2 class I 2.5 , resistors. Parallel termination is supported for SSTL-2, SSTL-3 , HSTL (class I and II), GTL, GTL+, and CTT , ) SSTL-3 class I N/A 50 3.3 SSTL-3 class II (1) 50 50 3.3 SSTL-2 class I N


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2011 - LGA 2011 Socket diagram

Abstract: BR17
Text: ) . 20 3 Technologies , ) . 26 Datasheet, Volume 1 3 4 Power Management , . 43 PCI Express* Port 3 Signals , €¢ Negotiating down to narrower widths is supported, see Figure 1-2 — x16 port (Port 2 & Port 3 ) may negotiate , ) PCIe Port 2 (IOU0) PCIe Port 3 (IOU1) PCIe Transaction Transaction Transaction


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PDF LGA-2011 i7-3960X i7-3970X i7-39xxK i7-38xx LGA 2011 Socket diagram BR17
2005 - PC2-5300P-555-12

Abstract: pc2-5300p DDR2 pin out 5300P DDR2-400 HYS72T256322HP PC2-5300
Text: (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_s_rev321 / 3 , . . . . . . . . . . . . 16 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 Electrical , CAS Latencies ( 3 , 4 & 5), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self Refresh , produced on the Raw Card "W" Table 3 Address Format DIMM Density Module Organization , Buffer Type are Table 5 explained in Table 3 and Table 4 respectively. The pin numbering is depicted


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PDF HYS72T256322HP 240-Pin DDR2-800 DDR2-667 DDR2-533 DDR2-400 11102005-QKC8-JBW4 PC2-5300P-555-12 pc2-5300p DDR2 pin out 5300P PC2-5300
2001 - GTLP16612

Abstract: SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 SSTL-3 sstl lvttl Translator
Text: ® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 , , discrete I/O translators, buffers, drivers, and transceivers are used to convert GTL+, SSTL-2, or SSTL-3 , -2 and SSTL-3 drivers supporting outputs in the Class I and Class II standards. M-WP-MAX7000B , Corporation Using MAX 7000B Devices to Replace I/O Drivers Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers Number Description Part Numbers Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3


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PDF 7000B 7000B, GTLP16612 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 SSTL-3 sstl lvttl Translator
LP2996

Abstract: LP2996MX LP2994 LP2996LQ LP2996M LP2996MR LP2996MRX
Text: SSTL-2 SSTL-3 HSTL 20021202 © National Semiconductor Corporation , ) SSTL-3 HSTL I/F (SSTL) DDR-SDRAM , 1011 Figure 10 2 VDDQ/2 VTT SSTL-3 SSTL-2 VDDQ 0.5 , SO-8 PSOP-8 LLP 1 2 GND 2 4 SD 3 5 VSENSE 4 7 VREF , 14, 15 VTT - 1, 3 , 6, 9, 13, 16 NC VTT


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PDF SO-8PSOP-8LLP-16 DS200575-04-JP LP2996 LP2996 DS200575 LP2994 16-Lead LQA16A LP2996MX LP2996LQ LP2996M LP2996MR LP2996MRX
2005 - 186-PIN DIMM

Abstract: No abstract text available
Text: /64][000/020]HDL­[5/6]­C Small-Outline DDR SDRAM Modules Table of Contents 1 1.1 1.2 2 3 3.1 3.2 , clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC SPD , Configuration 2 Pin Configuration Table 3 Pin# 112 111 110 109 108 107 106 105 102 type type 101 115 100 , The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 3 , respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Pin Configuration of SO-DIMM Pin Buffer


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PDF HYS64D32000HDL­ HYS64D64020HDL­ 200-Pin GLD09568 L-DIM-200-6) HYS64D GLD09570 L-DIM-200-11) 186-PIN DIMM
2005 - HYS72T512020HR-5-A

Abstract: DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
Text: : mp_a4_s_rev312 / 3 / 2005-03-18 HYS72T512020HR­[3.7/5]­A Registered DDR2 SDRAM Modules Table of Contents , . . . . . 16 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 Electrical , Programmable CAS Latencies ( 3 , 4 & 5), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self , 1.1 and produced on the Raw Card "ZZ" Table 3 Address Format DIMM Density Module , 512M × 72 2 ECC 36 14/ 3 /11 Table 4 Components on Modules 1) ZZ Product Type2


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PDF HYS72T512020HR­ 240-Pin DDR2-667C DDR2-667D DDR2-533C DDR2-400B 02012005-N6JU-ZWV6 HYS72T512020HR-5-A DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
1998 - AN1523

Abstract: ICS1523 ICS1523M
Text: (PECL) differential outputs Single-ended ( SSTL-3 ) clock outputs Double-buffered PLL/DPA control , single-ended ( SSTL-3 ) high-speed clock outputs Dynamic Phase AdjustTM The Dynamic Phase Adjust allows , The ICS 1523 utilizes LVTTL inputs, and SSTL-3 (EIA/JESD88) and low-voltage PECL (pseudo-ECL) outputs, operating at 3.3V supply voltage. The LVTTL inputs are 5 V-tolerant. The SSTL-3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL-3


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PDF ICS1523 ICS1523 24-Pin ICS1523M AN1523 ICS1523M
2002 - HDMP-2630B

Abstract: HDMP-2631B
Text: device I/O supply voltage. SSTL-3 inputs can receive LVTTL signals successfully. SSTL-3 outputs do not , SSTL_2 in the text will also apply to SSTL_ 3 ; however, there are separate tables and figures showing , rates separately · Parallel data I/O, clocks and control compatible with SSTL_2 (HDMP-2630B) or SSTL_ 3 , Ordering Information Part Number Parallel I/O HDMP-2630B SSTL_2 HDMP-2631B SSTL_ 3 The high-speed , transitions. The HDMP-2630B/ 2631B incorporate the following: · SSTL_2 or SSTL_ 3 Parallel I/O · High Speed


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PDF HDMP-2630B/2631B HDMP-2630B/2631B serial13 5988-4935EN HDMP-2630B HDMP-2631B
2007 - PC3200S-3033-1-Z

Abstract: PC2700S-25330 bdl 39 DDR400 DDR400B HYS64D64020GBDL HYS64D64020HBDL PC3200 PC2700S-2533
Text: . 1.21, 2007-01 03292006-F1IB-1I3E PC2700­2533 - 166 MHz 166 166 MHz 133 3 , ­5­C PC2700 (CL=2.5) HYS64D64020GBDL­6­C TABLE 3 Ordering Information for RoHS Compliant Products , "2033­0" means CAS latency of 2.0 clocks, RCD 1) latency of 3 clocks, Row Precharge latency of 3 clocks , Bit 3 Note: ECC type module NC NC - Note: Non-ECC module CB4 I/O SSTL Check , Outline DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 3 ,4, 15, 16, 27


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PDF HYS64D 64020H 64020G 200-Pin HYS64D64020 PC3200S-3033-1-Z PC2700S-25330 bdl 39 DDR400 DDR400B HYS64D64020GBDL HYS64D64020HBDL PC3200 PC2700S-2533
2004 - HYS64T128020HM-3.7-A

Abstract: 4200M HYB18T1G160AF PC2-3200
Text: 16 3 3.1 3.2 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . , ( 3 , 4 and 5), Burst Length (8 & 4) and Burst Type Table 1 · · · · · Burst Refresh , SPD Revision 1.1 and produced on the Raw Card "A". Table 3 Address Format DIMM Density Module , 8 13/ 3 /10 A Components on Modules1) Product Type2) DRAM Components2) DRAM Density , # Name Pin Type Buffer Type Function 3 DQ0 I/O SSTL Data Bus 63:0 4 DQ1


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PDF HYS64T128020HM 214-Pin DDR2-533C DDR2-400B 04132004-S0LP-CL4Q HYS64T128020HM-3.7-A 4200M HYB18T1G160AF PC2-3200
2007 - PC2-3200R-333-12-ZZ

Abstract: PC2-3200R-333-12 DDR2 SDRAM component data sheet 1024M HYB18T2G402BF HYS72T1G042ER DDR2-400B
Text: faster than DDR2­400 comply with DDR2­400 timing specifications. · Programmable CAS Latencies ( 3 , 4 and , ethers. Rev. 1.0, 2007-04 04242007-NQ2Z-YM3O 3 Internet Data Sheet HYS72T1G042ER , the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "Z". TABLE 3 Address Format DIMM , bits Raw Card 8 GByte 1024M × 72 4 ECC 36 Z 14/ 3 /11 TABLE 4 Components on , : 1-Rank, 2-Ranks module SSTL Rank 3 is selected by S3 NC NC - Not Connected Note: 1


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PDF HYS72T1G042ER 240-Pin rev400 04242007-NQ2Z-YM3O PC2-3200R-333-12-ZZ PC2-3200R-333-12 DDR2 SDRAM component data sheet 1024M HYB18T2G402BF DDR2-400B
2008 - Not Available

Abstract: No abstract text available
Text: details, refer to Chapter 4.1 Speed Bins. Rev. 0.63, 2008-12 01292008-3X8M-8FRF 3 Advance , : 2 × 256Mbit × 4 Address Bits (Row/Column/Bank): 14/11/ 3 TABLE 3 Product Information for Modules , -Gbit Dual-Die) Organization: 2 × 256Mbit × 4 Address Bits (Row/Column/Bank): 14/11/ 3 Rev. 0.63, 2008-12 , [ 3 :0] On-Die Termination [1:0] Clock Enable [1:0] Differential Clock Inputs [1:0] Control Signals , dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 58 178 56 177 175 70 55 174 196 172 171 3 4 9 10 122 123


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PDF IMSH8GP22A1F2C IMHH8GP22A1F2C 240-Pin IMSH8GP22A1F2C, IMHH8GP22A1F2C IMHH8GP22A1F2C- 10F/13H/13G]
JESD8

Abstract: ANSI/TIA/EIA-644 15-V EP1C12 JESD89A JESD87
Text: devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3 , and LVDS , /A 3.3 N/A SSTL-3 Class I and II Voltage-referenced ­0.3 to 3.9 3.3 1.5 3.3 , Supported I/O Standards SSTL-3 Class I & II (EIA/JEDEC Standard JESD8-8) The SSTL-3 I/O standard is a , defines the input and output specifications for devices that operate in the SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies an input voltage range of ­ 0.3 V VI VCCIO + 0.3


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PDF C51008-1 JESD8 ANSI/TIA/EIA-644 15-V EP1C12 JESD89A JESD87
LP2955

Abstract: LP2995 M08A SO-8PSOP-8LLP-16 LLP-16
Text: SO-8PSOP-8LLP-16 DDR SSTL-2 SSTL-3 20020514 © National , VREF VTT 1.25V SSTL-3 0.5 VDDQ × 0.45 VDDQ , TTVREF VDDQ ×0.45 V 2 50k VTT VDDQ × 0.5 SSTL-3 0.5 FIGURE 6. SSTL-3 Implementation VTT VDDQ × 0.5 VTTGND VSENSE VREF VTT , -8 LLP 1 13469 1316 NC 2 2 GND 3 5 VSENSE 4 7 VREF VDDQ/2


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PDF LP2995 SO-8PSOP-8LLP-16 DS200393-11-JP LP2995 DS200393 16-Lead LQA16A LP2955 M08A SO-8PSOP-8LLP-16 LLP-16
gm72v16821

Abstract: GMM2645233CTG gm72v16821ct
Text: LVTTL 44 TSOP 1 1(400MIL) SSTL-3 NOW 50 TSOP I I (400MIL) 66/83/100 MHz SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 4K LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 MHz 54 TSOP 1 1 (400MIL) NOW *NOTE LVTTL : Low Voltage Transistor Transistor Logic CTT : Center Tapped Termination SSTL-3 , 13 LG Semicon 3 . SDRAM SOD1MM MODULE SDRAM LINE-UP NOTE : * ; Comming Soon, f ; Under , GM72V161621CT GM72V66421CT GM72V66423CT GM72V66441CT GM72V66443CT GM72V66821CT GM72V66823CT 3 ,3V GM72V66841CT


OCR Scan
PDF GM72V16421CT 400M1L) 512Kx GMM27332233CTG 27332230CMTG 16Mx4) 100/125MHz MAR98 144pin 66/83/100MHz gm72v16821 GMM2645233CTG gm72v16821ct
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