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Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
74SSTL16837ADGGRG4 74SSTL16837ADGGRG4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC, TSSOP-64
74SSTL16857DGGRG4 74SSTL16857DGGRG4 ECAD Model Texas Instruments SSTL SERIES, 14-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
SN74SSTL16837ADGGR SN74SSTL16837ADGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16837ADGGRE4 74SSTL16837ADGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
SN74SSTL16837DGGR SN74SSTL16837DGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, SSOP-64
74SSTL16847DGGRE4 74SSTL16847DGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

SSTL-18 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
CMOS applications handbook

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Text: devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS , SSTL-2 class II Voltage referenced 2.5 V 2.5 V v v v v v SSTL-18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL-18 class II Voltage referenced , SSTL-2 class I or Pseudo class II differential (3) (5) Differential SSTL-18 class I or class II , ) (8) These pins support SSTL-18 class II and 1.8 - and 1.5-V HSTL class II inputs. PCI-X does not


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PDF CII51010-2 SSTL-18, CMOS applications handbook ttl to mini-lvds EP2C20 EP2C35 EP2C50 SSTL-18
2009 - SSTL-18

Abstract: EPM2210F256FBGA DDR2 SSTL class g22 touch 3C120F780 AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
Text: top_oe_n_to_the_max2 E25 Output enable (active low) Output 1.8 V Bidirectional SSTL-18 Class I Top , Negative differential clock Input Bidirectional SSTL-18 Class I top_ddr2top_a[0] J13 Address Output SSTL-18 Class I top_ddr2top_a[1] G18 Address Output SSTL-18 Class I top_ddr2top_a[2] E8 Address Output SSTL-18 Class I top_ddr2top_a[3] D24 Address Output SSTL-18 Class I top_ddr2top_a[4] D7 Address Output SSTL-18 Class I top_ddr2top_a[5


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PDF 3C120 DS-01002-1 3C120F780 3C120 SSTL-18 EPM2210F256FBGA DDR2 SSTL class g22 touch AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
HSTL standards

Abstract: DDR2 sstl_18 class I 15-V SSTL-18
Text: and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8 , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 , V Output Buffer 50 25 50 Z = 50 Input Buffer VREF = 1.25 V SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series


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PDF SII52004-4 HSTL standards DDR2 sstl_18 class I 15-V SSTL-18
Not Available

Abstract: No abstract text available
Text: . Programming flash. Figure 2–8 Programming flash 18 8. Programming complete. Figure 2–9 , pairs CDR-based transceivers, 19 pairs LVDS transmitter channels, and 18 pairs LVDS receiver channels , transmitter channels, and 18 pairs LVDS receiver channels. Additionally, both ports A and B of the HSMC , Description I/O Standard 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 , 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.4-V PCML 1.8 -V(*) 1.8 -V(*) 2.5-V 2.5


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HSTL standards

Abstract: SSTL-18 class sstl 15-V AGX52008-1 APEX20KC
Text: SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I SRAM , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM 8­2 Arria GX Device , Table 8­1. Arria GX I/O Standard Applications (Part 2 of 2) I/O Standard Differential SSTL-18 Class II , = 1.25 V SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under the JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard


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PDF AGX52008-1 HSTL standards SSTL-18 class sstl 15-V APEX20KC
2008 - K1B3216B2E

Abstract: Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
Text: With up to 7,280 KByte of enhanced TriMatrix memory and 384 embedded 18 × 18 multipliers, the on-board , EPM2210GF256 CPLD in a BGA package 1.8 -V core power On-board memory 1-GByte DDR2 SDRAM DIMM , ) 125-MHz XTAL RJ45 Jack CMOS + LVDS 2.5-V CMOS 10/100/1000 Ethernet 1.8 -V CMOS 2.5 , 14-Pin LCD Header 1.8 -V SSTL 1.8 -V SSTL 1-GByte DDR2 (x72) CMOS + LVDS USB 2.0 HSMC Port A 16-MB DDR2 (x8) 50-MHz XTAL 16-MB DDR2 (x8) 1.8 -V CMOS Power Measure


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PDF 3SL150 K1B3216B2E Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
2004 - mini-lvds receiver

Abstract: JESD85 ttl to mini-lvds bga 896
Text: flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS compatibility , LVCMOS 1.8 -V LVTTL and LVCMOS 1.5-V LVCMOS SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class , Differential SSTL-2 class I or Pseudo class II differential (3) v (5) Differential SSTL-18 class I or , Notes to Table 10­1: (1) (2) (3) These pins support SSTL-18 class II and 1.8 - and 1.5-V HSTL class II , . PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II


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ttl to mini-lvds

Abstract: EP2C5 mini lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18 SSTL IO pad
Text: flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS compatibility , -2 class II Voltage referenced 2.5 V 2.5 V v v v v v SSTL-18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL-18 class II Voltage referenced 1.8 V , (6) 1.8 V 1.8 V v (5) Differential SSTL-18 class I or class II v v (5) 10­2 , ) These pins support SSTL-18 class II and 1.8 - and 1.5-V HSTL class II inputs. PCI-X does not meet the IV


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2005 - Not Available

Abstract: No abstract text available
Text: Handbook, Volume 1 Operating Conditions Table 4­26. SSTL-18 Class I Specifications Symbol VCCIO , volume 1 of the Arria GX Device Handbook. Table 4­27. SSTL-18 Class II Specifications Symbol VCCIO , Corporation May 2008 DC and Switching Characteristics Table 4­28. SSTL-18 Class I & II Differential , ground Maximum 1.8 4.6 4.6 4.6 40 150 Unit V V V V mA C ­65 Altera Corporation May 2008 , buffers, 1.8 -V operation Supply voltage for output buffers, 1.5-V operation Supply voltage for output


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PDF AGX51004-1
2005 - TCO 706

Abstract: GX 6107
Text: Device Handbook, Volume 1 Operating Conditions Table 4­26. SSTL-18 Class I Specifications Symbol , . Table 4­27. SSTL-18 Class II Specifications Symbol VCCIO VREF VTT Parameter Output supply voltage , Corporation May 2009 DC and Switching Characteristics Table 4­28. SSTL-18 Class I & II Differential , With respect to ground - - Maximum 1.8 4.6 4.6 4.6 40 150 Units V V V V mA C Altera , Supply voltage for output buffers, 1.8 -V operation Supply voltage for output buffers, 1.5-V operation


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PDF AGX51004-1 TCO 706 GX 6107
SSTL-18

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 JESD8-15
Text: devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS , SSTL-2 class II Voltage referenced 2.5 V 2.5 V v v v v v SSTL-18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL-18 class II Voltage referenced , ) (5) v (6) 1.8 V 1.8 V v (5) Differential SSTL-18 class I or class II v v (5 , ) (7) (8) These pins support SSTL-18 class II and 1.8 - and 1.5-V HSTL class II inputs. PCI-X does


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PDF CII51010-2 SSTL-18, SSTL-18 ttl to mini-lvds EP2C20 EP2C35 EP2C50 JESD8-15
mini-lvds source driver

Abstract: ttl to mini-lvds EP2C5 HSTL standards linear handbook mini lvds national semiconductor handbook CII51010-2 EP2C20 EP2C35
Text: flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18 , SSTL-2, and LVDS compatibility , 2.5 V 2.5 V v v v v v SSTL-18 class I Voltage referenced 1.8 V 1.8 V v v v v v SSTL-18 class II Voltage referenced 1.8 V 1.8 V v v (1 , differential (3) (5) Differential SSTL-18 class I or class II Pseudo differential (3) (4) 1.8 V , v Notes to Table 10­1: (1) (2) (3) (4) (5) (6) (7) (8) These pins support SSTL-18


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HSTL standards

Abstract: 15-V SSTL-18
Text: and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8 , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 , = 1.25 V SSTL-18 Class I and SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard


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class sstl

Abstract: HSTL standards 15-V AGX52008-1 APEX20KC SSTL-18
Text: -2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class , Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 Class II DDR2 SDRAM 1.8 -V differential , = 1.25 V SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under the JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard , to operate in the SSTL-18 logic switching range 0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a


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PDF AGX52008-1 class sstl HSTL standards 15-V APEX20KC SSTL-18
EIA standards 783

Abstract: PLL 566 AGX51004-1 PRBS31 SSTL-18 n e c 2705 TCO 706
Text: Table 4­21. SSTL-18 Class I Specifications Symbol Parameter Conditions Minimum Typical , Handbook. Table 4­22. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum , Conditions Table 4­23. SSTL-18 Class I & II Differential Specifications Symbol Parameter Conditions , ground ­0.5 1.8 V VCCIO Supply voltage With respect to ground ­0.5 4.6 V , voltage for output buffers, 1.8 -V operation Rise time 100 ms (3) 1.71 1.89 V Supply


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PDF AGX51004-1 EIA standards 783 PLL 566 PRBS31 SSTL-18 n e c 2705 TCO 706
2009 - EIA standards 783

Abstract: PLL 566 AGX51004-2 PRBS31 SMPTE292M SSTL-18 din 2982 SMPTE-424M TCO 706
Text: - 0.1 VCCIO V Table 4­26. SSTL-18 Class I Specifications Symbol Parameter Conditions , chapter. Table 4­27. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum , 4­27. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum Typical , this I/O standard as shown in the Arria GX Architecture chapter. Table 4­28. SSTL-18 Class I & II , ground ­0.5 1.8 V VCCIO Supply voltage With respect to ground ­0.5 4.6 V


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PDF AGX51004-2 EIA standards 783 PLL 566 PRBS31 SMPTE292M SSTL-18 din 2982 SMPTE-424M TCO 706
DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Text: - termination resistors (3-state) 74ALVC16834A 18 -bit registered driver with inverted register enable (3-state) 74ALVC162834A 18 -bit registered driver with inverted register enable and 30- termination resistors (3-state) 74ALVC16835A 18 -bit registered driver (3-state) 74ALVC162835A 18 -bit registered driver with 30 , -bit registered driver with 30- termination resistors (3-state) 74AVCM162834 18 -bit registered driver with inverted register enable and 15- termination resistors (3-state) 74AVCM162835 18 -bit registered


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PDF PC100 PC133 PCK2509 PCK2510 DDR200 DDR266 DDR333 DDR400 PCKVF857 DDR2-400 DDR2 SSTL class SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 hp SSTU32866
2005 - PC2-5300P-555-12

Abstract: pc2-5300p DDR2 pin out 5300P DDR2-400 HYS72T256322HP PC2-5300
Text: VREF AI - I/O Reference Voltage Reference voltage for the SSTL-18 inputs. 238 VDDSPD , 17 17 18 18 19 23 24 27 28 Rev. 1.0, 2005-11 11102005-QKC8-JBW4 240-Pin Dual-Die , Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply All speed grades , High Temperature Self Refresh All inputs and outputs SSTL_ 18 compatible Off-Chip Driver Impedance , 72 2 ECC 18 14/2/11 Table 4 Components on Modules 1) W Product Type2) DRAM


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PDF HYS72T256322HP 240-Pin DDR2-800 DDR2-667 DDR2-533 DDR2-400 11102005-QKC8-JBW4 PC2-5300P-555-12 pc2-5300p DDR2 pin out 5300P PC2-5300
15-V

Abstract: AGX52008-1 APEX20KC SSTL-18 Teradyne connector 72 pin
Text: -2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class , Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 Class II DDR2 SDRAM 1.8 -V differential , = 1.25 V SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under the JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard , to operate in the SSTL-18 logic switching range 0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a


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JESD8-15

Abstract: mini-lvds connector panels Quad LVDS interface mini-lvds source driver BEL 100N TRANSISTOR BEL 100N TRANSISTOR TYPE METAL TRANSISTOR linear handbook JESD87 t20g th02
Text: . Selectable 1/O capabilities such as SSTL-18 , SSTL-2, and LVDS compatibility allow Cyclone™ II devices to , / v' y y SSTL-2 class II Voltage referenced 2.5 V 2.5 V v' v/ v' y y SSTL-18 class I Voltage referenced 1.8 V 1.8 V v' v/ v' y y SSTL-18 class II Voltage referenced 1.8 V 1.8 V v' v/ (V (V (V HSTL- 18 , ) Differential SSTL-18 class I or class II Pseudo differential (3) (4) 1.8 V y (6) 1.8 V (4) s/ (5) y (5 , / 2.5 V/ 1.8 V/ 1.5 V (4) •y •y Notes to Table 10-1: (1) These pins support SSTL-18 class II


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HSUL-12

Abstract: SSTL-12 SSTL-125 SSTL-135 SSTL12
Text: JESD8-9B SSTL-18 Class I DDR2 SDRAM JESD8-15 SSTL-18 Class II DDR2 SDRAM JESD8 , SDRAM JESD8-9B Differential SSTL-18 Class I DDR2 SDRAM JESD8-15 Differential SSTL-18 , 2.5 1.25 1.25 SSTL-18 Class I VCCPD 1.8 2.5 0.9 0.9 SSTL-18 Class II , 2.5 2.5 — 1.25 Differential SSTL-18 Class I VCCPD 1.8 2.5 — 0.9 Differential SSTL-18 Class II VCCPD 1.8 2.5 — 0.9 Differential SSTL-15 Class I VCCPD


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PDF SV51006 HSUL-12 SSTL-12 SSTL-125 SSTL-135 SSTL12
2005 - HYS72T512020HR-5-A

Abstract: DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
Text: /O Reference Voltage Reference voltage for the SSTL-18 inputs. 13 Rev. 1.1, 2005-08 02012005 , Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply , Refresh All inputs and outputs SSTL_ 1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and , Buffer Type Type Function 18 RESET I CMOS Register Reset The RESET pin is connected to , Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_ 18


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PDF HYS72T512020HR­ 240-Pin DDR2-667C DDR2-667D DDR2-533C DDR2-400B 02012005-N6JU-ZWV6 HYS72T512020HR-5-A DDR2 pcb layout DDR2 pin out DDR2-400 DDR2-533 HYS72T512020HR PC2-3200
SSTL "on-chip termination" 1998

Abstract: 15-V SSTL-18 DDR2 SDRAM sstl_18 HSTL standards
Text: and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8 , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 , V Output Buffer 50 25 50 Z = 50 Input Buffer VREF = 1.25 V SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series


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interfacing differential logic families 1998

Abstract: 15-V SSTL-18 HSTL standards
Text: and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8 , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 , SSTL-18 Class I & SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard is a 1.8 -V memory


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DDR2 sstl_18 class

Abstract: HSTL standards 15-V SSTL-18 N098
Text: and embedded system SSTL-2 Class I DDR SDRAM SSTL-2 Class II DDR SDRAM SSTL-18 Class I DDR2 SDRAM SSTL-18 Class II DDR2 SDRAM 1.8 -V HSTL Class I QDRII SRAM/RLDRAM II/SRAM 1.8 , Differential SSTL-2 Class II DDR SDRAM Differential SSTL-18 Class I DDR2 SDRAM Differential SSTL-18 , SSTL-18 Class I and SSTL-18 Class II The 1.8 -V SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8 -V (SSTL_ 18 ). The SSTL-18 I/O standard is a 1.8 -V memory


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