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AK2526DVD ASSMANN WSW components GmbH CABLE INTERNAL S/P-DIF AUDIO
AT4075F NKK Switches Switch Hardware SQ DIF FOR UB PB
MAX4611ESD+ Maxim Integrated Products SPST, 4 Func, 1 Channel, CMOS, PDSO14, ROHS COMPLIANT, SOIC-14
MAX4611ESD+T Maxim Integrated Products SPST, 4 Func, 1 Channel, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14
MAX4611ESD Maxim Integrated Products SPST, 4 Func, 1 Channel, CMOS, PDSO14, 0.150 INCH, MS-012AB, SOIC-14

SS/611ES-DIF Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
611ES

Abstract: 600t SMART Differential Pressure Transmitter abb 600t SMART Pressure Transmitter abb DIN19213 nace group 600T profibus connector co sensor DC200 silicone oil BAS 98 ATEX
Text: Specification sheet 600T EN Series Pressure Transmitters Model 611ES differential/gauge , 1 GENERAL DESCRIPTION Model 611ES and 614ES detailed in this specification sheet apply for , model 611ES the following versions can be obtained : a) two remote seals of same type and size; this , 611ES C N D E F W U 2 - 10 kPa - 100 mbar - 40.1 inH2O - 40 kPa - 400 mbar - 160 , bar 348 psi 8000 kPa 80 bar 1160 psi 16000 kPa 160 bar 2320 psi (TD) Normal 611ES


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PDF 611ES 614ES EN10204 SS/61XES-RS 600t SMART Differential Pressure Transmitter abb 600t SMART Pressure Transmitter abb DIN19213 nace group 600T profibus connector co sensor DC200 silicone oil BAS 98 ATEX
614-E

Abstract: 611ES.B DN80-100 DC200 silicone oil 16*2 alphanumeric LCD 600T UNI 5737 NUT 614ES ABB KENT-TAYLOR transmitter remote seal ASTM A194
Text: Specification sheet 600T EN Series Pressure Transmitters Model 611ES level/differential/gauge , standard 1 GENERAL DESCRIPTION Model 611ES and 614ES detailed in this specification sheet apply for , properly selecting the high and low pressure side variant in the ordering codes model 611ES can be in the , / NW100 S2 2in/F50 S3 3-4in/F80 Range and span limits · Model 611ES B C N D E F 10 kPa , types) 611ES 611ES Direct mount and Direct mount Direct mount Direct mount one remote seal


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PDF 611ES 614ES EN10204 SS/61XES-DM 614-E 611ES.B DN80-100 DC200 silicone oil 16*2 alphanumeric LCD 600T UNI 5737 NUT ABB KENT-TAYLOR transmitter remote seal ASTM A194
600t SMART Differential Pressure Transmitter abb

Abstract: 600T differential pressure transmitter 600t SMART Pressure Transmitter abb MR0175* bolts bolts and nuts according to din standards uni 3740 UNI 3740 9 99-ATEX 611ES 600t SMART Differential Pressure Transmitter
Text: . 18974-4995 USA Tel. (215) 674-6693/6320/6777 Facsimile (215) 674-7184 SS/ 611ES-DIF Rev . 8 ab - , Specification sheet 600T EN Series Pressure Transmitters Model 611ES Flange mounted , °F) change between the limits of - 20°C to + 65°C (-4 to +150°F) : Model 611ES Flange mounted , bar or 290 psi · Model 611ES (differential flange mounted) - zero error : ± 0.20% of URL - span , ORDERING INFORMATION model 611ES Flange Mounted Differential Pressure Transmitter Select one character or


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PDF 611ES EN10204 SS/611ES-DIF 600t SMART Differential Pressure Transmitter abb 600T differential pressure transmitter 600t SMART Pressure Transmitter abb MR0175* bolts bolts and nuts according to din standards uni 3740 UNI 3740 9 99-ATEX 600t SMART Differential Pressure Transmitter
2014 - Not Available

Abstract: No abstract text available
Text: - 100MHz Low-Power (LP) HCSL DIF pairs • 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) • support • Key Specification • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew < 60ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 3.0ps RMS â , ; support DIF power management Programmable Slew rate for each output; allows tuning for various line length Programmable output amplitude; allows tuning for various application environments DIF outputs


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PDF 9FGU0831 9FGU0831 100MHz
2014 - Not Available

Abstract: No abstract text available
Text: ) HCSL DIF pairs • • • • w/Zo=100ohms 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) support • • Key Specification • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew < 60ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is , 1.5V; maximum power savings OE# pins; support DIF power management Programmable Slew rate for each , application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0


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PDF 100ohms 9FGU0841 9FGU0841 100ohm 100MHz
2013 - DT1X

Abstract: IDT6P41302
Text: 1.05 and 1.8V; maximum power savings OE# pins; support DIF power management LP-HCSL differential clock , line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF , HCSL-compatible (LP-HCSL) DIF · pairs w/Zo=100 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications · · · · DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe


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PDF IDT6P41302 IDT6P41302 DT1X
2012 - Not Available

Abstract: No abstract text available
Text: off. Features/Benefits · 1.8V operation; reduced power consuption · OE# pins; support DIF power , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports , - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · · · · · pairs 1 - 1.8V LVCMOS REF output w/Wake-On-Lan Key Specifications DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase


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PDF 9FGV0831 9FGV0831
2014 - Not Available

Abstract: No abstract text available
Text: 100MHz Low-Power (LP) HCSL DIF pairs • 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) • support • Key Specifications • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <60ps DIF phase jitter is PCIe Gen2 and Gen3 compliant REF phase jitter is < 3.0ps RMS â , ; support DIF power management Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs


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PDF 9FGU0631 9FGU0631 100MHz
1995 - 64 point radix 4 FFT

Abstract: radix-2 16 point DFT butterfly graph 64 point FFT radix-4 16 point DIF FFT using radix 4 fft 64-point core i3 CORE i3 instruction set transistor YA SB JY
Text: -point DFTs, then into 16 N/16-point DFTs, and so on. In the radix-2 DIF FFT, the DFT equation is expressed , other that computes odd samples. Similarly, the radix-4 DIF FFT expresses the DFT equation as four , ( 4r + 2 ) x( 4r + 3 ) Figure 6.9 Radix-4 DIF FFT Butterfly 195 6 One-Dimensional FFTs , x'd + jy' d Figure 6.10 Radix-4 DIF FFT Butterfly, Complex Data The real and imaginary output , 51 52 53 54 55 56 57 58 59 60 61 62 63 Figure 6.11 Sixty-Four-Point Radix-4 DIF FFT


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PDF N/16-point 16-point 64-point 1024-point 64 point radix 4 FFT radix-2 16 point DFT butterfly graph 64 point FFT radix-4 16 point DIF FFT using radix 4 fft core i3 CORE i3 instruction set transistor YA SB JY
2012 - pcie X1 edge

Abstract: 603-25-150 DT1X 9FGV0841AKLF
Text: 1.05 and 1.8V; maximum power savings OE# pins; support DIF power management LP-HCSL differential clock , line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF , PCIe Gen1-2-3 Clock Generator Output Features · 8 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · , DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1


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PDF 9FGV0841 9FGV0841 pcie X1 edge 603-25-150 DT1X 9FGV0841AKLF
2014 - Not Available

Abstract: No abstract text available
Text: PCIe Gen1-2-3 clock generator Output Features • • 6 -100MHz Low-power HCSL (LP-HCSL) DIF , €¢ Key Specifications • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <60ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 3.0ps RMS • • â , # pins; support DIF power management Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF


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PDF 100ohms 9FGU0641 9FGU0641 100ohms. 100ohm -100MHz
2013 - Not Available

Abstract: No abstract text available
Text: DIF power management • LP-HCSL differential clock outputs; reduced power and Recommended , HCSL-compatible (LP-HCSL) DIF • pairs 1 - 1.8V LVCMOS REF output w/Wake-On-Lan • Key Specifications • • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 1.5ps RMS • • • â , Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until


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PDF 9FGV0431
2013 - Not Available

Abstract: No abstract text available
Text: spread off. Features/Benefits · 1.8V operation; reduced power consuption · OE# pins; support DIF , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports , - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · · · · · pairs 1 - 1.8V LVCMOS REF output w/Wake-On-Lan Key Specifications DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase


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PDF 9FGV0431 9FGV0431
2012 - Not Available

Abstract: No abstract text available
Text: operation; reduced power consuption OE# pins; support DIF power management LP-HCSL differential clock , line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF , PCIe Gen1-2-3 Clock Generator Output Features · 4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · , DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1


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PDF 9FGV0441 9FGV0441
2012 - 9FGV0431

Abstract: No abstract text available
Text: spread off. Features/Benefits · 1.8V operation; reduced power consuption · OE# pins; support DIF , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports , - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · · · · · pairs 1 - 1.8V LVCMOS REF output w/Wake-On-Lan Key Specifications DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase


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PDF 9FGV0431 9FGV0431
2012 - pcie X1 edge

Abstract: 603-25-150
Text: operation; reduced power consuption OE# pins; support DIF power management LP-HCSL differential clock , line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF , PCIe Gen1-2-3 Clock Generator Output Features · 4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · , DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1


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PDF 9FGV0441 9FGV0441 pcie X1 edge 603-25-150
2014 - Not Available

Abstract: No abstract text available
Text: -2-3 clock generator • Output Features • • 4 - 100MHz Low-Power (LP) HCSL DIF pairs â , Specifications • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 3.0ps RMS • • resistors , ; support DIF power management Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs


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PDF 100ohms 9FGU0441 9FGU0441 100ohm 100MHz
2013 - Not Available

Abstract: No abstract text available
Text: -2-3 Clock Generator Output Features • • 4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF â , €¢ • • • • • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 1.5ps RMS • â , # pins; support DIF power management LP-HCSL differential clock outputs; reduced power and board space , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean


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PDF 9FGV0441 9FGV0441
2014 - Not Available

Abstract: No abstract text available
Text: Low-Power (LP) HCSL DIF pair • 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) • support • Key Specifications • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 3.0ps RMS • • • PCIe device 39mW typical power consumption; reduced thermal concerns OE# pins; support DIF power , output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is


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PDF 9FGU0431 9FGU0431 100MHz
2012 - 9FGV0441

Abstract: Fox Electronics 850mV
Text: operation; reduced power consuption OE# pins; support DIF power management LP-HCSL differential clock , line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF , PCIe Gen1-2-3 Clock Generator Output Features · 4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · , DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1


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PDF 9FGV0441 9FGV0441 Fox Electronics 850mV
2012 - Not Available

Abstract: No abstract text available
Text: -2-3 Clock Generator Output Features • • 4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF â , €¢ • • • • • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 1.5ps RMS • â , # pins; support DIF power management LP-HCSL differential clock outputs; reduced power and board space , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean


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PDF 9FGV0441
2002 - Not Available

Abstract: No abstract text available
Text: for $30 -TH700 for $30 -TH700 for $30 -TH700 for $30 -R3K for $30 AMP-AMP - DIF . -R3K , €” — — — — — — — — — — Dif . std. -SCO for $30 $125 Dif . std. Dif . std. -SCO for $30 $250 $250 Dif . std. -SCO for $30 $250 $250


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PDF PHE-7352-15 PHE-7451-15 PHE-7353-15 1999MV -TH700 PHE-7451-15-PT1K-HPH-SCO PHE-7354-15
2013 - Not Available

Abstract: No abstract text available
Text: spread off. Features/Benefits · 1.8V operation; reduced power consuption · OE# pins; support DIF , ; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports , - 0.7V low-power HCSL-compatible (LP-HCSL) DIF · · · · · pairs 1 - 1.8V LVCMOS REF output w/Wake-On-Lan Key Specifications DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase


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PDF 9FGV0431 9FGV0431
2014 - Not Available

Abstract: No abstract text available
Text: Low-Power (LP) HCSL DIF pairs • 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) • support • Key Specifications • • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 compliant REF phase jitter is < 3.0ps RMS • • • PCIe devices 23mW typical power consumption; reduced thermal concerns OE# pins; support DIF power , output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is


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PDF 9FGU0231 9FGU0231 100MHz
2014 - Not Available

Abstract: No abstract text available
Text: -2-3 clock generator • Output Features • • 2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo , €¢ • • • • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase , ; support DIF power management Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs


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PDF 100ohms 9FGU0241 9FGU0241 100ohm 100MHz
Supplyframe Tracking Pixel