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Part Manufacturer Description Datasheet Download Buy Part
74ACT16863DLG4 Texas Instruments ACT SERIES, DUAL 9-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56
74ALVCH16863DLG4 Texas Instruments ALVC/VCX/A SERIES, DUAL 9-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56
SN74ALVCH16863DLR Texas Instruments 18-Bit Transceiver With 3-State Outputs 56-SSOP -40 to 85
74ACT16863DL Texas Instruments 18-Bit Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
74ALVCH16863DGGRG4 Texas Instruments ALVC/VCX/A SERIES, DUAL 9-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
74ACT16863DLR Texas Instruments ACT SERIES, DUAL 9-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56

SR 6863 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
SR 6863

Abstract: sr 6863 D 61bl TLV2432MFK TLV2432ID TLV2432CPWLE TLV2432CD TLV2432AMJG TLV2432AMFK TLV2432AID
Text: MIN TYP MAX SR Slew rate at unity gain Vo= 1.5 V to 3.5 V, RL = 2 kirf, CL= 100 pF* 25°C 0.15 0.25 , , Vqq = 3 V PARAMETER TEST CONDITIONS TA+ TLV2432M TLV2432AM UNIT MIN TYP MAX SR Slew rate at , PARAMETER TEST CONDITIONS TAt TLV2432C, TLV2432I TLV2432AI UNIT MIN TYP MAX SR Slew rate at unity , unit min typ max SR Slew rate at unity gain Vo = 1.5 Vto3.5 V, R|_ = 2knt, C|_ = 100 pFt 25 , TEST CONDITIONS TLV2432Y MIN TYP MAX UNIT SR Slew rate at unity gain Vo = 1 5 V to 3.5 V, CL= 100 pFt


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PDF TLV2432, TLV2432A, TLV2432Y slos168a- TLV2432A) TLV2432 TLV2432A -30E6 -30E6 250E-6 SR 6863 sr 6863 D 61bl TLV2432MFK TLV2432ID TLV2432CPWLE TLV2432CD TLV2432AMJG TLV2432AMFK TLV2432AID
2004 - LH28F800BJHE-PBTLT9

Abstract: No abstract text available
Text: User Interface (CUI) Status Register ( SR ) SRAM-Compatible Write Interface Industry-Standard , 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. Boot Block 1 , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF LH28F800BJHE-PBTLT9 LHF80JT9) EL16X081 LHF80JT9 LH28F800BJHE-PBTLT9
FE005

Abstract: LH28F800BJHB-39
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJHB-39 LHF80J39 AP-001-SD-E AP-006-PT-E AP-007-SW-E FE005 LH28F800BJHB-39
Electronic Combination Lock Circuit

Abstract: LH28F800BJHG-PBTLZ3
Text: ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 0.75mm pitch 48-Ball CSP s ETOXTM , abort the operation. SR .7 remains "0" until the reset operation is complete. Memory contents being , command and then write data with address to the device (See Figure 5). If OTP program is failed, SR .4(WORD WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE , Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can


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PDF LH28F800BJHG-PBTLZ3 LHF80JZ3 AP-001-SD-E AP-006-PT-E AP-007-SW-E Electronic Combination Lock Circuit LH28F800BJHG-PBTLZ3
2001 - LH28F800BJE-PTTL90

Abstract: 7E003
Text: Write and Lock-Bit Configuration Command User Interface (CUI) Status Register ( SR ) SRAM-Compatible , command and then write data with address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF LH28F800BJE-PTTL90 16/1M LHF80J01) EL132002 LHF80J01 LH28F800BJE-PTTL90 7E003
2001 - LHF80J21

Abstract: FE005 LH28F800BJB-PTTL90
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJB-PTTL90 LHF80J21 AP-001-SD-E AP-006-PT-E AP-007-SW-E LHF80J21 FE005 LH28F800BJB-PTTL90
2001 - LH28F800BJHB-PBTL90

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. Boot Block 1 Lock Configuration Code , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF x8/x16) LH28F800BJHB-PBTL90 LHF80J27 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F800BJHB-PBTL90
2000 - LH28F800BJE-PBTL90

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Industry-Standard Packaging 48-Lead TSOP , 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. Boot Block 1 , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF LH28F800BJE-PBTL90 16/1M LHF80J04) FM00Z004 LHF80J04 LH28F800BJE-PBTL90
LH28F320BJHE-PBTL90

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Industry-Standard Packaging 48-Lead TSOP , the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF x8/x16) LH28F320BJHE-PBTL90 LHF32J08 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F320BJHE-PBTL90
2002 - Not Available

Abstract: No abstract text available
Text: Blocks - Status Register ( SR ) - Six 4k-word Parameter Blocks · SRAM-Compatible Write Interface , command and then write data with address to the device (See Figure 5). If OTP program is failed, SR .4(WORD WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE , . - 16 - W28J321B/T Clear Status Register Command Status register bits SR .5, SR .4, SR .3 or SR , erase completion by analyzing the status register bit SR .7. When the block erase is complete, status


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PDF W28J321B/T
2002 - LH28F320BJHE-PBTL90

Abstract: No abstract text available
Text: , Word/Byte Write and Lock-Bit Configuration Command User Interface (CUI) Status Register ( SR , the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF LH28F320BJHE-PBTL90 16/4M LHF32J08) EL12X044 LHF32J08 LH28F320BJHE-PBTL90
2001 - LH28F800BJB-PTTL10

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJB-PTTL10 LHF80J22 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F800BJB-PTTL10
2001 - CSP-48

Abstract: LH28F800BJHB-PTTL90
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJHB-PTTL90 LHF80J23 AP-001-SD-E AP-006-PT-E AP-007-SW-E CSP-48 LH28F800BJHB-PTTL90
LH28F800BJHB-PBTL10

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 48-Ball CSP s ETOXTM , failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. Boot Block 1 Lock Configuration Code , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF x8/x16) LH28F800BJHB-PBTL10 LHF80J28 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F800BJHB-PBTL10
638 B34

Abstract: relay 1201 CMX868
Text: be omitted. Key SR Status Register b Bit (bits are subscripted 0 through 15. e.g. b1 b2 , Ready ( SR b6) Rx Tones Detect Modes DTMF Detect Mask ( SR b5) 2225 Hz Detect Mask ( SR b6) 1st Programmable tone detected ( SR b6) See Table to left 2nd Programmable Tone Detected ( SR b6) S1 (DPSK, QAM) Detected ( SR b9) 2100 Hz Detected ( SR b7) 1010.(FSK) Detected ( SR b9) Rx Data Ready ( SR b6) IRQ MASK BITS In Band Energy Detected ( SR b10) Descrambler Disabled Descrambler


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PDF CMX868 CMX868 22bis CMX868, 638 B34 relay 1201
2001 - LH28F320BJB-PTTL90

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Chip-Size Packaging 60-Ball CSP s ETOXTM , data with address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS , Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF x8/x16) LH28F320BJB-PTTL90 LHF32J10 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F320BJB-PTTL90
1999 - INTEL application notes

Abstract: 28F128J3A 28F320J3A 28F640J3A
Text: error bit SR .4 will be set to 1). See Table 4 for Status Register Definitions. Attempting to program a locked protection register segment will result in a status register error (program error bit SR .4 and lock error bit SR .1 will be set to 1). Table 3. Intel® StrataFlashTM Memory Command Set , Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR .7 1 = WSM Ready 0 = , . No SR .7 = 1? Comments Repeat for subsequent programming operations. Yes SR Full Status


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PDF AP-717 28F128J3A, 28F640J3A, 28F320J3A INTEL application notes 28F128J3A 28F640J3A
2003 - Not Available

Abstract: No abstract text available
Text: Write and Lock-Bit Configuration - Command User Interface (CUI) - Status Register ( SR ) · Optimized , 5). If OTP program is failed, SR .4(WORD WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. The OTP block is also , Clear Status Register Command Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM , analyzing the status register bit SR .7. When the block erase is complete, status register bit SR .5 should


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PDF W28J321B/T
1996 - AP-627

Abstract: 28F004S5 29218* intel 28F016S5 28F016S3 28F008SA-L 28F008S5 28F008S3 28F004SC 28F004S3
Text: Definition Bit Description Status SR .7 WSM Status 1 = Ready 0 = Busy SR .6 Erase Suspend Status 1 = Erase Suspended 0 = Erase in Progress/Completed SR .5 Erase and Clear , Block Lock-Bits SR .4 Program and Set Lock-Bit Status 1 = Error in Program or Set Block/Master Lock-Bit 0 = Successful Program or Set Block/Master Lock-Bit SR .3 VPP Status 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR .2 Program Suspend Status 1 = Program Suspended 0 = Program in


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PDF AP-627 AP-627 28F004S5 29218* intel 28F016S5 28F016S3 28F008SA-L 28F008S5 28F008S3 28F004SC 28F004S3
2003 - LH28F160BJHE-BTL90

Abstract: No abstract text available
Text: , Word/Byte Write and Lock-Bit Configuration Command User Interface (CUI) Status Register ( SR , register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete, status register bit SR .5 should be checked. If a block erase error is detected, the status register , will result in both status register bits SR .4 and SR .5 being set to "1". Also, reliable block erasure


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PDF LH28F160BJHE-BTL90 LHF16J08) ELl52051 LHF16J08 LH28F160BJHE-BTL90
2003 - LH28F800BJHE-PBTL90

Abstract: No abstract text available
Text: , Word/Byte Write and Lock-Bit Configuration Command User Interface (CUI) Status Register ( SR , 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to "1" too. Boot Block 1 , register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear , analyzing the output data of the RY/BY# pin or status register bit SR .7. When the block erase is complete


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PDF LH28F800BJHE-PBTL90 LHF80J05) EL152049 LHF80J05 LH28F800BJHE-PBTL90
2003 - LH28F160BJHG-TTL90

Abstract: No abstract text available
Text: ) Status Register ( SR ) SRAM-Compatible Write Interface Chip-Size Packaging 0.75mm pitch 48-Ball CSP , operation. SR .7 remains "0" until the reset operation is complete. Memory contents being altered are no , =1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are , register bit SR .7. When the block erase is complete, status register bit SR .5 should be checked. If a , erased. An invalid Block Erase command sequence will result in both status register bits SR .4 and SR


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PDF LH28F160BJHG-TTL90 LHF16JZB) EL126076 LHF16JZB LH28F160BJHG-TTL90
2003 - EL1510

Abstract: No abstract text available
Text: Configuration Command User Interface (CUI) Status Register ( SR ) SRAM-Compatible Write Interface , write data with address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS , register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status , erase completion by analyzing the output data of the RY/BY# pin or status register bit SR .7. When the


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PDF LH28F320BJE-PBTL90 LHF32J06) EL151047 LHF32J06 EL1510
2001 - LH28F800BJHE-PTTL10

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Industry-Standard Packaging 48-Lead TSOP , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJHE-PTTL10 LHF80J07 AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F800BJHE-PTTL10
2002 - LH28F800BJE-PTTLZ1

Abstract: No abstract text available
Text: ) Status Register ( SR ) s SRAM-Compatible Write Interface s Industry-Standard Packaging 48-Lead TSOP , address to the device (See Figure 5). If OTP program is failed, SR .4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR .1(DEVICE PROTECT STATUS) bit is set to , . DQ0=1 ·Reserved for Future Use Permanent Lock Configuration Status register bits SR .5, SR .4, SR .3 or SR .1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command


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PDF x8/x16) LH28F800BJE-PTTLZ1 LHF80JZB AP-001-SD-E AP-006-PT-E AP-007-SW-E LH28F800BJE-PTTLZ1
Supplyframe Tracking Pixel