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SM DELAY LINES Datasheets Context Search

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d-101-00

Abstract: SMD-580 SMD-2020 D5150 TIC 2060 SMD 2020 SMD-2030 SMD-2080 d20100 SMD-5100
Text: 12 million hours. The " SM D Series" delay lines are packaged in a 14-pin DIP housing, molded of flame-proof Diallyl Phthalate per MIL-M-14, Type SDG-F. These delay lines are designed to meet the applicable , w ith the low signal levels of TTL and ECL. These delay lines find extensive use in providing the , to provide the utmost in miniaturization and reliability. The MTBF on these delay lines , when , Mount DIP Series" Lumped Constant Passive Delay Lines developed by Engineered Components Company have


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PDF MIL-HDBK-217, D-1005 SMD-1010 SMD-101 D-1020 SMD-1025 SMD-1030 SMD-1040 SMD-1050 SMD-1060 d-101-00 SMD-580 SMD-2020 D5150 TIC 2060 SMD 2020 SMD-2030 SMD-2080 d20100 SMD-5100
FLDL-TTL-160

Abstract: 8527C
Text: -202, M ethod215. design notes The "Wee DIP Series" Logic Delay Lines developed by Engi neered , logic delay lines are of hybrid construc tion utilizing the proven technologies of active integrated , surface mount t2 l COMPATIBLE Wee DIP LOGIC DELAY UNE _ J % T^L FAST input , The SMFLDL-TTL is offered in 76 delays from b to 500ns. Delay tolerances are maintained as shown in the accompanying part number table, when tested underthe "Test Conditions" shown. Delay time is


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PDF SO-14 500ns 500ns. C/090894 FLDL-TTL-160 8527C
Not Available

Abstract: No abstract text available
Text: design notes The "W e e DIP S eries" Logic Delay Lines developed by Engineered C om ponents Company , logic delay lines are o f hybrid construction utilizing the proven technologies o f active in , surface mount t2 l COMPATIBLE Wee DIP LOGIC DELAY LINE 3 m illion hours. Module design , ­ put; no additional external com ponents are needed to obtain the desired delay . T^L input and output Delay stable and precise SO -14 pin pattern Wee DIP package (.23 5 high) Available in delays


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PDF 500ns
2006 - SMA1405

Abstract: active
Text: ACTIVE DELAY LINES , 5-TAP & 10-TAP THROUGH-HOLE & SURFACE MOUNT RESISTORS CAPACITORS COILS DELAY LINES A08 SERIES: 8-Pin DIP A14 SERIES: 14-Pin DIP SA08 SERIES: 8-Pin SIP SMA14 SERIES: 14-Pin SO , °C compatible RCD A0805AG 1 50NS 1 RCD A1410AG 100NS RCD's active delay lines have been designed to , . Excellent for applications requiring high delay stability, fast rise times and no jitter, such as memory , [10.2] max TYPE A0805AG (5-tap,8-pin SM ) .800 [20.3] Max 14 8 A0805 Schematic .285


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PDF 10-TAP 14-Pin SMA14 A1405 1000nS A0805AG A1410AG 100NS A0805, SMA1405 active
2006 - Not Available

Abstract: No abstract text available
Text: ACTIVE DELAY LINES , 5-TAP & 10-TAP THROUGH-HOLE & SURFACE MOUNT RESISTORS CAPACITORS COILS DELAY LINES A08 SERIES: 8-Pin DIP A14 SERIES: 14-Pin DIP SA08 SERIES: 8-Pin SIP SMA14 SERIES: 14-Pin SO , compliant 1 RCD A1410AG 100NS RoHS RCD's active delay lines have been designed to provide , . Excellent for applications requiring high delay stability, fast rise times and no jitter, such as memory , [10.2] max TYPE A0805AG (5-tap,8-pin SM ) .800 [20.3] Max 14 8 A0805 Schematic .285


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PDF 10-TAP 14-Pin SMA14 A1405 1000nS A0805AG A1410AG 100NS A0805,
2005 - RCD Components

Abstract: 100NS A0805 A1405 A1410 SA08 SMA14
Text: ACTIVE DELAY LINES , 5-TAP & 10-TAP THROUGH-HOLE & SURFACE MOUNT A08 SERIES: 8-Pin DIP A14 , 100NS 1 RCD's active delay lines have been designed to provide precise tap delays with all the , CAPACITORS COILS DELAY LINES RCD Components , voltage: 3.2V 2.) Input pulse width: 50nS or 1.2x the total delay (whichever is greater) 3.) Input rise time: 2.0nS (0.75V to 2.4V) 4.) Delay measured at 1.5V on leading edge only with no loads on output


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PDF 10-TAP 14-Pin SMA14 A1405 1000nS 500nS -1000nS RCD Components 100NS A0805 A1410 SA08
ut 803A

Abstract: SM803 b 803a SM805 SM803A
Text: Microcomuputer SM 803/ SM 803A/ SM 805/ SM 805A The Z 8 has 32 lines dedicated to input and o u t put. T h e , CMOS 8-Bit Single Chip Microcomuputer SM 803/ SM 803A/ SM 805/ SM 805A SM803/SM803A SM805/SM805A , 7 | d, u « -4 U C, z l TUT SHARP CM OS 8-Bit Single Chip Microcomuputer SM 803/ SM 803A/ SM 805/ SM 805A Features 1. Complete sing le-chip m icrocom puter with in ternal , (internal 4MHz): SM 803/ SM 80f> 8 MHz (internal 6 MHz): S M 8 0 3 A /S M 8 0 5 A 10. High speed


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PDF 803/SM 03A/SM 805/SM SM803/SM803A SM805/SM805A ut 803A SM803 b 803a SM805 SM803A
m80c85ah

Abstract: M80C88A-2 80C85AH
Text: Previous version: Aug. 1996 G ENERAL DESCRIPTION The M SM 80C86A-10 is com plete 16-bit CPUs im plem , andM SM 80C85AH hardw are and peripherals. FEATURES · 1 M byte D irect Addressable M em ory Space · , -pin Plastic D IP (DIP40-P-600-2.54): (Product name: M SM 80C86A-10RS) · 44-pin Plastic Q FJ (QFJ44-P-S650 , ) 371 LOGK(WR) ~31~l S^M /IO) ~3Q~I S7(DT/R) ~29~l SgfÏÏEN) NC \ T NC [ T ad5 [ T a d 4 Q tT ad3 Q I , ] S^M /ÏO) 2 A D , AD, M s7(Q T /ïï) o isi isi i§ i y ly isi isi y isi y isi « « 2. L


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PDF E200010-27-X2 MSM80C86A-10RS/GS/JS 16-Bit 80C86A-10 MSM80C88A-10 80C85AH 14-word 24-Operand m80c85ah M80C88A-2
2006 - P1410

Abstract: Inductors MIL-PRF-83531 P0805AG P0805
Text: PASSIVE DIP DELAY LINES , TAPPED SMP1410 - 14 PIN, 10 TAP SM P0805 - 8 PIN, 5 TAP DIP & SM P1410 - 14 PIN, 10 TAP DIP & SM P2420 - 24 PIN, 20 TAP DIP & SM RESISTORS CAPACITORS COILS DELAY LINES Term.W is RoHS compliant RoHS RCD's passive delay line series are a lumped constant , Delay Tolerance Tap Delay Tolerance Temperature Coefficient Insulation Resistance Dielectric , : Delay Impedance Total TR: Max Rise TD: Delay Delay (nS) Time (nS) per Tap (nS) Values (±10% ) Time


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PDF SMP1410 P0805 P1410 P2420 P1410, P1410A SMP1410, P0805, P2420) Inductors MIL-PRF-83531 P0805AG
Not Available

Abstract: No abstract text available
Text: SMFMLDL-TTL is offered in forty-two (42) delays from 5ns to 250ns. Each module includes two (2) separate delay lines , each isolated and fully buffered. Delay tolerances are maintained, as shown in the accompanying part number table, when tested underthe "Test Conditions" shown. Delay time is measured at the +1.5V , FAST T2L circuits. These logic delay lines are of hybrid construction utilizing the proven technologies , surface mount t2 l CO M PATIBLE Wee DIP M U LTI-LO G IC J DELAY LINE # T2 L FAST input and


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PDF SO-14 250ns 250ns. C/102794
SM DELAY LINES

Abstract: No abstract text available
Text: com patible with F A S T T 2L circuits. These logic delay lines are of hybrid construc tion utilizing , surface mount t 2l COMPATIBLE Wee DIP LOCIC DELAY LINE # T2L FAST in p u t and o u tp u t # , inversion. The delay m odules are intended prim arily for use w ith positive going pulses and are calibrated to the tolerances show n in the table on rising edge delay ; w here best accuracy is desired in , elay Lines developed by Engi neered C om ponents C om pany have been designed to provide precise delays


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PDF SO-14 500ns L-TTL-410 L-420 L-TTL-430 L-TTL-440 L-TTL-450 L-TTL-460 L-TTL-470 L-TTL-480 SM DELAY LINES
SM DELAY LINES

Abstract: No abstract text available
Text: Independent fo r Input/O utput · Lead Free Com patible · Sm all P hase R ipple · P aten t P ending EMC Technology's miniature ceramic delay lines are ideal for feed forward amplifiers or other applications where phase balance is critical. The Delay Lines are surface mount parts available in leadless or ball grid mounting. The devices have a small footprint and a low profile. Delay Lines are lead free and compatible , (ira Tcclmob<$/ Introduction M iniature D elay Line Features · Sm all P ackage Size · ·


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PDF 10ppm SM DELAY LINES
51426-2

Abstract: No abstract text available
Text: September 1992 O K I Semiconductor M SM 514262-JS/ZS_ 262,144-Word x 4 , ■M SM 514262 M ultiport DRAM ■PIN CONFIGURATION sc S I0 1 STÜ2 Ü T /Ö F W1 /1 0 , SEMICONDUCTOR ■M SM 514262 M ultiport DRAM ■FUNCTIONAL BLOCK DIAGRAM OKI SEMICONDUCTOR 3 ■M SM 514262 M ultiport DRAM ■ELECTRICAL CHARACTERISTICS Absolute Maxim um Ratings ^ , < O ° Output high voltage ■M SM 514262 M ultiport DRAM ■DC Characteristics 2: RAM


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PDF 514262-JS/ZS_ 144-Word MSM514262 512-word MSM514262 51426-2
Not Available

Abstract: No abstract text available
Text: SURFACE MOUNTING DIGITAL DELAY LINES TTL AND DTL COMPATIBLE 5 TAPS*G AND J LEADS SERIES GSMT , •0 3 i Suggested P.C. Board solder pads for G SM T & JSMT. h intermediate delay values available upon request. L IM IT S D C PARAM ETERS M ode l N o . G Style G SM T25 G SM T 30 G SM T45 G SM T 50 G SM T75 G SM T 100 G SM T125 G SM T 150 G SM T200 G SM T250 J Style Total D elay (ns) J SM T 25 JSM T 30 J SM T 4 5 JSM T 50 JSM T 75 JSM T100 J SM T 125 JSM T 1 5 0


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SM DELAY LINES

Abstract: No abstract text available
Text: Stability Orientation Independent fo r Input/Output Applications EMC Technology's ceramic Delay Lines are ideal fo r feed forward amplifiers. The Delay Lines are surface mount parts available in leadless , Num ber Frequency (MHz) Delay (ns) Delay Accuracy (ns) Insertion Loss (dB Typ. @ 1 GHz) Return Loss , SM T Leadless SM T with Ball Grid E M C T e c h n o lo g y 8851 SW Old Kansas Ave. Stuart FL 34997


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sm-tech

Abstract: 90Pb
Text: equipment, and inductive components designed and built specifically for use on our new product lines , Rhombus is able to offer cost effective, highly reliable product lines for through-hole as well as surface mount applications. Rhombus has an extensive offering of surface mount delay lines and pulse , auto-insertable through-hole series. RECOMMENDED SOLDER PADS ( Delay Lines ): Standard Gullwing SMD Rhombus , rework costs and time are significantly reduced. Many manufacturers have setup production lines that


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Not Available

Abstract: No abstract text available
Text: Stability Orientation Independent fo r Input/Output Applications EMC Technology's ceramic Delay Lines are ideal fo r feed forward amplifiers. The Delay Lines are surface mount parts available in leadless , Number Frequency (MHz) Delay (ns) Delay A ccuracy (ns) Insertion Loss (dB Typ. @ 1 GHz) Return Loss (dB M , .) Height (mm) System Error Correction Ordering Inform ation Part N um ber D20 D20B Package SM T Leadless SM T ivith Ball Grid EMC T e ch n o lo g y 8851 SW Old Kansas Ave. Stuart FL 34997 (772


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Siemens PEB 2040

Abstract: PCM SWITCH SM DELAY LINES TS1273 TS0B
Text: Input PCM Lines and Speech Memory for all 512 Subscribers On-Chip • Connection Memory for 256 Channels of 8 Output Lines On-Chip • Non-Blocking Time Switch with 16/16 PCM Lines can be Built with Two Devices • jLiP-lnterface for Writing and Reading the Connection Memory • Delay Between Input and Output Lines Selectable • Tristate for Further Expansion or Hot Standby • Advanced NMOS Technology , connect any of the 512 PCM channels of 16 incoming PCM lines to any of the 256 PCM channels of 8 output


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PDF
Not Available

Abstract: No abstract text available
Text: Control A ctive Delay 2 Control Inactive Detay Address Float to R D Active R D Acrive Delay M SM 80C88A , -10RS/GS/JS » M SM 80C88A -10 Parameter R D Inactive Delay R D Inactive to Next Address A ctive H L D A V , Responses M SM 80C88A -10 U n it Min. Command A ctive Delay (See Note 1) Command Inactive Delay (See Note 1 , Th e M SM 80 C 8 8 A -1 0 are internal 16-bit C P U s w ith 8-bit interface implemented in Silico n , icroprocessor. It is directly com patible w ith M SM 80 C 8 8 A -1 0 software and M SM 80 C 8 5 A /M SM 80 C 8 5


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PDF MSM80C88A-10RS/GS/US 16-bit OS8G88-1, 80C86A
Not Available

Abstract: No abstract text available
Text: Normal DMA mode - Extended Interrupt mode - Extended DMA mode n 6, 8, or 11 ISA-bus interrupt lines and 3 DRQ/DACK lines supported (IRQ 's and DRQ's are mode dependent) n On-chip EEPROM for resource , > IORD* (Note 1) , SM EM R* (Note 1) IOWR* (Note 1) , SM EM W * (Note 1) AEN SD<7:0> OSC (Note 2) RSTDRV , ISA bus- used for internal state machine. Reset input from the ISA bus. Clock and Data input lines , request pins. On-chip interrupt requests may be connected to any of the 6 lines . Interrupt request line to


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PDF NM95MS15
560 ohm RESISTOR

Abstract: B12-B1 68-PIN SMJ34061GB
Text:  SM / SM J34061 VIDEO SYSTEM CONTROLLER Generates User-Programmable Control Signals (Horizontal , Address Space with Arbitrary Word Width • Standard and Class B Processing — SM Prefix . . . Standard , Electronic-Library Service CopyRight 2003 SM / SM J34061 VIDEO SYSTEM CONTROLLER PIN ASSIGNMENTS (GB PACKAGE) PIN , Service CopyRight 2003 SM / SM J34061 VIDEO SYSTEM CONTROLLER typical system block diagram *- CRT , €¢ HOUSTON. TEXAS 7 7001 14-285 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SM / SM


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PDF J34061 SMJ4161 560 ohm RESISTOR B12-B1 68-PIN SMJ34061GB
Siemens PEB 2040

Abstract: L200 siemens c60s5 PCM SWITCH
Text: PCM Lines and Speech Memory for all 512 Subscribers On-Chip · Connection Memory for 256 Channels of 8 Output Lines On-Chip · Non-Blocking Time Switch with 16/16 PCM Lines can be Built with Two Devices · juP-lnterface for Writing and Reading the Connection Memory · Delay Between Input and Output Lines Selectable · , of 16 incoming PCM lines to any of the 256 PCM channels of 8 output lines . A block diagram of the , speech memory SM . That means that all 512 8-bit words are written into a fixed position of the SM


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SMJ4161

Abstract: 560 ohm RESISTOR
Text:  SM / SM J34061 VIDEO SYSTEM CONTROLLER JULY 1987 Generates User-Programmable Control Signals , Space with Arbitrary Word Width • Standard and Class B Processing — SM Prefix . . . Standard , Manufacturer SM / SM J34061 VIDEO SYSTEM CONTROLLER PIN ASSIGNMENTS (GB PACKAGE) pin function pin function , Manufacturer SM / SM J34061 VIDEO SYSTEM CONTROLLER typical system block diagram host processor jaddress bus , 77001 This Material Copyrighted By Its Respective Manufacturer SM / SM J34061 VIDEO SYSTEM CONTROLLER


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PDF J34061 SMJ4161 sgus010 560 ohm RESISTOR
2006 - SMP01S

Abstract: Inductors P01AG
Text: PASSIVE SIP DELAY LINES , SINGLE OUTPUT RESISTORS CAPACITORS COILS DELAY LINES SMP01S - 4 PIN SM P01S - 4 PIN DIP P01 - 14 PIN DIP & SM S01 - 3 PIN SIP Industry's widest range: 0.1nS to 1000nS , RoHS Term.W is RoHS compliant RCD's passive delay lines are a lumped constant design , . 100V D C ±10% Max. OPTIONS Custom circuits, delay and/or impedance values MIL-D-23859 screening , coefficient Faster rise times RCD Type Delay Time, TD (nS) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.5 1.0


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PDF SMP01S 1000nS 100NS, 1000NS, FA105 GF-061. Inductors P01AG
Not Available

Abstract: No abstract text available
Text: Delay Lines are digitally programmable by the presence of either a " 1 " or a " 0 " at each of the , Programmable Logic Delay Lines developed by Engineered Com ponents C om p any have been designed to allow for final delay adjustment during or after in stallation in a circuit. These Logic Delay Lines incorporate , T A IL IS SHOWN BELOW .600-n n n .200 SM PDLTTL-7- Delay time is , Logic Delay Lines are packaged in a S O -1 6 DIP housing, molded of flame-proof Diallyl Phthalate per M


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PDF 357ns
Supplyframe Tracking Pixel