The Datasheet Archive

SIT9005ACB1H-28NM datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
SIT9005ACB1H-28NM SIT9005ACB1H-28NM ECAD Model SiTIME Crystals, Oscillators, Resonators - Programmable Oscillators - MEMS OSC PRG SSXO LVCMOS CS 2.8V Original PDF

SIT9005ACB1H-28NM Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - Parallel FIR Filter

Abstract: FPGA IMPLEMENTATION of Multi-Rate FIR Altera 28-nm Portfolio OPTIMIZED FPGA IMPLEMENTATION OF MULTI-RATE FIR Signal Path Designer radar fir filter DSP processor latest version in 2010 how dsp is used in radar FIR FILTER implementation on fpga 28nm
Text: Implementing FIR Filters and FFTs with 28-nm Variable-Precision DSP Architecture WP , . This white paper introduces the DSP architecture of the latest 28-nm Altera® FPGAs and shows how this , least resources. At the 28-nm process node, Altera has developed the FPGA industry's first , precision and performance requirements to be implemented using the 28-nm silicon fabric with two to three , Features This innovative 28-nm DSP architecture is also designed with key features that enable the


Original
PDF 28-nm WP-01140-1 ebcasts/all/wc-2010-dsp-var-prec-dsp-arch erature/wp/wp-01131-stxv-dsp-architecture Parallel FIR Filter FPGA IMPLEMENTATION of Multi-Rate FIR Altera 28-nm Portfolio OPTIMIZED FPGA IMPLEMENTATION OF MULTI-RATE FIR Signal Path Designer radar fir filter DSP processor latest version in 2010 how dsp is used in radar FIR FILTER implementation on fpga 28nm
2011 - format .rbf

Abstract: FIPS-197 3A991 AN425 BR1220 BR2477A
Text: application note describes how you can use the design security features in Altera® 40- and 28-nm FPGAs to , configuration files. This application note provides the hardware and software requirements for the 40- and 28-nm , configuration flow. 1 This application note uses the term "40-nm" or " 28-nm " FPGAs. Table 1 lists the , Encryption Enabled" on page 29 "JTAG Secure Mode for 28-nm FPGAs" on page 32 "US Export , Approach 40-nm FPGA 28-nm FPGA Non-volatile key The non-volatile key is stored in polyfuses


Original
PDF AN-556-2 28-nm 40-nm" 28-nm" format .rbf FIPS-197 3A991 AN425 BR1220 BR2477A
2010 - matrix circuit VHDL code

Abstract: led matrix 32X32 vhdl code for FFT 32 point vhdl code for cordic LU decomposition 32x32 multiplier verilog code 64x64-bit ieee floating point multiplier verilog vhdl code for cordic multiplication verilog code for matrix multiplication inverse trigonometric function vhdl code
Text: Achieving One TeraFLOPS with 28-nm FPGAs WP-01142-1.0 White Paper Due to recent , (teraFLOPS) are feasible-and on a single FPGA die. Introduction Altera's 28-nm Stratix® V FPGAs family , , Altera has developed a new variableprecision DSP architecture for 28-nm FPGAs. By giving the designer the , with 28-nm FPGAs September 2010 Altera Corporation FPGA-specific Optimizations for , Corporation - Do not apply special or error conditions here Achieving One TeraFLOPS with 28-nm FPGAs


Original
PDF 28-nm WP-01142-1 28-nm matrix circuit VHDL code led matrix 32X32 vhdl code for FFT 32 point vhdl code for cordic LU decomposition 32x32 multiplier verilog code 64x64-bit ieee floating point multiplier verilog vhdl code for cordic multiplication verilog code for matrix multiplication inverse trigonometric function vhdl code
2009 - precision

Abstract: No abstract text available
Text: Enabling High-Performance, High-Precision Signal Processing 28-nm Variable-Precision DSP Block Architecture More than ever, digital signal processing (DSP) applications need high performance and high precision, in the greater than 18-bit range. That's why the DSP capabilities of FPGAs are ideal. In our 28-nm Stratix® V FPGAs, you can take advantage of our new variable-precision DSP blocks to support a variety of , Multiplier Size Competing DSP Architecture Altera 28-nm Advantage Native support for 27x27


Original
PDF 28-nm 18-bit SS-01066-1 precision
2010 - lpddr2

Abstract: samsung lpddr2 samsung* lpddr2 lpddr2 phy micron lpddr2 ibm edram lpddr2 datasheet 28-nm LPDDR2 SDRAM samsung micron lpddr2 datasheet
Text: stack extends the CMOS process technology well beyond 32/ 28nm . Samsung Foundry, in conjunction with the IBM Joint Development Alliance (JDA), tuned its 32/ 28nm LP High-k Metal Gate (HKMG) gate-first , , immersion lithography is a critical feature of Samsung Foundry's 32/ 28nm process flow. Samsung has the , from leading companies such as ARM. · Manufacturing plant ­ Maintains advanced 90, 65, 45, 32/ 28nm , Turn-key management SHIP PRODUCTS Samsung 65/45/32/ 28nm IP Solutions Standard Cell Library CPUs


Original
PDF BRO-07-SLSI-001 lpddr2 samsung lpddr2 samsung* lpddr2 lpddr2 phy micron lpddr2 ibm edram lpddr2 datasheet 28-nm LPDDR2 SDRAM samsung micron lpddr2 datasheet
2010 - tcam

Abstract: ternary content addressable memory 100GbE Altera Stratix V 10Gbase-kr transmitter receiver ber fec 100G 40GBASE-R 100g phy interlaken network processor datasheets of optical fpgas
Text: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As , 28-nm technology node. Introduction Two qualities are important in a network: speed and , rate of 40 Gbps Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs July 2010 Altera , Challenges on 28-nm FPGAs Page 4 40-GbE and 100-GbE IEEE 802.3ba Standards Figure 3. 100-GbE Line , -GbE Line-Card Design Challenges on 28-nm FPGAs July 2010 Altera Corporation Addressing the Challenges of


Original
PDF 100-GbE 28-nm WP-01128-1 40-GbE/100-GbE tcam ternary content addressable memory 100GbE Altera Stratix V 10Gbase-kr transmitter receiver ber fec 100G 40GBASE-R 100g phy interlaken network processor datasheets of optical fpgas
2010 - OTN SWITCH

Abstract: OC192 muxponder stratixv
Text: Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs WP , reconfiguration. Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs , Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs Page 4 Implementation in the , . Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs July 2010 Altera , Reconfiguration in 28-nm FPGAs Page 6 Partial Reconfiguration Feature Application Figure 3. Block


Original
PDF 28-nm WP-01137-1 100G-Optical OTN SWITCH OC192 muxponder stratixv
2010 - matlab code for radix-4 fft

Abstract: matlab code for half adder FPGA "video wall" FFT 1024 point matlab code using 64 point radix 8 matlab code for fft radix 4 matlab code for mimo wireless radar dsp processor radar fir filter FIR filter matlaB simulink design
Text: Accelerating DSP Designs with the Total 28-nm DSP Portfolio WP-01136-1.0 White Paper , Subscribe Page 2 Altera's Total 28-nm DSP Portfolio These systems not only have different , functions that are optimized for the FPGA architecture. Altera's Total 28-nm DSP Portfolio The biggest , algorithms. To support the 28-nm Stratix® V FPGAs, Altera offers a total DSP portfolio, which, as , - Accelerating DSP Designs with the Total 28-nm DSP Portfolio July 2010 Altera Corporation


Original
PDF 28-nm WP-01136-1 com/b/28-nm-dsp-portfolio s/all/wc-2010-accelerate-fpga-dsp-designs matlab code for radix-4 fft matlab code for half adder FPGA "video wall" FFT 1024 point matlab code using 64 point radix 8 matlab code for fft radix 4 matlab code for mimo wireless radar dsp processor radar fir filter FIR filter matlaB simulink design
2010 - Optical SAS QSFP

Abstract: CEI-6G-LR QSFP 32G 28G-SR CEI-11G QSFP QSFP 25G QSFP CONNECTOR interlaken ibis sata
Text: -Gbps transceiver industry, highlights the challenges, and introduces 28-nm silicon and productivity solutions that , step further in the 28-nm generation. Smaller feature sizes imply shorter channel lengths for , ) Altera's 28-nm Stratix® V FPGAs deliver the highest bandwidth and levels of system integration, and , Chip-to-chip, chip-to-module, cable 1 to N 28-nm Transceiver Block Architecture Altera's 28-nm , 3 Extending Transceiver Leadership at 28 nm Altera Corporation 28-nm Transceiver Power


Original
PDF 28-Gbps Optical SAS QSFP CEI-6G-LR QSFP 32G 28G-SR CEI-11G QSFP QSFP 25G QSFP CONNECTOR interlaken ibis sata
Not Available

Abstract: No abstract text available
Text: This application note describes how you can use the design security features in Altera 40- and 28-nm , configuration files. This application note provides the hardware and software requirements for the 40- and 28-nm , configuration flow. Note: This application note uses the term "40-nm" or " 28-nm " FPGAs. The following table , 40-nm FPGA 28-nm FPGA 1 Non-Volatile key The non-volatile key is securely stored in fuses , is validated as conforming to the Federal Information Processing Standards FIPS-197. 1 For 28-nm


Original
PDF AN-556 28-nm 40-nm" 28-nm"
2010 - ROADM

Abstract: Altera Stratix V muxponder 2.5G DWDm OC192
Text: White Paper Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs The rapid growth in , -01126-1.0 April 2010, ver. 1.0 1 Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs Altera , Corporation Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs Figure 3. Block Diagram of 100 , . Implementing 100-Gbit OTN Muxponders in Stratix V FPGAs Altera's 28-nm Stratix V FPGAs are designed with a , -Gbit OTN Muxponder Solutions on 28-nm FPGAs Altera Corporation Figure 4. Block Diagram of a 100


Original
PDF 100-Gbit 28-nm 10-Gbit 10-Gbit-based ROADM Altera Stratix V muxponder 2.5G DWDm OC192
2010 - b 103g

Abstract: interlaken ternary content addressable memory WP-01127-1 Altera Stratix V tcam interlaken network processor computer networking diagram optical switch fabric Double high-speed switching diode
Text: Integrating 100-GbE Switching Solutions on 28-nm FPGAs WP-01127-1.1 White Paper With , connection from I1 to O2 inhibits the path from I2 to O1. Integrating 100-GbE Switching Solutions on 28-nm , -GbE Switching Solutions on 28-nm FPGAs Page 4 Backplane Switching Backplane Switching A backplane , -GbE Switching Solutions on 28-nm FPGAs July 2010 Altera Corporation Implementing Crossbar Switching and Backplane Switching Page 5 Implementing Crossbar Switching and Backplane Switching Altera's 28-nm


Original
PDF 100-GbE 28-nm WP-01127-1 b 103g interlaken ternary content addressable memory Altera Stratix V tcam interlaken network processor computer networking diagram optical switch fabric Double high-speed switching diode
2010 - RAM SEU

Abstract: AN357 M20K engine injection controller altera MTBF Altera Stratix V Altera 28nm Device
Text: Enhancing Robust SEU Mitigation with 28-nm FPGAs WP-01135-1.0 White Paper Systems designed , , modern high-end devices, such as Altera's 28-nm Stratix V FPGAs, must offer robust SEU mitigation , user memory. Enhancing Robust SEU Mitigation with 28-nm FPGAs July 2010 Altera Corporation , Corporation Enhancing Robust SEU Mitigation with 28-nm FPGAs Page 4 Configuration RAM Soft-Error , in Flash Enhancing Robust SEU Mitigation with 28-nm FPGAs July 2010 Altera Corporation User


Original
PDF 28-nm WP-01135-1 com/literature/an/an357 RAM SEU AN357 M20K engine injection controller altera MTBF Altera Stratix V Altera 28nm Device
2013 - Not Available

Abstract: No abstract text available
Text: Product Brief CAT-DACIQ12B160M-28 CAT-DACIQ12B122M-28 CAT-DACIQ12B80M-28 12-Bit, 160Msps, I/Q DAC IP Core in 28nm General Description The CAT-DACIQ12B160M-28 is a complete state-of-theart dual digital-to-analog converter (DAC) specifically designed for analog front-end (AFE) that is , -28 CAT-DACIQ12B122M-28 CAT-DACIQ12B80M-28 12-Bit, 160Msps, I/Q DAC IP Core in 28nm Recommended Operating , in 28nm Electrical Characteristics (continued) (Over recommended operating junction temperature


Original
PDF CAT-DACIQ12B160M-28 CAT-DACIQ12B122M-28 CAT-DACIQ12B80M-28 12-Bit, 160Msps, CAT-DACIQ12B160M-28 160MHz. 10MHz
2010 - 28HP

Abstract: pcie gen3 10GBASE-KR CPRI Multi Rate class 10 up board Datasheet 2012 Altera Stratix V 28Gbps 28-nm tflops 10Gbase-kr transmitter
Text: techniques only go so far. FPGA vendors must find innovative ways to go beyond Moore's Law on the 28-nm , is no exception. The 28-nm process delivers clear performance benefits, but to realize the full potential of these benefits, the proper "flavor" of the 28-nm process must be selected. Altera chose the , processes without strained silicon. No other 28-nm process flavor has this potent combination of HKMG and , used technologies at the 28-nm process node are used to maintain or increase performance while


Original
PDF WP-01125-1 28-Gbps ebcasts/all/wc-2010-introducing-stratix-v 28HP pcie gen3 10GBASE-KR CPRI Multi Rate class 10 up board Datasheet 2012 Altera Stratix V 28Gbps 28-nm tflops 10Gbase-kr transmitter
2013 - Not Available

Abstract: No abstract text available
Text: Product Brief CAT-ADP12B160M-28 CAT-ADP12B123M-28 CAT-ADP12B80M-28 12-Bit, 160Msps, Pipeline ADC IP Core in 28nm General Description The CAT-ADP12B160M-28 is an ultra-low-power, highperformance analog-to-digital converter (ADC) IP core that operates up to 160Msps. It is ideally suited for , -28 CAT-ADP12B123M-28 CAT-ADP12B80M-28 12-Bit, 160Msps, Pipeline ADC IP Core in 28nm Recommended Operating , -28 CAT-ADP12B80M-28 12-Bit, 160Msps, Pipeline ADC IP Core in 28nm Electrical Characteristics (continued


Original
PDF CAT-ADP12B160M-28 CAT-ADP12B123M-28 CAT-ADP12B80M-28 12-Bit, 160Msps, CAT-ADP12B160M-28 160Msps.
2012 - xc7z020

Abstract: ZYNQ-7000 XC7Z020-1CLG484CES XC7Z XC7Z020-1CLG484C ZC702 Xilinx Ethernet development RGMII phy Xilinx male header xilinx DDR3 controller user interface
Text: Xilinx 28nm scalable optimized programmable logic architecture. Additional reference designs and , dual-core CortexTM-A9 processor meets Xilinx 28nm programmable logic · ASIC-like performance and power with


Original
PDF ZYNQ-7000 ZC702 ZYNQTM-7000 xc7z020 XC7Z020-1CLG484CES XC7Z XC7Z020-1CLG484C Xilinx Ethernet development RGMII phy Xilinx male header xilinx DDR3 controller user interface
2013 - Not Available

Abstract: No abstract text available
Text: fractional phase-locked loop (PLL) reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm , : ■“Functional Description” ■“Fractional PLL Reconfiguration in 28-nm Devicesâ , clock in the PLLs of 28-nm devices. You can also change the charge pump and loop filter components , reconfiguring the entire FPGA. Fractional PLL Reconfiguration in 28-nm Devices The fractional PLLs in 28-nm , fractional PLLs in 28-nm devices support dynamic reconfiguration. While the device is in user mode, you can


Original
PDF AN-661-3 28-nm 28-nm
2012 - Not Available

Abstract: No abstract text available
Text: fractional phase-locked loop (PLL) reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm , : ■“Functional Description” ■“Fractional PLL Reconfiguration in 28-nm Devicesâ , clock in the PLLs of 28-nm devices. You can also change the charge pump and loop filter components , reconfiguring the entire FPGA. Fractional PLL Reconfiguration in 28-nm Devices The fractional PLLs in 28-nm , fractional PLLs in 28-nm devices support dynamic reconfiguration. While the device is in user mode, you can


Original
PDF AN-661-2 28-nm 28-nm
2014 - Marvell SSD controller

Abstract: marvell hard disk controller 88NV1140/88NV1120 88NV1120/88NV1140
Text: new controller design is also optimized for small-form factor applications. By using 28nm CMOS , low-power management (L1.2) design •• Advanced 28nm CMOS process Marvell 88NV1120/88NV1140 TARGET


Original
PDF 88NV1140/88NV1120 88NV1140/88NV1120 128GB 88NV1120 88NV1140 Marvell SSD controller marvell hard disk controller 88NV1120/88NV1140
2010 - interlaken

Abstract: 10GBASE-KR pcie gen3 optical 400G M20K 100g phy CPRI multi rate 400G 28Gbps Stratix V
Text: possible through Moore's Law. Our new 28-nm Stratix® V FPGAs address bandwidth, cost, and power , , migrate your Stratix V designs to our new 28-nm HardCopy V ASICs. Also with transceiver variants , · 28-nm high-K metal gate manufacturing process optimized for low power ·0.85-V core voltage ·Partial , capabilities in our new 28-nm devices can support a wide range of next-generation designs. Wireline


Original
PDF 28-nm GB-01009-3 interlaken 10GBASE-KR pcie gen3 optical 400G M20K 100g phy CPRI multi rate 400G 28Gbps Stratix V
2014 - Not Available

Abstract: No abstract text available
Text: application targeted, high-end FPGAs and are half the power and half the cost of high-end, 28-nm FPGAs. The , -nm Tri-Gate transistors consume 50% less power and are nearly 40% faster than transistors built on 28-nm


Original
PDF SPEEDSTER22i 10/40/100G 22-nm PB024
2010 - Altera Stratix V

Abstract: QSFP 40G transceiver CEI-28G QSFP 10G JTRS otu 4 M20K 400G QSFP optical 400G
Text: optical networking. Altera's 28-nm Stratix® V FPGAs combine the flexibility needed to adapt to changing , protocol variants while having the highest performance 28-nm reprogrammable logic available. This , . These 28-nm FPGAs combine the flexibility needed to adapt to changing network standards and support , : www.altera.com/literature/wp/wp-01125-stxv- 28nm -innovation.pdf 6. White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs: www.altera.com/literature/wp/wp


Original
PDF WP-01138-1 28-nm Altera Stratix V QSFP 40G transceiver CEI-28G QSFP 10G JTRS otu 4 M20K 400G QSFP optical 400G
2002 - OPC-WD247-31100

Abstract: 120X80X10 cwdm add drop
Text: Adjacent Channel Isolation @c+1.2nm (dB) N/A 30 Non-Adjacent Channel Isolation @c+ 2.8nm (dB) N


Original
PDF OPC-WD247-31100 120x80x10 OPC-WD247-31100 120X80X10 cwdm add drop
GR-1209

Abstract: OPC-DD221-31100
Text: Adjacent Channel Isolation @c+1.2nm (dB) N/A 25 Non-Adjacent Channel Isolation @c+ 2.8nm (dB) N


Original
PDF 200GHz GR-1209 OPC-DD221-31100 120x80x10 OPC-DD221-31100
Supplyframe Tracking Pixel