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Part Manufacturer Description Datasheet Download Buy Part
TRF4002PWP Texas Instruments RF Power Amplifier ASIC 20-HTSSOP
PMP5738 Texas Instruments High current core/ASIC/FPGA supply
SM28VLT32SKGD1 Texas Instruments 32-Mbit High-Temp Flash ASIC With Serial Peripheral Interface (SPI) Bus 0-XCEPT
DBB03AIPMR Texas Instruments Digital Baseband ASIC for Dolphin Chipset 64-LQFP -40 to 85
DBB03IPMR Texas Instruments Digital Baseband ASIC for the Dolphin Chipset 64-LQFP -40 to 85
DBB03IPM Texas Instruments Digital Baseband ASIC for the Dolphin Chipset 64-LQFP -40 to 85

SHA-256 asic Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - SHA-256 Cryptographic Accelerator

Abstract: verilog code for 128 bit AES encryption CS5311 SHA-1 using vhdl verilog code for 8 bit AES encryption SHA-256 verilog code for aes encryption SHA-512 SHA256 verilog code for 32 bit AES encryption
Text: including SHA- 256 , SHA-384, and SHA-512. These cores are available for both ASIC and programmable logic , ) and provides authentication between users during data transmission. The CS5311 core provides SHA- 256 , CS5310 SHA-2 CS5311 CS5312 · · Fully implements SHA- 256 secure hash algorithms to NIST FIPS 180-2 specifications · Fully implements SHA- 256 , SHA-384, SHA-512 secure hash algorithms to NIST , cycles (1 clock per algorithm step + 1 clock load) · · · Each 512-bit block for SHA- 256


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PDF CS5310/11/12 CS5310/11/12 CS5310 CS5311 SHA-256 DS5310 SHA-256 Cryptographic Accelerator verilog code for 128 bit AES encryption SHA-1 using vhdl verilog code for 8 bit AES encryption verilog code for aes encryption SHA-512 SHA256 verilog code for 32 bit AES encryption
2008 - SHA-256 asic

Abstract: SHA256 SHA-256
Text: Compliant to FIPS 180-2 specifi- cation of SHA- 256 . Bit padding. SHA256 SHA- 256 Secure , is a high-performance implementation of the SHA- 256 Secure Hash message digest Algorithm. This , . Optimized design for ASIC or The processing of one 512-bit block is performed in 66 clock cycles and the , implementation, running at 280 MHz and requiring just 20,500 gates in a 0.18 µm ASIC process. The complete , Results The following are sample ASIC results with all I/Os assumed to be routed off-chip using I/O


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PDF SHA-256. SHA256 SHA-256 SHA256 SHA-256 asic
2008 - SHA-256

Abstract: 3SE50F484-2 sha256 HC210F484C 3C16F484 SHA-256 mbps 1C12F324-6 megafunction EP1AGX50 SHA-256 mbps asic
Text: Compliant to FIPS 180-2 specification of SHA- 256 . Bit padding. SHA256 SHA- 256 Secure Hash Function Megafunction The SHA256 megafunction is a high-performance implementation of the SHA- 256 Secure Hash message digest Algorithm. This one-way hash function conforms to the 1995 US Federal Information , streaming applications. Optimized design for ASIC or FPGA implementations. Robust verification , soft megafunction (synthesizable HDL) for ASIC technologies and as a firm megafunction (netlist) for


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PDF SHA-256. SHA256 SHA-256 SHA256 512-bit 3SE50F484-2 HC210F484C 3C16F484 SHA-256 mbps 1C12F324-6 megafunction EP1AGX50 SHA-256 mbps asic
SHA-256 mbps asic

Abstract: SHA-256 DTLs ecdsa SHA-256 asic Intel 8202 AES-GCM-128 gzip 8200S ECDH-256
Text: power consumption per command · Small form factor · No external memory required · SHA-1, SHA- 256 · MD5 aSIC Specifications Public Key · RSA and DH up to 8k-bits, DSA · ECDH and ECDSA ( 256 , · eLZS, LZS, GZIP (Deflate RFC 1951) Encryption / Decryption · AES (128, 192, 256 ) CBC, GCM, CTR, ECB, XTS- 256 , XTS-512 · 3DES, DES, ARC4 Authentication · Software failover protection , Temperature sensor Reliability and Service Features · AES-GMAC, -XCBC-MAC · HMAC-SHA-1, - 256 ; HMAC-MD5


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2008 - sha256

Abstract: SHA-256 3s500e-5
Text: Compliant to FIPS 180-2 specifi- cation of SHA- 256 . Bit padding. SHA256 SHA- 256 Secure Hash Function Core 264-1 bits maximum message length. Supported Message lengths mul- tiple , is a high-performance implementation of the SHA- 256 Secure Hash message digest Algorithm. This , . Optimized design for ASIC or The processing of one 512-bit block is performed in 66 clock cycles and the , available as a soft core (synthesizable HDL) for ASIC technologies and as a firm core (netlist) for FPGA


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PDF SHA-256. SHA256 SHA-256 SHA256 3s500e-5
2009 - Not Available

Abstract: No abstract text available
Text: -1, SHA- 256 • MD5 • HMAC-SHA-1, HMAC-SHA- 256 • HMAC-MD5 • SSL3.0-MAC aSIC , €¢ Software failover protection (All HW functionality) in case of device failure • AES (128, 192, 256 ) CBC, GCM, CTR, ECB, GMAC, XCBC-MAC, XTS- 256 , XTS-512 • 3DES Hashing for Authentication or , -bits, DSA • ECDH and ECDSA ( 256 -bit, 384-bit, 521-bit) • Hardware random number generator PCI , ) Host Utilities and Applications Power-on Self Test (POST); DMA and ASIC configuration; error log


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PDF PB-8200Series-1-0110
2007 - MCS8140CV

Abstract: MCS8140 DATASHEET MosChip ARM926EJ-S pci parallel port moschip MCS8140 voip codec chip pc100 system board MCS8140 USER MANUAL MII switch
Text: . 7 Ver1.1 1 8th September 2007 MCS8140 Hardware FAQ MCS8140 Hardware ( ASIC & System , MCS8140 ASIC , its features, System related queries & other details concerning the ASIC , hardware design , the DES, 3DES, AES, MD5, SHA-1, and SHA- 256 algorithms. The interface pins for the on-chip I2S audio , MCS8140 ASIC is under Mass Production, ordering information given below: Part Type : MCS8140CV Package : QFP 256 , RoHS Commercial Grade : 0 to 70 deg C Contact sales@moschip.com for further information. d


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PDF MCS8140 MCS8140 MCS8140, MCS8140. MCS8140CV MCS8140 DATASHEET MosChip ARM926EJ-S pci parallel port moschip voip codec chip pc100 system board MCS8140 USER MANUAL MII switch
z80 vhdl

Abstract: TC190 TOSHIBA TC160 LSI CMOS GATE ARRAY toshiba TC200 PLL in RTL tc260c TOSHIBA TC203 TX49 5V/130nm CMOS
Text: 250 MHz 2, 4, 8 Mb 128/ 256 , 144/288 2, 4, 8 Mb 128/ 256 , 144/288 7 ASIC , CMOS ASIC s e mi con duc t or http://www.semicon.toshiba.co.jp/ 2006-9 ASIC ASIC IC 3 C O N T E N T S ASIC 3 ASIC 4 5 ASIC 8 UniversalArrayTM QTAT Solution for SoC Designs 11 SoC EDA 12 16 18 2 ASIC ASIC


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PDF TC320 TC300 TC280 TC260 TC200 TC203 TC220 TC223 TC190 TX49RISC z80 vhdl TC190 TOSHIBA TC160 LSI CMOS GATE ARRAY toshiba TC200 PLL in RTL tc260c TOSHIBA TC203 TX49 5V/130nm CMOS
2005 - ARM SC100

Abstract: ARM RNG AES RSA chips AT91SO101 AT83C26 hardware AES SHA-256 SC100 BGA256 AT91SO100
Text: , APACS, ZKA, Common Criteria (EAL4+), FINREAD Memory · 256 bits of Key Storage (battery backup) · , Hardware SHA-1, SHA- 256 True Random Number Generator (RNG) Two CRC 16 Engines and one CRC 32 Engine , ­SMIC­26Oct05 AT91SO100 Figure 1. Block Diagram. Intrusion Switch Sensors 256 bit User Key CP15 (MPU , Timers EEPROM 256 KB ext_nwait DPRAM SCK MOSI MISO NSS SPI USB + USB - USB Device , Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC /ASSP/Smart Cards 1150


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PDF 32-bit -SC100 384-byte 128-byte 6514BS 26Oct05 ARM SC100 ARM RNG AES RSA chips AT91SO101 AT83C26 hardware AES SHA-256 SC100 BGA256 AT91SO100
2005 - TN-29-11

Abstract: Micron NAND CRC-16 SHA-256 09005aef81c06f58 Micron NAND flash memory micron flash otp
Text: system-component serial numbers, such as those of the microprocessor and/or ASIC device, to employ a serial number , component authentication numbers (from the system CPU and/or ASIC , etc.). Read CPU, ASIC , or other , hash algorithm attributes. From the number of security bits provided for each hash algorithm, SHA- 256 , 128 160 256 - - 64 64 80 128 CRC-16 CDC-32 MD-4 MD-5 SHA-1 SHA- 256 Using the


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PDF TN-29-11: 64-bit 09005aef81c06f58 09005aef81c06f44 tn2911 TN-29-11 Micron NAND CRC-16 SHA-256 Micron NAND flash memory micron flash otp
2007 - secure access module

Abstract: AT91SO25 at91so100 AT91SO51 ARM SC100 AES RSA chips AT91SO101 hardware AES 256 controller CRC-16 and CRC-32 ARM SC100 7816
Text: PED, APACS, ZKA, Common Criteria (EAL4+), FINREAD Memory · 256 bits of Key Storage (battery , 128-192-256 Hardware SHA-1, SHA- 256 True Random Number Generator (RNG) Two CRC 16 Engines and one CRC 32 , . Block Diagram (Secure controller) Intrusion Switch Sensors 256 bit User Key CP15 (MPU , Timers EEPROM 256 KB ext_nwait DPRAM SCK MOSI MISO NSS SPI USB + USB - USB Device , Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC


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PDF 32-bit -SC100TM 384-byte 128-byte 6514BS secure access module AT91SO25 at91so100 AT91SO51 ARM SC100 AES RSA chips AT91SO101 hardware AES 256 controller CRC-16 and CRC-32 ARM SC100 7816
2006 - WLAN Module MII

Abstract: e300c3 circuit diagram bluetooth based home automation DDR PHY ASIC SHA-256 mbps asic AES SHA SHA-256 MPC8349E MPC8313E asic graphic
Text: Printer CPU and Interface ASIC . . . . . . . . 2 1.2 High-End Printer I/O Processor . . . . . . . . . . . , . 1.1 Low-End Printer CPU and Interface ASIC Figure 1 illustrates how the MPC8313E can perform the function of the CPU + interface ASIC on a low-end printer application. e300c3 Core PCI Main ASIC Rasterize DDR SDRAM FLASH MPC8313E Compress Decompress HalfToning Interface ASIC Color , Low-End Printer Application In this application, the CPU interfaces to the main ASIC through the


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PDF MPC8313EPB MPC8313E MPC8313E WLAN Module MII e300c3 circuit diagram bluetooth based home automation DDR PHY ASIC SHA-256 mbps asic AES SHA SHA-256 MPC8349E asic graphic
2006 - EMV2000

Abstract: ISO14443 SHA-256 AT90SC AT90SC256144RCFT CRC16 SHA-256 Cryptographic Accelerator
Text: to 256 Bytes Secure Microcontroller for Smart Cards AT90SC 256144RCFT Summary Memory · , 25oC ­ 10 Years Data Retention · 8K Bytes of RAM + 256 Bytes of DMA Dedicated RAM Peripherals · , Generation, AES, MD5, SHA-1, SHA- 256 ) · DMA Controller to Speed-up Data Transfers when communicating via , ) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC /ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado


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PDF FIPS201 EMV2000 6534AS 13Oct06 ISO14443 SHA-256 AT90SC AT90SC256144RCFT CRC16 SHA-256 Cryptographic Accelerator
2006 - AT98SC

Abstract: AT98SC032 At98sc032ct-usB Atmel at98sc AT98SC032CTUSB SHA-256 SHA-256 mbps asic SHA-256 asic AT98SC-EV2
Text: Features General · Strong Challenge-Response Authentication Using Digital Signature · Digital Signature (RSA PKCS#1 V2.1, ECDSA) · Message Authentication Code (3DES MAC, HMAC) · Encryption (3DES, RSA PKCS#1 V2.1) · Message Digest (SHA-1, SHA- 256 ) · Public Key Pair Generation (RSA including CRT, ECC) · HOTP One-Time Password Generation · High Speed Hardware Cryptographic Engines - Hardware 3DES , MPU/ High Speed Converters/RF Datacom ASIC /ASSP/Smart Cards Avenue de Rochepleine BP 123


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PDF SHA-256) 112-bits 32-bit 8-/16-bit 6533AS-SMIC-13Oct06 AT98SC AT98SC032 At98sc032ct-usB Atmel at98sc AT98SC032CTUSB SHA-256 SHA-256 mbps asic SHA-256 asic AT98SC-EV2
2006 - AT98SC008CT

Abstract: AT90SC 3des ATMEL Application Note SOIC SHA-256 AT98SC FIPS140-2 AT90SC Summary 44QFN SHA-256 mbps asic Triple DES embedded
Text: Features General · · · · · · · · · · · · · · · Single Chip Turnkey Solution Strong Challenge-Response Authentication Using Digital Signature Digital Signature (3DES MAC, RSA PKCS#1, ECDSA) Encryption (3DES, RSA PKCS#1) Message Digest (SHA-1, SHA- 256 ) Public Key Pair Generation (RSA including CRT or ECC) High Speed Hardware Cryptographic Engines ­ Hardware 3DES Crypto Accelerator (112 , Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC


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PDF SHA-256) 112-bits 32-bit 8-/16-bit 6526AS 25Jan06 AT98SC008CT AT90SC 3des ATMEL Application Note SOIC SHA-256 AT98SC FIPS140-2 AT90SC Summary 44QFN SHA-256 mbps asic Triple DES embedded
AT98SC016CU

Abstract: AT90SC 3des AT98SC016 AT98SC masters in public administration SHA-256 Cryptographic Accelerator ISO7816 ecdsa digital signature block diagram FIPS140-2
Text: Features General · Single Chip Turnkey Solution · Strong Challenge-Response Authentication Using Digital Signature · Digital Signature (3DES MAC, PKCS#1 RSASSA_PSS and RSASSA_PKCS1_v1_5, · · · · · · · · · · · · · · DSA, EC-DSA, HMAC) Encryption (3DES, PKCS#1 RSAES_OAEP and RSAES_PKCS1_v1_5) Message Digest (SHA-1, SHA- 256 ) Public Key Pair Generation (RSA, RSA-CRT, DSA and EC-DSA , 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 ASIC /ASSP/Secure Products Zone


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PDF SHA-256) 112-bits 32-bit 8-/16-bit AT98SC016CU AT90SC 3des AT98SC016 AT98SC masters in public administration SHA-256 Cryptographic Accelerator ISO7816 ecdsa digital signature block diagram FIPS140-2
2002 - BL8531H

Abstract: d110d
Text: SEC ASIC 2 / 11 STBY CKIN MIXED BL8531H_ADC 12BIT 10MSPS ADC ABSOLUTE MAXIMUM RATINGS , from the same source to avoid power latch-up. SEC ASIC 3 / 11 MIXED BL8531H_ADC 12BIT , otherwise specified) SEC ASIC 4 / 11 MIXED BL8531H_ADC 12BIT 10MSPS ADC I/O CHART Index , ASIC D2 D3 5 / 11 D4 D5 MIXED BL8531H_ADC 12BIT 10MSPS ADC FUNCTIONAL , SHA. SEC ASIC 6 / 11 MIXED BL8531H_ADC 12BIT 10MSPS ADC CORE EVALUATION GUIDE 1


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PDF 12BIT 10MSPS BL8531H 12bit 10MHz 100mW 10MHz. d110d
BW1222L

Abstract: No abstract text available
Text: Output AP : Analog Power AG : Analog Ground SEC ASIC · · · · DP : DG : AB : DB : 2/21 , body model) SEC ASIC 3/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR ANALOG , High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ Max Unit , the input signal is held for data conversion SEC ASIC 5/21 MIXED BW1222L AFE FOR CCD , STRTLN tS SEC ASIC 6/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM


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PDF BW1222L 10-bit 10-bit BW1222L
ASIC R2

Abstract: No abstract text available
Text: Power AG : Analog Ground SEC ASIC - DP DG AB DB : : : : 2 Digital Power , a 1.5k resistor (Human body model) SEC ASIC 3 MIXED AFE16 16-Bit AFE FOR CCD/CIS , µA High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ Max , to when the input signal is held for data conversion SEC ASIC 5 MIXED AFE16 16 , ] R-2 R-2 SEC ASIC G-2 G-2 B-2 B-2 R-1 R-1 6 G-1 G-1 B-1 B-1 R0


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PDF 16-Bit AFE16 16-bit ASIC R2
Not Available

Abstract: No abstract text available
Text: Output AP : Analog Power AG : Analog Ground SEC ASIC - DP DG AB DB : : : : 2 , . 100pF capacitor is discharged through a 1.5k resistor (Human body model) SEC ASIC 3 MIXED , VOL SEC ASIC Typ Max Unit Comment V 0.7 3.0 V V 0.3 4 IoH = 0.5mA , SEC ASIC 5 MIXED AFE_CIP4 12-Bit 20 MSPS AFE FOR CCD/CIS SIGNAL TIMING DIAGRAM 3 , tADCLK ADCCLK tADDT OUTPUT D[7:0] R-2 R-2 SEC ASIC G-2 G-2 B-2 B-2 R-1 R


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PDF 12-Bit 12-bit
2000 - bgr 1

Abstract: ap ag
Text: ASIC 2/11 ANALOG adc1276x 14BIT 10MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics , power latch-up. SEC ASIC 3/11 ANALOG adc1276x 14BIT 10MSPS ADC DC ELECTRICAL , =0V, Toper=25°C, REFTOP=2V, REFBOT=1V unless otherwise specified) SEC ASIC 4/11 ANALOG adc1276x , CKIN DO[13:0] D1 SEC ASIC D2 D3 5/11 D4 D5 ANALOG adc1276x 14BIT , amp is SEC ASIC 6/11 ANALOG adc1276x 14BIT 10MSPS ADC CORE EVALUATION GUIDE 1. ADC


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PDF 14BIT 10MSPS adc1276x adc1276x 14bit 10MHz 48TSSOP 120mW bgr 1 ap ag
2000 - BW1224L

Abstract: cis Linear Image Sensor samsung CMOS image sensor VDDD25
Text: : Analog Output -DO : Analog Output -AP : Analog Power -AG : Analog Ground SEC ASIC -DP -DG -AB , a 1.5k resistor (Human body model) SEC ASIC 3 /20 ANALOG BW1224L AFE FOR CCD/CIS , 10 µA High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ , to when the input signal is held for data conversion SEC ASIC 5 /20 ANALOG BW1224L , SEC ASIC 6 /20 ANALOG BW1224L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIGRAM 1


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PDF BW1224L 12-bit 12-bit BW1224L cis Linear Image Sensor samsung CMOS image sensor VDDD25
2000 - 4-bit flash adc

Abstract: ADC1256 ADC1256X cmos 4093 PIN DIAGRAM
Text: AINC adc1256x DO[11:0] [MSB:LSB] REFTOP1 REFTOP REFBOT REFBOT1 CML SEC ASIC , , VDD25A3) be powered from the same source to avoid power latch-up. SEC ASIC 3/12 ANALOG , specified) SEC ASIC 4/12 ANALOG ADC1256X 12BIT 20MSPS ADC I/O CHART Index AINT Input (V , 1.25 1111 1111 1111 SEC ASIC 5/12 1LSB=0.488mV REFTOP=1.75V REFBOT=0.75V ANALOG , :0] D1 SEC ASIC D2 D3 6/12 D4 D5 ANALOG ADC1256X 12BIT 20MSPS ADC


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PDF 12BIT 20MSPS ADC1256X ADC1256X 12bit 20MHz 48TSSOP 115mW 4-bit flash adc ADC1256 cmos 4093 PIN DIAGRAM
2008 - 8155 block diagram

Abstract: parallel+data+transfer+using+8155+chip
Text: . Compression • LZS • MPPC Encryption • AES (128, 192, 256 ) CBC, ECB, and CTR modes • 3DES/DES , • Wide key AES (128-bit, 192-bit, 256 -bit), including counter mode • RFC 2405 â , (optional) Streaming Bus (or optional PL3 mode) Customer Logic FPGA, ASIC , etc. X-Bus Other


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PDF 8155PP5 576-pin PB-8155-ver6-0608. 8155 block diagram parallel+data+transfer+using+8155+chip
2002 - AT88RF080

Abstract: RFID reader source code AT93C46SC AT90SC3232CS AT90SCS AT88SC1616C AT88SC101 AT88SC0808C AT88SC0404C AT88SC0104C
Text: Authentication and Encryption Now Now AT88SC1616C AT88SC3216C 16 (128 x 8) 16 ( 256 x 8) 2.7V­5.5V , Authentication and Encryption Sept `02 Sept `02 AT88SC25616C 16 (2048 x 8) 2.7V­5.5V 256 Kbit , -bit Zone 1K EEPROM with Password Security, Two 512-bit Zones Now Now AT88SC1003 2 ( 256 x 1) +512 , -Kbit Zones Voltage 2.4V­5.5V Description 2-wire, 256 -bit EEPROM with security for online , AT88SCV002 Organization 256 x 1 Serial Memory Part Number Organization Voltage Serial


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PDF AT88SC0104C AT88SC0204C AT88SC0404C AT88SC0808C AT88SC1616C AT88SC3216C 0233Q-07/02-6M AT88RF080 RFID reader source code AT93C46SC AT90SC3232CS AT90SCS AT88SC1616C AT88SC101 AT88SC0808C AT88SC0404C AT88SC0104C
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