The Datasheet Archive

SDAC-11 datasheet (6)

Part Manufacturer Description Type PDF
SDAC-11-1 ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF
SDAC-11-1-883B ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF
SDAC-11-1-B ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF
SDAC-11-3 ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF
SDAC-11-3-883B ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF
SDAC-11-3-B ILC Data Device 13 BIT HYBRID D/A CONVERTER Very Fast Settling Times: 50 ns Current Output, Scan PDF

SDAC-11 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - MC13783

Abstract: No abstract text available
Text: Freescale Semiconductor Application Note Document Number: AN3261 Rev. 1.1 , 01/2010 MC13783 , . . . . . . . . . . . . 11 CODEC Startup From Full Audio Shutdown NOTE It is assumed that the , X - 39 9 CDCRXSECGAIN1 X - 39 10 CDCSUMGAIN X 39 11 , CDCFS8K16K X - 40 11 CDCEN 1 - 40 12 CDCCLKEN X - 40 13 CDCTS , settings. MC13783 Recommended Audio Output SPI Sequences Application Note, Rev. 1.1 2 Freescale


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PDF AN3261 MC13783
dc to ac converters

Abstract: No abstract text available
Text: -1 0 PARAM ETER R E S O L U T IO N U N IT S Bits 2 6 1 5 -1 0 13 S D A C - 11 261 5-11 13 S D A C -1 2 , max 0 .0 2 5 .0 max 100 ± 0 .0 5 m ax 11 ± 0 .0 1 2 5 max 1 ± 0 .0 2 5 max ±15 ± 25 1 .0 max 0.01 , INPUTS LSB 9 10 11 12 13 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 , accordance w ith require ments o f M IL-STD -883. PIN CONNECTION TA B LE PIN 1 2 3 4 5 6 7 8 9 10 11 12 , 13 (LSB) Bit 12 B it 11 B it 10 B it 9 B it 8 Bit 7 PIN 13 14 15 16 17 18 19 20 21 22 23 24


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PDF oooooooooooo24 IL-STD-202E, C-4/86 dc to ac converters
Y CONAS 12

Abstract: sonar block diagram B-28 DGL-13
Text: -10 SDAC-11 SDAC-12 PARAMETER UNITS 2615-10 2615-11 2615-12 RESOLUTION Bits 13 13 13 ACCURACY (USING , Error % F.S. Range 10.1 max ±0.05 max ±0.025 max Monotonic to Bits 10 11 12 DYNAMIC CHARACTERISTICS , 1 2 3 4 5 6 7 8 9 10 11 12 13 + F.S. - 1 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 + 1/2 F.S. 0 0 1 1 1 1 1 1 , Bit 13 (LSB) 18 Bit 1 (MSB) 7 Bit 12 19 Feedback 2 8 Bit 11 20 Feedback 3 9 Bit 10 21 Feedback 1 10 Bit 9 22 Ref. In 11 Bit 8 23 Ref. Out 12 Bit 7 24 +5 VDC Input B-29 This Material


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PDF MIL-STD-883. MIL-STD-883 MIL-STD-202E, C-4/86 Y CONAS 12 sonar block diagram B-28 DGL-13
MFP10S

Abstract: USP6947325 PB0A
Text: ) ACK No.A1812- 11 /20 LE24CBP222 0 1 S0 0 S2 S1 / W A8 1 0 NO ACK R/W 1 , Shifter TMDS LCD-TV No.A1812-18/20 LE24CBP222 11 ) HDMI Receiver VDD(3V)*1 DDC+5V *3


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PDF LE24CBP222 Bank22Kbit 128bit 4224bit 400kHz A1812-1/20 USP6947325) LE24CBP222M MFP10S USP6947325 PB0A
2012 - HDMI connect

Abstract: No abstract text available
Text: Configuration HPD_H CEC_H HPD_C VCCA 12 1 2 3 11 10 9 8 7 SCL_H SDA_H CEC_C SCL_C 4 GND , 8 9 10 11 12 Signal Name SCL_H SDA_H OE GND VCCC SDA_C SCL_C CEC_C HPD_C HPD_H VCCA CEC_H OE , FXMHD103 - HDMI Voltage Translator Timing Diagrams(10, 11 ,12,13,14) DATA IN tpxx DATA OUT Vmi tpxx Vmo , ) or (tpLHmax ­ tpLHmin) Figure 11 . F-Toggle Rate Figure 12. Output Skew Time Notes: 10 , 5.5 only. 11 . VCCI=VCCA for control pin OE or Vmi=(VCCA / 2). 12. DDC Rise Times 30% - 70%, CEC & HPD


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PDF FXMHD103 JESD22-A114) JESD22-C101) FXMHD103 HDMI connect
HT46

Abstract: extern near HA0005E HT24 HT24LC02 HT48R30A-1
Text: ;-; file name op_ht24.asm ; date 2003/ 11 /18 ; MCU: HT48R30A-1 ; EEPROM: HT24LC02 ; Fsys: 1MHz , HT24.INC ; date 2003/ 11 /18 ;- , ht24.asm ; date 2003/ 11 /18 ; ROM status 94H ; RAM status 16H


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PDF A0005E HT24LC02 HT46 extern near HA0005E HT24 HT48R30A-1
HT24

Abstract: HT24LC02 HT24LC04 HT24LC08 HT24LC16 HT48R30A-1 t6100a wack
Text: No file text available


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PDF T6100AH 1000kHz 24SKDIP ht48r30a-1 40CL42TH HT24 HT24LC02 HT24LC04 HT24LC08 HT24LC16 t6100a wack
HT48R30A-1

Abstract: CMAC HT24 HT24LC02 HT46
Text: ;-; op_ht24.asm ; 2003/ 11 /18 ; MCU: HT48R30A-1 ; EEPROM: HT24LC02 ; Fsys: 1MHz , .42TH ;-; HT24.INC ; 2003/ 11 /18 ;- , MSA.42TH ;-; ht24.asm ; 2003/ 11 /18


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PDF 20CL42TH tibK220CL42TH T5000AH HT48R30A-1 HT24LC02 HT48R30A-1 CMAC HT24 HT24LC02 HT46
2012 - Not Available

Abstract: No abstract text available
Text: 12 11 10 9 1 SCL_H 4 5 GND VCCC SCL_C 6 SDA_C 3 CEC_C 7 , source) when there is an HDMI sink connected to the FXMHD103. 11 VCCA 12 CEC_H © 2012 , GND tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 11 . F-Toggle Rate Figure , ; Input tR=tF=2.5ns, 10% to 90%, at VIN=4.5V to 5.5 only. 11 . VCCI=VCCA for control pin OE or Vmi=(VCCA , www.fairchildsemi.com 11 FXMHD103 — HDMI Voltage Translator Timing Diagrams(10, 11 ,12,13,14) Power Down


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PDF FXMHD103 JESD22-A114) JESD22-C101)
2011 - IES5502TR

Abstract: IES5502 IES5502T BC857BS IES5502D DTC124E IES5501 UM10204 IES5502TR hendon
Text: µs tRDYHL READY Low to VSxxx-x off - 1.1 µs Note 1. Guaranteed by design (not , Packaging and Soldering Information" on the Hendon Semiconductors web site. 11 ESD CAUTION Electrostatic , Product Specification 1.1 20080421 Pre-charge condition update 1.2 20080513 Fix , for any damages resulting from such improper use or sale. 2011 Jan 14, Revision 1.5 11


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PDF IES5502 IES5502 IES5501 IES5502TR IES5502T BC857BS IES5502D DTC124E UM10204 IES5502TR hendon
pb0a

Abstract: A1811 1011100B USP6947325 VESA Serial eeprom
Text: No.A1811- 11 /20 LE24CBK222 0 1 S0 0 S2 S1 / W A8 1 0 NO ACK R/W 1 S0 0 S2 S1


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PDF LE24CBK222 Bank22Kbit 128bit 4224bit 400kHz A1811-1/20 USP6947325) LE24CBK222M 225mil) pb0a A1811 1011100B USP6947325 VESA Serial eeprom
1998 - Not Available

Abstract: No abstract text available
Text: Bias Sink Current 1.028 1.1 1.87 V 200 RS in series with CL, CL = 1nF, 200Ω ≤ RS â , output of 6-bit DAC. Controls negative gate bias voltage of external power amplifier. 11 SDG , ) KDAC value [6:0]; LSB is bit 0, binary. Power class: 00 = Class 1 01 = Class 2 10 = Class 3 11 = , 10 Receive mode, SDAC and GDAC outputs disabled 11 Standby: REF, GDAC, and XDAC enabled , . 11 M AX 1 0 0 7 Table 2. Power Modes Pin Configura t ion Chip I nform a t ion


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PDF MAX1007 24-pin
1998 - MAX1007

Abstract: MAX1007CAG MAX1007EAG MAX840 KDAC transistor sdg
Text: 1.028 1.1 1.87 V 200 RS in series with CL, CL = 1nF, 200 RS 1k Internal DAC Reference , negative gate bias voltage of external power amplifier. 11 SDG Software-Programmable Logic Output , ) KDAC value [6:0]; LSB is bit 0, binary. Power class: 00 = Class 1 01 = Class 2 10 = Class 3 11 = , Receive mode, SDAC and GDAC outputs disabled 11 Standby: REF, GDAC, and XDAC enabled. Rest of IC is , . 11 MAX1007 Table 2. Power Modes Pin Configuration Chip Information TRANSISTOR


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PDF PWT1900 MAX1007 MAX1007 MAX1007CAG MAX1007EAG MAX840 KDAC transistor sdg
2008 - IES5502T

Abstract: IES5502D BC857BS DTC124E IES5501 UM10204 IES5502
Text: µs tRDYHL READY Low to VSxxx-x off - 1.1 µs Note 1. Guaranteed by design (not , "Integrated Circuit Packaging and Soldering Information" on the Hendon Semiconductors web site. 11 ESD , 20080320 Product Specification 1.1 20080421 Pre-charge condition update 1.2 20080513 , . 2008 Jul 24, Revision 1.4 11 Product Specification Hendon Semiconductors


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PDF IES5502 IES5502 IES5501 IES5502T IES5502D BC857BS DTC124E UM10204
SDA 1024

Abstract: HT48R30A-1 HA0016E HT24 HT24LC02 HT24LC04 HT24LC08 HT24LC16 EEPROM Capacity
Text: No file text available


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PDF A0016E HT24LC04 SDA 1024 HT48R30A-1 HA0016E HT24 HT24LC02 HT24LC04 HT24LC08 HT24LC16 EEPROM Capacity
2009 - esaki Diode

Abstract: TUNNEL DIODE detail of half adder ic SCHINDLER MC1650 AM687 AD9235 tunnel diode GaAs MT-021 12bit ADC BiCMOS
Text: output data are shown in Figure 11 for the AD9235 12-bit 65-MSPS ADC where there is a 7-clock cycle pipeline delay. PIPELINE DELAY (LATENCY) = 7 CLOCK CYCLES Figure 11 : Typical Pipelined ADC Timing for , ) which dissipate 700 mW and 600 mW, respetively. Page 11 of 14 MT-024 PIPELINED ADCs FOR


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PDF MT-024 MT-020) 1980s 1990s, esaki Diode TUNNEL DIODE detail of half adder ic SCHINDLER MC1650 AM687 AD9235 tunnel diode GaAs MT-021 12bit ADC BiCMOS
1998 - 1152MHz

Abstract: transistor sdg
Text: , CL = 1nF, 200 RS 1k RS in series with CL, CL = 1nF, 200 RS 1k 200 2.42 0.96 1.028 1.87 1.1 V V µA , input. 2 FPS2 3 4 5 6 7 8 9 10 11 12 FPS1 SDAC AVDD XDAC AGND REF KDAC GDAC SDG BANT 13 , . Power class: 00 = Class 1 01 = Class 2 10 = Class 3 11 = Class 4 GDAC value [5:0]; LSB is bit 0, binary , shut down. PSDWDW 11 VALID BANT OLD DATA Figure 4c. Power-Sense/Best-Antenna Detailed , . 11 Mobile-Radio Analog Controller MAX1007 Pin Configuration TOP VIEW RPS 1 FPS2 2 FPS1 3


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PDF MAX1007 MAX1007 1152MHz transistor sdg
1997 - KDAC

Abstract: MAX1007 MAX1007CAG MAX1007EAG gaas amplifier
Text: SDG 11 14 PSDWDW BANT 12 13 PSDCTRL SSOP 2


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PDF MAX1007 MAX1007 KDAC MAX1007CAG MAX1007EAG gaas amplifier
2011 - Not Available

Abstract: No abstract text available
Text: Min 2.7 0.41VCC 6 1.2 1 0 Typ 9 520 2.2 0.92 11 0.5VCC 0.5VCC 10 165 55 60 30 15 400 Max 5.5 10 , VCC = 3.3 V Vbus = VI(EN) = VCC = 5.5 V Min 50 50 Typ 95 75 95 1.1 1 0.5 Max 150 120 Unit s s s s s s , R4 3.9 k R5 1.1 k R6 1.1 k VCC SCL SDA SCLC VCC SCLB SDAB SCLB SDAB RDY , bidirectional bus buffer with hot insertion logic backplane PERIPHERAL CARD 1 (3.3 V) R3 1.1 k R4 1.1 k R7 , + - 11 R (1) This calculation is valid for VSxxx(in) 200 mV, as below this point


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PDF PCA9522 PCA9522 IES5502,
Not Available

Abstract: No abstract text available
Text: ±15 ±25 2.0 max 0.04 10.0 max 200 ±0.1 max 10 SDAC-11 2615-11 13 ±0.02? max 2 ±0.05 max ±15 125 1.0 max 0.02 5.0 max 100 ±0.05 max 11 SO AC-12 - - ILC DATA D EVICE CORPORATION 2 uQ , 0 1 1 3 0 1 1 1 0 1 1 1 D IG IT A L B IT IN P U T S LSB 9 10 11 12 13 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 , IL-ST D -883. PIN C O N N E C T IO N T A B L E PIN 1 2 3 4 5 6 7 8 9 10 11 12 F U N C T IO N +15 V , (LSB) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 PIN 13 14 15 16 17 18 19 20 21 22 23 24 F U N C T IO


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PDF 00D3T AND2615 MIL-STD-202E, C-4/86
2012 - schematic diagram hdmi to rca

Abstract: No abstract text available
Text: HPD_B à à 64 pin LQFP (FB), Pb-free and Green 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 , resistor. 11 /OE I Output Enable control. Active low. /OE only disables the high speed TMDS , SPDIF_IN I Single mode ARC signal input. See page 11 in detail. 17 ARC_OUT O Single mode , b[7:6] = 11 no port active See Port Selection truth table 0 = Output Disable 5 TMDS Output , lock 12-0237 11 www.pericom.com 07/28/2012 PI3HDMI336 3:1 ActiveEye™ HDMI™ Switch


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PDF PI3HDMI336 PI3HDMI336 JP212: JP213: JP214: schematic diagram hdmi to rca
Not Available

Abstract: No abstract text available
Text: AM component detection sensitivity set lì S300Q 11 T.C.adjl HCC/SNC tim e constant set , , and Q detector block 11 NEC b42752S 0 0 4 tJSD3 3 7 T N E C E uPC2535 2.2 STATION , constants are determined by the capacitance o f capacitor C16 connected between pin 11 and GND and , to pin 10. Control pin 11 is com m only used to control HCC and SNC functions w ith reference to the , of pin 36) (Level of pin 36) No signal V i» 60 dB^V V. - 100 dB/iV RSD · 11 kQ RAFC - 56 kQ 28 50


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PDF b427S25 uPC2535 /JPC2535 fiPC2535 WS-60-00-1 IR-30-00-1
P14SF

Abstract: 78C354 P24SF
Text: D P A A 4 P 4 V P 3 f SDAC10 10 I - SDAC11 L_ 11 P2.6, SDAC12 P 12 P2.7, SDAC13 È OSCOUT , .7, SDAC13 OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 W78C/E354 (DIP40 , 21 c c c c c c c c c 3 3 C 9 C 10 c 11 c 12 c 13 3 3 3 3 3 3 3 3 3 3 3 VDD SDAC4 , SDAC8 SDAC9 7 10 SDAC10 11 SDAC11 SDAC12 19 20 SDAC13 BSDACO 29 BSDAC1 30 VDD 68 16 Vss BDDAC 59 DDACO , .5 (SOA) 51 36 ADCO DIP-40 - DIP-48 27 25 11 12 13 14 4 5 6 7 22 23 29 43 15 16 30 - PLCC-68 PIN


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PDF W78C354/W78E354 W78C354 80C32 12-bit W78E354) P14SF 78C354 P24SF
2012 - PI3HDMI1421

Abstract: TQFN42 PI3HDMI1421ZHE HPDX 40
Text: 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CD4+ CD4GND SCLC SDAC HPDC DNC BD1+ BD1VDD BD2+ BD2 , SDA_A HPD_A SW OE# mux_demux_en HPDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 GND 38 37 36 , property of their respective owners. 11 www.pericom.com P-0.107/20/12 HDMITM Revision 1.4 , area 09-0091 DATE: 02/ 11 /09 DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE


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PDF 48pin 48-contact PI3HDMI1421 PI3HDMI1421 42-contact PD-2035 PI3HDMI1421ZBE PI3HDMI1421ZHE 48-pin, TQFN42 PI3HDMI1421ZHE HPDX 40
ax1007 12

Abstract: transistor sdg KDAC
Text: 1.1 V V HA V Digital Inputs (CS, SCLK, DIN, PKWDW, ADCCTRL, PSDWDW, PSDCTRL) Input Voltage High , input. 2 FPS2 3 4 5 6 7 8 9 10 11 12 FPS1 SDAC AV dd XDAC AGND REF KDAC GDAC SDG BANT 13 , 3 11 = Class 4 GDAC value [5:0]; LSB is bit 0, binary. Reserved Reserved Reserved ADC value [7:0 , Controller Table 2. Power Modes RxEN. TxEN 00 01 10 11 Total shutdown Transmit mode, all DACs enabled , only when the device is performing the transmit power-sense measurement. A M X IV M 11


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PDF AX1007 ax1007 12 transistor sdg KDAC
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