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CSD15571Q2 Texas Instruments 20-V N-Channel NexFET™ Power MOSFET 6-WSON -55 to 150
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CSD15380F3T Texas Instruments 20-V N-Channel FemtoFET MOSFET 3-PICOSTAR -55 to 150
TMP6131LPG Texas Instruments Silicon-based linear thermistor with a Positive Temperature Coefficient (PTC) 2-TO-92 -65 to 150
INA330AIDGSR Texas Instruments Thermistor Signal Amplifier for Temperature Control 10-VSSOP -40 to 85
INA330AIDGSRG4 Texas Instruments Thermistor Signal Amplifier for Temperature Control 10-VSSOP -40 to 85

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panasonic lcd tft panel

Abstract: 386SX MN89303A QFH128-P-1818
Text: -SD4 -SD5 -Vss -SD6 -SD7 -SD8 -vDD -SD9 -SD 10 -SDII -Vss -SD 12 -SD 13 -SD14 - SD15 -vDD , voltage 1 TEST ,AEN ,SBHE, IOWR ,IORD ,SMEMW, SMEMR .REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY Vili 0 0.8 V "L" level , voltage 1 BACKON ,LCDON, LOGICON , SD15 to 0, MD15 to 0 ,BIOSEN Vom Io=-2.0mA V,=VDD or Vss VDD-0.6 V , output voltage 2 SD15 to 0 ,MD15 to 0 , BIOSEN VQL2 Io=4.0mA V,=VDD or Vss 0.4 V "L" level output


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PDF MN89303A MN89303A 16-monochrome 16-ipment QFH128-P-1818 0D1S414 panasonic lcd tft panel 386SX QFH128-P-1818
1998 - EMP7096

Abstract: hard drive spindle motors diagram Hitachi HC14 HA13614FH 607034B H01PW Nippon capacitors Hitachi DSAUTAZ006 hitachi ha17903 IC7HC14
Text: interface signals. It detects the high/low levels of the SD15 to SD0 operating mode setup switches and , Operation mode 16 setting switches SD15 to SD0 VCM PWM generator SCI control VIPWMH VIPWML SCLK Data , 14 13 12 MR2 10k SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 RESET , EPM7096LC68 6,16,26,34, 38,48,58,66 SD14 VIPWML VIPWMX 18 29 VIPWML VPL VIPWML SD15 VCM , H L SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 H L CLKSEL VMODE VD15


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PDF HA13614FH ADE-607-034B 16-bit EMP7096 hard drive spindle motors diagram Hitachi HC14 607034B H01PW Nippon capacitors Hitachi DSAUTAZ006 hitachi ha17903 IC7HC14
2014 - Not Available

Abstract: No abstract text available
Text: Purpose ESD Protection - SD Series SD15 Electrical Characteristics (TOP=25ºC) Parameter Symbol , Pulse Power - P pk (kW) 140 1 0.1 120 SD05 100 80 60 SD12 40 SD15 20 , Series SD15 Transmission Line Pulsing(TLP) Plot SD24 Transmission Line Pulsing(TLP) Plot 20 , 0.0004 inches (0.102mm) SD12-01FTG SOD323 g1 3000 Substrate material Silicon SD15 , : SD05-01FTG 1: SD12-01FTG 2: SD15 -01FTG 3: SD24-01FTG 4: SD36-01FTG Package F: SOD323 Package


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PDF IEC61000-4-5) IEC61000-4-2, OD323
1997 - i386DX

Abstract: i386SX diode r639 i386 Engine SA11 SA10 MN89302 MD14 MD11 MD10
Text: REFRESH MEMR GND IOCS16 MEMCS16 VDD SA1 MEMW IOCHRDY IOWR IORD BIOSEN AEN SBHE GND SD15 , ,IOWR ,IORD , SMEMW ,SMEMR , REFRESH ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "L" level input voltage 2 TEST ,MINTEST , VSS BACKON ,LCDON , LOGICON , SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 V OH2 , "L" level output voltage 2 VOL2 IO =4.0mA VI =VDD or VSS SD15 to 0 ,MA9 to 0 ,RAS , UCAS


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PDF MN89302 MN89302 IOCS16 MEMCS16 QFH128-P-1818 i386DX i386SX diode r639 i386 Engine SA11 SA10 MD14 MD11 MD10
1997 - TFT LCD display circuit diagram of 30 pin out

Abstract: 386SX 386DX MN89303A SD10 MD10 MD11 MD14
Text: SD15 VDD VSS For Information Equipment MN89303A Block Diagram Gray scale engine RAM , , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "H" level input voltage 2 MINTEST , , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY , , LOGICON , SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 VOH2 IO=­8.0mA VI=V DD or VSS , output voltage 2 V OL2 IO=4.0mA VI=V DD or VSS SD15 to 0 ,MD15 to 0 , BIOSEN "L" level output


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PDF MN89303A MN89303A 16-monochrom9303A IOCS16 MEMCS16 QFH128-P-1818 TFT LCD display circuit diagram of 30 pin out 386SX 386DX SD10 MD10 MD11 MD14
LD4AJ

Abstract: panasonic 32 lcd diagram ic i386SX i386DX TFT LCD display circuit diagram of 30 pin out MN89302 QFP128-P-1818
Text: ,IOW R ,IORD , SM EM W ,S M E M R , REFRESH ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "L" level input voltage 2 TEST ,M IN T , Parameter Pull-down resistance "H" level output voltage 1 BACKON ,L C D O N , LOG ICON , SD15 to 0 , MD15 to , voltage 2 SD15 to 0 ,MA9 to 0 ,RAS , UCAS ,LCAS ,W E ,BIOSEN "L" level output voltage 3 DCLK ,DISP ,LP ,FP , Output leakage current IOCS 16 .BACKON , MA9 to 0 ,M EM CS16 , UCAS ,LCAS ,RAS , LOGICON ,LCDON , SD15 to


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PDF MN89302 MN89302 bR32fl52 QFH128-P-1818 LD4AJ panasonic 32 lcd diagram ic i386SX i386DX TFT LCD display circuit diagram of 30 pin out QFP128-P-1818
1997 - i386SX

Abstract: MD10 MD11 MD14 MN89302 SA10 SA11 i386DX
Text: MEMR GND IOCS16 MEMCS16 VDD SA1 MEMW IOCHRDY IOWR IORD BIOSEN AEN SBHE GND SD15 SD14 , ,IOWR ,IORD , SMEMW ,SMEMR , REFRESH ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "L" level input voltage 2 TEST ,MINTEST , VSS BACKON ,LCDON , LOGICON , SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 V OH2 , "L" level output voltage 2 VOL2 IO =4.0mA VI =VDD or VSS SD15 to 0 ,MA9 to 0 ,RAS , UCAS


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PDF MN89302 MN89302 i386SX MD10 MD11 MD14 SA10 SA11 i386DX
2001 - CXD2460

Abstract: DAC01 DAC02 SD15 VSP1221 ic 501
Text: ). The format is as follows: DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required , cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format section). , -bit blocks can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS CXD2460 DAC01 DAC02 SD15 ic 501
2001 - Not Available

Abstract: No abstract text available
Text: : DATA_REQUEST on SDIN SD15 1 SD14-SD10 Required register address SD9-SD0 Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be 1 for register , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB RD/WR (1) SD14 A4 SD13 A3 SD12 A2 SD11 A1 SD10 A0 , SLES012A ­ SEPTEMBER 2001 ­ REVISED JULY 2004 Control Register SD15 MSB RD/W R SD14 0 SD1 3 0 SD12 0 , unchanged. See the CCD input section. Programmable-Gain Amplifier (PGA) Register SD15 MSB RD/WR SD14 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, 75-dB 48-Pin
2001 - DAC01

Abstract: DAC02 SD15 VSP1221
Text: ). The format is as follows: DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required , cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format section). , -bit blocks can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS DAC01 DAC02 SD15
2001 - CXD2460

Abstract: No abstract text available
Text: : DATA_REQUEST on SDIN SD15 1 SD14-SD10 Required register address SD9-SD0 Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be 1 for register , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB RD/WR (1) SD14 A4 SD13 A3 SD12 A2 SD11 A1 SD10 A0 , SLES012A ­ SEPTEMBER 2001 ­ REVISED JULY 2004 Control Register SD15 MSB RD/W R SD14 0 SD1 3 0 SD12 0 , unchanged. See the CCD input section. Programmable-Gain Amplifier (PGA) Register SD15 MSB RD/WR SD14 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, 75-dB 48-Pin CXD2460
1997 - on semiconductor r640

Abstract: MN89303A 386DX MD10 MD11 MD14 SD10 386DX bios
Text: SD5 VSS SD6 SD7 SD8 VDD SD9 SD10 SD11 VSS SD12 SD13 SD14 SD15 VDD VSS For , 0.3 V TEST ,AEN ,SBHE , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to , ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "L" level input voltage 2 , VDD­ 0.6 V VDD­ 0.6 V VI=V DD or VSS BACKON ,LCDON , LOGICON , SD15 to 0 , MD15 to 0 , =4.0mA VI=V DD or VSS SD15 to 0 ,MD15 to 0 , BIOSEN "L" level output voltage 3 V OL3 IO=0.8mA VI=V


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PDF MN89303A MN89303A on semiconductor r640 386DX MD10 MD11 MD14 SD10 386DX bios
schematic lcd inverter samsung

Abstract: samsung lcd inverter schematic LCD display 20X2 3.3v lcd cross reference HVL3224QE 25X2 lcd display LCD display 20X2 3v GPS LED DOT lcd inverter board schematic schematic Samsung lcd power supply unit
Text: SD15 SA5 68 SD14 62 69 SD13 SA4 70 SD12 SA3 71 SD11 64 72 SD10 63 , EXT. SRAM LVDD 66 VDD 3.3V SD15 67 BID EXT. SRAM SD14 68 BID EXT , VCCIO 17 ADD3 42 CE 67 SD15 92 XD7 18 ADD2 43 OE 68 SD14 93 , SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 7 8 9 10 13 14 15 16 CLOCK GND GND , GREEN D1 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 FR FM LP XCLK OFF SD15 SD14 SD13 SD12


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PDF HVL3224QE May/30//2003 HYVIX-MAIN-R003, 320-by-240 16-bit HVL3224QE HVL3224QE) schematic lcd inverter samsung samsung lcd inverter schematic LCD display 20X2 3.3v lcd cross reference 25X2 lcd display LCD display 20X2 3v GPS LED DOT lcd inverter board schematic schematic Samsung lcd power supply unit
2001 - DAC01

Abstract: DAC02 SD15 VSP1221 SLES012A SD701
Text: ). The format is as follows: DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required , cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format section). , -bit blocks can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS DAC01 DAC02 SD15 SLES012A SD701
2001 - ICX205

Abstract: DAC01 DAC02 SD15 VSP1221
Text: ). The format is as follows: DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required , cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format section). , -bit blocks can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS ICX205 DAC01 DAC02 SD15
2001 - CXD2460

Abstract: VSP1221
Text: : DATA_REQUEST on SDIN SD15 1 SD14-SD10 Required register address SD9-SD0 Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be 1 for register , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB RD/WR (1) SD14 A4 SD13 A3 SD12 A2 SD11 A1 SD10 A0 , SLES012A ­ SEPTEMBER 2001 ­ REVISED JULY 2004 Control Register SD15 MSB RD/W R SD14 0 SD1 3 0 SD12 0 , unchanged. See the CCD input section. Programmable-Gain Amplifier (PGA) Register SD15 MSB RD/WR SD14 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, 75-dB 48-Pin CXD2460 VSP1221
2001 - ICX205

Abstract: DAC01 DAC02 SD10 SD13 SD14 SD15 VSP1221
Text: (pin 47). The format is as follows: DATA_REQUEST on SDIN SD15 SD14­SD10 SD9­SD0 1 , don't cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 RD/WR A4 SD13 SD12 SD11 , 2001 control register SD15 MSB SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 , unchanged. See the CCD input section programmable-gain amplifier (PGA) register SD15 MSB RD/WR


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PDF VSP1221 12BIT, 21MSPS, SLES012 12-Bit, 21-MSPS, 75-dB 48-Pin VSP1221 ICX205 DAC01 DAC02 SD10 SD13 SD14 SD15
1999 - TA2025

Abstract: TA17- 04 sa2025 diode td15 IC a210 E0C37120 SD015 TA12 TA10 E0C37109
Text: TD9 TD8 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA25 SA24 SA23 Vss SVcc SA4 SA5 SA6 , SD15 ­0 TD15­0 Data bus E0C37109 ADATAENA# RD/WR# AADRENA# DEN# DDIR AEN# TEST ACE1 , ­0 Address bus E0C37120 Data bus SD15 ­0 TD15­0 ISA 5V IC Data bus DEN# DDIR AEN# TEST


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PDF PF1046-01 E0C37120 E0C37120 E0C37109 32-bit 26-bit 16-bit TA2025 TA17- 04 sa2025 diode td15 IC a210 SD015 TA12 TA10 E0C37109
1997 - i386

Abstract: No abstract text available
Text: SD14 SD15 VDD VSS For Information Equipment Block Diagram MN89303A Gray scale engine RAM , ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "H" , ,SA19 to 0 , BIOSEN ,IOCHRDY ce /D isc on tin ue SD15 to 0 ,MD15 to 0 , "L" level input , voltage 1 BACKON ,LCDON , LOGICON , SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 UD7 to 0 ,LD7 , SD15 to 0 ,MD15 to 0 , BIOSEN V OL2 IO=4.0mA VI=V DD or VSS "L" level output voltage 3 DCLK ,DISP ,LP


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PDF MN89303A MN89303A 16-monochrome 16-gradation i386
2001 - Not Available

Abstract: No abstract text available
Text: : DATA_REQUEST on SDIN SD15 1 SD14-SD10 Required register address SD9-SD0 Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be 1 for register , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB RD/WR (1) SD14 A4 SD13 A3 SD12 A2 SD11 A1 SD10 A0 , SLES012A ­ SEPTEMBER 2001 ­ REVISED JULY 2004 Control Register SD15 MSB RD/W R SD14 0 SD1 3 0 SD12 0 , unchanged. See the CCD input section. Programmable-Gain Amplifier (PGA) Register SD15 MSB RD/WR SD14 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, 75-dB 48-Pin
2001 - SD15

Abstract: VSP1221 DAC01 DAC02 31AI
Text: ). The format is as follows: DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required , cares. Also, note that SD15 (RD/WR) should be 1 for register read (see the serial data format section). , -bit blocks can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS SD15 DAC01 DAC02 31AI
Not Available

Abstract: No abstract text available
Text: V AEN ,SBHE ,IOWR ,IORD , SMEMW ,SM EM R, REFRESH ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to , ,SM EM R, REFRESH ,A21 to 20 , SA19 to 0 , SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "L" level input , ,LC D O N , LOGICON , SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 VOH2 Io , 0 "L” level output voltage 2 VOI.2 Io=4.0mA V[=VDD or Vss SD15 to 0 ,MA9 to 0 ,RAS , , V0=VDD or V js UCAS ,LCAS ,RAS , LOGICON ,LC D O N , SD15 to 0 ,MD15 to 0 , BIOSEN .IOCHRDY 320


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PDF MN89302 MN89302 MEMCS16 QFH128-P-1818
2001 - Not Available

Abstract: No abstract text available
Text: : DATA_REQUEST on SDIN SD15 1 SD14-SD10 Required register address SD9-SD0 Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be 1 for register , pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB RD/WR (1) SD14 A4 SD13 A3 SD12 A2 SD11 A1 SD10 A0 , SLES012A ­ SEPTEMBER 2001 ­ REVISED JULY 2004 Control Register SD15 MSB RD/W R SD14 0 SD1 3 0 SD12 0 , unchanged. See the CCD input section. Programmable-Gain Amplifier (PGA) Register SD15 MSB RD/WR SD14 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, 75-dB 48-Pin
2001 - Not Available

Abstract: No abstract text available
Text: SDIN SD15 SD14-SD10 SD9-SD0 1 Required register address Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR) should be , can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , Control Register SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD , Amplifier (PGA) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS
2001 - Not Available

Abstract: No abstract text available
Text: : DATA_REQUEST on SDIN SD15 SD14-SD10 SD9-SD0 1 Required register address Don't Care Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR , can be send through the SDIN pin (pin 47) keeping SLOAD (pin 46) low. SD15 MSB SD14 SD13 , SD15 MSB SD14 SD1 3 SD12 SD1 1 SD10 SD9 SD8 SD7 SD6 RD/W R 0 0 , ) Register SD15 MSB SD14 SD13 RD/WR 0 0 SD12 SD11 SD10 SD9 0 0 1 SD8


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PDF VSP1221 SLES012A 12-BIT, 21-MSPS, VSP1221 a12-bit, 21-MSPS
Supplyframe Tracking Pixel