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1601037-2 TE Connectivity (1601037-2) 131-083-010=TAB,059X032,STDSMZ

SCK 083 Datasheets Context Search

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2000 - SCK 083

Abstract: TH sck 083
Text: View HOLD 1 8 VCC S1 2 7 3 6 4 5 SO .159 in. CS VSS WP SCK . 083 in. NOTE: ALL DIMENSIONS IN µM (to , 256 SO SI SCK CS HOLD Command Decode and Control Logic 64 64 X 256 128 128 X 256 WP Write Control and , three-wire bus. The bus signals are a clock input ( SCK ) plus separate data in (SI) and data out (SO) lines , the serial clock. Serial Clock ( SCK ) SCK WP VSS Serial Clock Input Write Protect Input , HOLD SCK SI When CS is HIGH, the X25650 is deselected and the SO output pin is at high impedance and


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PDF X5643 X25650 --14-lead SCK 083 TH sck 083
2012 - TQFP-64-EP

Abstract: SCK 083 J-STD-20D
Text: Configuration Rev. 0.83 iW7032 Product Brief February, 2012 LED15 MISO AVSS VIN SCK , Direct & Segment-Edge LED Backlit LCDTV LCD Public Information Displays Rev. 0.83 iW7032 Product , LED08 - LED15 EPGND SCK MOSI MISO CSB GND2 FB2 LED16-LED23 EPGND XO SYNCLK EPGND Type Ground Ground , . SCK , serial clock input for Serial Peripheral Interface (SPI). Logic high is defined as 3.3V. Master , . Exposed bottom pad used as the high current LED return current path. Rev. 0.83 iW7032 Product Brief


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PDF iW7032 32-Channel iW7032 TQFP-64-EP SCK 083 J-STD-20D
1995 - TH sck 083

Abstract: sck 083 DSP56156 E400 WS-063 WT137
Text: - - - 1.414 0.707 354 100 Vp Vp mVp mVp G - 0.83 G G + 0.83 dB VREF , k Resistance BIAS - 10 (See Note 4) - k VC - 0.83 VC VC + 0.83 dB , or 17 dB (± 0.83 dB variation due to 10% variation on VCC): Allowable Single-ended Load , Control Variation VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB (± 0.83 dB variation due to 10 , that only one frame sync FS is used) bl = bit length wl = word length T SCK FST (Transmit Frame


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PDF DSP56156 TH sck 083 sck 083 E400 WS-063 WT137
2009 - sck 083

Abstract: thermistor SCK 103 NTC THERMISTORS SCK 055 sck 084 sck 2r56 sck 103 thermistor NTC SCK 055 SCK 2r58 SCK 1R37 SCK 206
Text: SCK NTC Power Thermistors Series MERITEK Inrush Current Limiters UL E223037 , coating material: available silicone PART NUMBERING SYSTEM SCK Meritek Series Element Size (Diameter , 0.02 7.5 ± 1 8 rev.6a Specifications are subject to change without notice. SCK NTC Power Thermistors Series MERITEK SPECIFICATIONS SCK 05 Part No Zero Power Resistance at , SCK 08 Part No Zero Power Resistance at 25oC ( ) SCK08-042 SCK08-04R72 SCK08-053 SCK08


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PDF E223037 SCK30-1R0 SCK30-2R5 SCK30-3R0 SCK30-4R0 SCK30-4R7 SCK30-5R0 SCK30-6R8 SCK30-7R0 SCK30-8R0 sck 083 thermistor SCK 103 NTC THERMISTORS SCK 055 sck 084 sck 2r56 sck 103 thermistor NTC SCK 055 SCK 2r58 SCK 1R37 SCK 206
2009 - THERMISTORS SCK 055

Abstract: SCK 2r58 sck 2r56 sck-0510 THERMISTORS SCK 053 sck 084 sck202r5 NTC SCK 055 SCK20100 sck 104 NTC
Text: NTC Power Thermistors Inrush Current Limiters SCK Series MERITEK UL E223037 FEATURES , coating material: available silicone PART NUMBERING SYSTEM SCK Meritek Series Element Size (Diameter , Power Thermistors SCK Series MERITEK SPECIFICATIONS x SCK 05 Part No SCK05-052 SCK05 , Constant Temperature ( Sec. ) (o C ) 15 17 -40~+150 x SCK 08 Part No SCK08-042 SCK08 , . ) (o C ) 2.3 16 38 -40~+170 x SCK 10 Part No SCK10-015 SCK10-1R35 SCK10-1R55 SCK10


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PDF E223037 SCK30-1R0 SCK30-1R5 SCK30-2R0 SCK30-2R5 SCK30-3R0 SCK30-4R0 SCK30-4R7 SCK30-5R0 SCK30-6R8 THERMISTORS SCK 055 SCK 2r58 sck 2r56 sck-0510 THERMISTORS SCK 053 sck 084 sck202r5 NTC SCK 055 SCK20100 sck 104 NTC
2007 - NTC SCK 055

Abstract: THERMISTORS SCK 055 sck-0510 THERMISTORS SCK 053 THERMISTORS SCK 085 SCK-206 sck 104 NTC THERMISTORS SCK 054 ntc 8r0 sck 2r56
Text: NTC Power Thermistors Inrush Current Limiters SCK Series MERITEK UL E223037 FEATURES , coating material: available silicone PART NUMBERING SYSTEM SCK Meritek Series Element Size (Diameter , NTC Power Thermistors SCK Series MERITEK SPECIFICATIONS · SCK 05 Part No SCK05-052 SCK05 , Constant Temperature ( Sec. ) (o C ) 15 17 -40~+150 · SCK 08 Zero Power Resistance at 25oC , Temperature ( Sec. ) (o C ) 16 38 -40~+170 · SCK 10 Zero Power Resistance at 25oC ( ) 1 1.3


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PDF E223037 SCK30-1R0 SCK30-1R5 SCK30-2R0 SCK30-2R5 SCK30-3R0 SCK30-4R0 SCK30-4R7 SCK30-5R0 SCK30-6R8 NTC SCK 055 THERMISTORS SCK 055 sck-0510 THERMISTORS SCK 053 THERMISTORS SCK 085 SCK-206 sck 104 NTC THERMISTORS SCK 054 ntc 8r0 sck 2r56
1995 - t101a

Abstract: DSP56166 T101 MGS1-0-10 sck 083 TH sck 083
Text: - - 1.414 0.707 354 100 Vp Vp mVp mVp G- 0.83 G G+ 0.83 dB Vref Output , Differential Load Resistance 1 - - k R bias - 10d - k VC- 0.83 VC VC+ 0.83 , and 2) T = Icyc / 4 SCK Pin = Serial Clock SFS Pin = Transmit/Receive Frame Sync i ck = Internal , , all the timings remain valid by inverting the clock signal SCK and/or the frame sync SFS in the tables , i ck ns 131 SCK Clock High Period TBD - i ck ns 132 SCK Clock Low Period


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PDF DSP56166 t101a T101 MGS1-0-10 sck 083 TH sck 083
12M11

Abstract: No abstract text available
Text: n SCK si v ss ^ 5n -0 .2 4 4 "- 14-LEAD SOIC 8-Lead XBGA: Top View . 083 " · HOLD V cc , v cc PIN 1 < . 083 in 9 vss C SI SCK ( o o CO o 00 +l ( CO 00 , allowing operation on a simple three-wire bus. The bus signals are a clock input ( SCK ) plus separate data , . Data is latched by the rising edge of the serial clock. Serial Clock ( SCK ) The Serial Clock controls , a write to the PIN NAMES Symbol CS SO SI SCK WP v ss v cc HOLD NC Description Chip Select Input


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PDF X25650 14-Lead 20-Lead 12M11
Not Available

Abstract: No abstract text available
Text: inputs. ■FEATURES • High Speed Operation: tpd ( SCK to QH’)=14ns typ. SCK ¥ ] sclr T ] qh' (T o p V iew ) FUNCTION TABLE F u n ctio n RCK SCK SLoad SCLR X X X D a ta loaded to in p u t , p a g a tio n D elay T im e SCK o r S L o ad o r SCLR to Q h ’ 6.0 2.0 175 - 14 , - - 25 - - 21 - 4.5 R C K to Q H ' 2.0 4.5 RCK to SCK 6.0 2.0 S


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PDF HD74HC597 HD74HC597 Quiesc051) 0D1D315 T-90-20
1997 - tda 9592

Abstract: TDA 2310 verilog code for Modified Booth algorithm tda 7830 TDA 8344 sl 7221 KGL80 AO33 FD2S
Text: No file text available


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PDF KGL80 KGL80pads. tda 9592 TDA 2310 verilog code for Modified Booth algorithm tda 7830 TDA 8344 sl 7221 KGL80 AO33 FD2S
zf gear

Abstract: OC23 ih001 IH-001 ef12 RBS 2109 TMP87PS68DF TMP87CS68DF TLCS-870 LQFP80-P-1212-0
Text: (Output) SlOserial data output P44 (SI) I/O (Input) SlOserial data input P43 ( SCK ) I/O (I/O , . SFR RAM DBR TEST ROM 0000H 003F / 0040 00BF 00C0 's 083 F 0F80 OFF F 1080 64 bytes 128 , 0110 0120 0130 0140 0230 0240 0 1 8 9 A B C D E 083 F Register bank 0 Register bank 1 , 083C 083C 083C 083C 083 D 083 D PCL 083 D 083 D PCl — 083 E PCL push 083 E PCH push down 083 E PCL *pop 083 E PCH — 083 F PCH down 083 F PSW 083 F PCH 083 F PSW — SP


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PDF TMP87CS68 TMP87CS68DF TMP87CS68 87CS68 TMP87CS68DF 60kbyte-256byte) LQFP80-P-1212-0 TMP87PS68DF zf gear OC23 ih001 IH-001 ef12 RBS 2109 TMP87PS68DF TLCS-870
2008 - sck 083

Abstract: AD7682 AD7689 AD7699 AD7949 MO-220-VGGD-1 MSOP-10
Text: SCK SDO DIN Sequencer COM GND Figure 1. Table 1. Multichannel14-/16-Bit PulSAR ADC Type , CNV Pulse Width Data Write/Read During Conversion SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V , Above 2.3 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV Low to SCK High DIN Valid , Conversion SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge


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PDF 16-Bit, AD7682 16-bit MO-220-VGGD-1 20-Lead CP-20-4) PR07353-0-2/08 081407-B sck 083 AD7682 AD7689 AD7699 AD7949 MO-220-VGGD-1 MSOP-10
RBS 2111

Abstract: TLCS-870 TMP87CS71BF TMP87PS71AF
Text: output P34 (SO) SIO serial data output P33 (SI) I/O (Input) SIO serial data input P32 ( SCK ) I/O (I , 083C 083C 083C 083C 083 D 083 D PCL 083 D 083 D PCL 083 E PCL Tush 083E PCH Push down 083 E PCl Pop 083 E PCH Pop *up 083 F PCH -d0wn 083 F PSW 083 F PCH 083 F PSW SP before execution SP after execution 083 F 083 F 083 D 083C I j t J 083 D 083C 083 F 083 F 0040h 083 F (a) Stacking order (b) Stack depth Figure 1-8. Stack 1.8 System Clock Controller The


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PDF P87CS71B TMP87CS71BF TMP87CS71B TMP87CS71BF 61184x8 P-QFP80-1420-0 TMP87PS71AF TLCS-870 16-bit -30to70Â RBS 2111 TMP87PS71AF
TH sck 083

Abstract: 32764KHz LPC11 LPC08 12768 LPC14
Text: rlta n r danrmines tha accuracy of tha countar. Tha SPI dock ( SCK ) provides data transfer control when , -0 .3 Voo x 0.7 -1 2S Vqq x 0.2 V- -*0.3 +1 0.4 Inpul Voltage Low, SCK . MOSI. CE. OSCI Input Voltage High, SCK , MOSI, CE, OSCI Input IjMkago Current. SCK , MOSI, OSC1 Output Voltage Low, MISO Output , SCK Rising Edge CE Falling Edge lo MISO High Z G O O t g e* m 2.72 Maximum Frequency 150 ISO 367 , B ct»«as*o,Ct0HO )-2oopF urn-» oftnmrf- np> Hfcd (ConHnuad) SYMBOL *0« TBTCONOmONS SCK Rung Edge


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PDF CDP68HC68T3 COP68HC68T3 1-WMM-MARR18 TH sck 083 32764KHz LPC11 LPC08 12768 LPC14
2013 - FPT-8P-M08

Abstract: MB85RS2MTPF MB85RS2M MB85RS2MT MB85RS2MTPF-G-JNE2 TH sck 083
Text: 1 8 VDD CS 1 8 VDD SO 2 7 HOLD SO 2 7 HOLD WP 3 6 SCK WP 3 6 SCK VSS 4 5 SI VSS 4 5 SI (DIP-8P-M03) (FPT-8P-M08) PIN FUNCTIONAL , making chips deselect. When HOLD is "L" level, hold operation is activated, SO becomes High-Z, SCK and SI , Voltage pin Ground pin 1 CS 3 WP 7 HOLD 6 SCK 5 SI 2 8 4 SO VDD VSS , FRAM Cell Array 262,144 8 CS Address Counter SCK Control Circuit FRAM Status Register


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PDF DS501-00023-0v01-E MB85RS2MT MB85RS2MT FPT-8P-M08 MB85RS2MTPF MB85RS2M MB85RS2MTPF-G-JNE2 TH sck 083
2013 - SEAM-10X40PIN

Abstract: SEAM-10X40 BPF filter rf GHz la25p DA1213 LTM9013
Text: /SER 9013 TA01 GAIN_Q GAIN_I ADC LNA 0° 90° ADC GND LO IN 100 5V 100 15nH 6.8pF 15nH 0.01µF SCK , ­ . ­0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) CS, SDI, SCK , Mode Input Voltage Input Resistance Input Capacitance ADC Logic Inputs (SDI, SCK , CS) VIH VIL High , specifications are at TA = 25°C. (Notes 5, 7) PARAMETER SCK Period CS to SCK Set-up Time SCK to CS Hold Time SDI Set-Up Time SDI Hold Time SCK Falling to SDO Valid Readback Mode CSDO = 20pF , RPULLUP = 2k SYMBOL tSCK


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PDF LTM9013 300MHz 14-Bit, 310Msps 66dBc n15mm 800MHz, SEAM-10X40PIN SEAM-10X40 BPF filter rf GHz la25p DA1213
Nippon capacitors

Abstract: MGS1000
Text: - Typ 78 - Max 1400 10 Unit kQ PF - - G 1.414 0.707 354 100 G+ 0.83 Vp Vp mVp mVp dB G- 0.83 1.8 - - 0 2 - - - 2.2 ±1 100 50 V mA mV nF oc - 100 nF - - - 1 2 - Vp Vp a k£2 ki2 dB 500 1 - VC- 0.83 - - - - VC+ 0.83 - I'D


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PDF DSP56166/D DSP56166 16-bit DSP56166 DSP56100 1ATX31996-0 OSP56166/D Nippon capacitors MGS1000
2009 - ML22321

Abstract: No abstract text available
Text: SCK and the event execution according to the number is started. Disconnection Detection Set the , setting Setting of thermal detection Setting of judgement temperature SCK pin setting SIN pin setting , 0Fh 10h 11h 12h 13h 14h Volume [dB] -0.41 - 0.83 -1.28 -1.75 -2.25 -2.77 -3.34 -3.94 -4.58 -5.28 -6.04 , Address Controller 16bit Multiplexer 896Kbit Flash VPP CSB SCK SIN TEST TESTI0 TESTI1 BUSYB SCKEN ERR , ML22321-xxx VDD GND VDDL Regulator Address Controller 16bit Multiplexer 896Kbit ROM CSB SCK SIN TEST


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PDF PEDL22321FULL-0 ML22Q321/321 ML22321/ML22Q321, 16bit ML22Q321/321 16bitPCM ML22321
2013 - LTM9013

Abstract: No abstract text available
Text: CLKOUT 0° LNA 90° ADC CLK OF GND SCK CS SDI SDO GND PAR/SER 9013 TA01 , (VDD + 0.3V) Digital Input Voltage (Note 4) CS, SDI, SCK , Logic Inputs (SDI, SCK , CS) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level , MAX UNITS SPI Port Timing (Note 10) tSCK SCK Period tS Write Mode Readback Mode CSDO = 20pF RPULLUP = 2kΩ , 40 250 ns ns CS to SCK Set-up Time 5 ns tH SCK to CS


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PDF LTM9013 300MHz 14-Bit, 310Msps 300MHz 66dBc QFN-20 LTM9002 14-Bit LTM9013
1998 - sck 083

Abstract: X25650 X25650Z X25650ZI 402 WP
Text: VCC VSS SI WP SCK PIN 1 4048±30 4048±30 1000±30 . 083 in. 2118±30 , simple three-wire bus. The bus signals are a clock input ( SCK ) plus separate data in (SI) and data out , X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 64 64 X 256 128 128 X , is selected and a serial sequence is underway, HOLD may be used to pause Serial Clock ( SCK ) The , V CC 2 7 HOLD WP 3 6 SCK V SS When CS is HIGH, the X25650 is deselected


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PDF X25650 X25650 536-bit sck 083 X25650Z X25650ZI 402 WP
2000 - TH sck 083

Abstract: sck 083 sck 084 X25650 X25650Z X25650ZI X5643
Text: VCC 2 7 S1 3 6 CS VSS SCK 4 5 WP . 083 in. X ic or NOTE: ALL , three-wire bus. The bus signals are a clock input ( SCK ) plus separate data in (SI) and data out (SO) lines , 8Kbyte Array 64 SO SI SCK CS HOLD Command Decode and Control Logic 64 X 256 64 , clock. SCK Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and , WPEN bit is set "1". 7 HOLD 3 6 SCK VSS When CS is HIGH, the X25650 is deselected


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PDF X5643 X25650 TH sck 083 sck 083 sck 084 X25650 X25650Z X25650ZI X5643
2001 - Not Available

Abstract: No abstract text available
Text: Mark XAAS XAAT 8-Lead XBGA: Top View HOLD 1 8 .159 in. VCC S1 SCK 2 7 3 6 4 5 SO CS VSS WP . 083 , . The bus signals are a clock input ( SCK ) plus separate data in (SI) and data out (SO) lines. Access to , same bus. O SO SI SCK CS HOLD Command Decode and Control Logic WP Write Control and , latched by the rising edge of the serial clock. Serial Clock ( SCK ) The Serial Clock controls the serial , clock input. Chip Select (CS) PIN NAMES Symbol CS SO SI SCK WP VSS VCC HOLD NC Description Chip


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PDF X5643 X25650 --14-lead
1994 - DSP56001

Abstract: DSP56100 DSP56156 DSP56156ROM DSP96002 b 0743
Text: Vp Vp mVp mVp G - 0.83 G G + 0.83 dB VREF Output Voltage 1.8 2 2.2 V , 0.83 VC VC + 0.83 dB Input Impedance on MIC and AUX (See Note 1) Internal Input Gain Variation; G = -6 dB, 0 dB, 6 dB or 17 dB (± 0.83 dB variation due to 10% variation on VCC): Allowable , Internal Output Volume Control Variation VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB (± 0.83 dB


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PDF DSP56156/D DSP56156 DSP56156ROM 16-bit DSP56156 DSP56001 DSP56100 DSP56156ROM DSP96002 b 0743
1994 - brand tai hen

Abstract: WT137 DSP56001 DSP56100 DSP56156 DSP56156ROM DSP96002 SRD kHz transmitter Lf MF J1184
Text: Vp Vp mVp mVp G - 0.83 G G + 0.83 dB VREF Output Voltage 1.8 2 2.2 V , 0.83 VC VC + 0.83 dB Input Impedance on MIC and AUX (See Note 1) Internal Input Gain Variation; G = -6 dB, 0 dB, 6 dB or 17 dB (± 0.83 dB variation due to 10% variation on VCC): Allowable , Internal Output Volume Control Variation VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB (± 0.83 dB


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PDF DSP56156/D DSP56156 DSP56156ROM 16-bit DSP56156 brand tai hen WT137 DSP56001 DSP56100 DSP56156ROM DSP96002 SRD kHz transmitter Lf MF J1184
2001 - CXP853P40AS-2

Abstract: CXP85340A CXP853P40A SPC700 SCK 083
Text: /SDA1 REMOCON TIMER/COUNTER PD7/EC PE7/TO PD6/RMC SERIAL I/O PD3/SI PD2/SO PD1/ SCK , PD1/ SCK 31 34 XTAL VSS 32 33 PD0/INT2 Note) 1. Vpp (Pin 63) is always , EXTAL PD0/INT2 VSS PD1/ SCK PD3/SI PD2/SO PD4/HSI PD5/ACI PD6/RMC 20 21 22 23 , ) Single bit selectable 8-bit I/O port. (8 pins) PD0/INT2 I/O/Input PD1/ SCK I/O/I/O PD2/SO , ­7­ Hi-Z CXP853P40A Pin Circuit format When reset Port D SCK or SO Output


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PDF CXP853P40A CXP853P40A CXP85340A providing42/COPPER 64PIN QFP-64P-L01 P-QFP64-14x20-1 42/COPPER CXP853P40AS-2 SPC700 SCK 083
Supplyframe Tracking Pixel