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Part Manufacturer Description Datasheet Download Buy Part
LTC1386CS#PBF Linear Technology LTC1386 - 3.3V Low Power EIA/TIA562 Transceiver; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1386CS#TRPBF Linear Technology LTC1386 - 3.3V Low Power EIA/TIA562 Transceiver; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1386CN Linear Technology IC LINE TRANSCEIVER, PDIP16, PLASTIC, DIP-16, Line Driver or Receiver
LTC1386IS#TRPBF Linear Technology LTC1386 - 3.3V Low Power EIA/TIA562 Transceiver; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C
LTC1386IS#PBF Linear Technology LTC1386 - 3.3V Low Power EIA/TIA562 Transceiver; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C
LTC1386CS Linear Technology LTC1386 - 3.3V Low Power EIA/TIA562 Transceiver; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C

SBC 1386 EX Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract:
Text: u ild e r S in g le B o a rd C o m p u te r L o n B u ild e r R o u te r ( SBC ) L o n B u il d , testing in a d istrib u ted environm ent. C onnects tw o LONWORKS com m unication channels. SBC , E valuation Board, or u sin g custom I / O ex p ansion bo ard s T C o n f ig u r a t io n T , er su p p lie d by th e d e v e lo p m e n t statio n for u se by ex p an sio n bo ard s) D im ensions P rocessor n e u r o n c h ip 0 to 40°C -20 to 65°C +5V @ 1.0A, p lu s ex p a n sio n p o w e


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PDF d3076
1994 - iy ab

Abstract:
Text: escape escape escape escape escape escape EX (SP),HL EX (SP),IX EX (SP),IY EX A,(HL) EX A,A EX A,A' EX A,B EX A,C EX A,D EX A,E EX A,H EX A,L EX AF,AF' EX B,B' Mode , E3 37 3F 37 07 0F 17 1F 27 2F 1F BA BA BA BA 34 12 12 EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EXALL EXTS EXTS EXTSW EXTSW EXX , RRD RRW RRW RRW RRW RRW RRW RRW RRW RST RST RST RST RST RST RST RST SBC SBC SBC


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PDF Z380TM iy ab CB120E Z380
1994 - Z380

Abstract:
Text: CALR CPW CPW RESC SBC RST RET RET POP JP JP EX CALL CALL PUSH AND AND RST RET RET , SWAP EX IN OUT SBC LD NEG NEG RETN IM LD IN OUT ADC LD MLT RETI IM LD IN OUT 0F , LD LD INC INCW INC DEC LD RLCA EX ADD LD DEC DECW INC DEC LD RRCA DJNZ LD LD INC , ADC ADC ADC ADC ADC ADC ADC SUB SUB SUB SUB SUB SUB SUB SUB SBC H,E H,H H,L H,(HL , B4 B5 B5 B6 B6 B7 SBC SBC SBC SBC SBC SBC SBC AND AND AND AND AND AND AND AND


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PDF Z380TM Z380
1998 - Z8018X

Abstract:
Text: , nnnn 4 INC (HL) DEC (HL) 6 7 8 9 A B C D E F RLCA EX AF , , A SBC A, B SBC A, C SBC A, D SBC A, E SBC A, H SBC A, L SBC A, (HL) SBC , A, A A AND A, B ADD A, C ADD A, D ADD A, E ADD A, H ADD A, L ADD , RET P POP HL POP AF 3 3 JP NC, nnnn 3 3 2 JP PO, nnnn 3 3 EX (SP , RET M LD SP, HL 3 2 JP PE, nnnn 3 3 EX , DE, HL 3 JP M, nnnn 3 CALL PE


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PDF Z8018X UM971800200
1994 - tyx 8016

Abstract:
Text: . Decimal operation is possible only with the ADC and SBC instructions. This flag can be set with the SEP , , RTS, TBY, TYX, CLC, SEC, TDA, WIT, ex . : Mnemonic CLC CLI, SEI, TDB, XAB CLM , C flag ? ? ? ? ? ? ? ? ? ? ? PS ? ? ? ? ? ? ? ? ? ? 0 ex . : Mnemonic TXA (m=1, x=1) Machine Code 8A16 l l16 X The upper-byte is not transferred. A l l16 8A16 ex , boundary. ADC, LDY, AND, MPY, ex . : Mnemonic ADC A, #0A5H (m=1) CLP, CMP, MPYS*, ORA, CPX


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PDF H-ED298-A KI-9409 tyx 8016 AD1216 30E616 "7790" Mitsubishi mitsubishi 7700 machine instruction mitsubishi 8-bit assembler language 12361 tyx IN 8016 FE16 FF10
1994 - "7700 Family" Mitsubishi

Abstract:
Text: . Decimal operation is possible only with the ADC and SBC instructions. This flag can be set with the SEP , , RTS, TBY, TYX, CLC, SEC, TDA, WIT, ex . : Mnemonic CLC CLI, SEI, TDB, XAB CLM , C flag ? ? ? ? ? ? ? ? ? ? ? PS ? ? ? ? ? ? ? ? ? ? 0 ex . : Mnemonic TXA (m=1, x=1) Machine Code 8A16 l l16 X The upper-byte is not transferred. A l l16 8A16 ex , boundary. ADC, LDY, AND, MPY, ex . : Mnemonic ADC A, #0A5H (m=1) CLP, CMP, MPYS*, ORA, CPX


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PDF 16-BIT J24532 H-ED298-A KI-9409 "7700 Family" Mitsubishi tyx 8016 tda 8216 TDA 7770 TDA 12021 TDA 6316 mitsubishi 7700 machine instruction FE16 EE16 429 A516
ISDN Network Termination

Abstract:
Text: Preliminary Am2080/B S-Bus Interface Circuit ( SBC ) DISTINCTIVE CHARACTERISTICS Full duplex , /0 March 1989 GENERAL DESCRIPTION The Am2080 S-Bus Interface Circuit ( SBC ) implements the , or more SBCs can be used to build a point-to-point, passive bus, ex tended passive bus, or star configuration. Specific ISDN applications of the SBC include: ISDN terminals, ISDN network termination (central , procedures. The SBC does not require direct microprocessor control. The SBC is an IOM compatible part, 22


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PDF Am2080/B AM2080 AM20B0B 22-Pin 28-Pin AM2080B ISDN Network Termination
Z80 CPU Instruction Set

Abstract:
Text: , zz ( ex . wwH, IXL) indicate upper and lower 8-bit of the 16-bit register respectively. BIT b , Addressing Operation Name Mnemonics Op Code SUBC SBC A,g 10 011 g Immed Ext Ind SBC , SBC A,m 7 11 011 110 S S SBC A,(IX + d) 11 011 101 10 011 110 SBC A,(IY + d , INC IY 11 111 101 00 100 011 SBC SBC HL ww 11 101 101 S X V 01 ww0 010 , Addressing 7 6 4 2 1 0 Operation Name Mnemonics Op Code Exchange EX AFAF' 00 001


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PDF Z8018x UM005001-ZMP0400 Z80 CPU Instruction Set ZZLX
1997 - M50734

Abstract:
Text: the instruction. In s tr u c tio n s : ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC Ex a m , , RRF, SBC , STA, STX, STY, TST Ex a m p le : Mnemonic ADC$40 Machine code 65 16 40 16 Memory , , LSR, MUL, ORA, ROL, ROR, SBC , STA, STY Ex a m p le : Mnemonic ADC$5E,X Machine code 7516 5E16 , , CMP, DEC, EOR, INC, LDA, LDY, LSR, ORA, ROL, ROR, SBC , STA Ex a m p le : Mnemonic ADC$AD12, X , , EOR, LDA, LDX, ORA, SBC , STA Ex a m p le : Mnemonics ADC$AD12, Y Machine code 7916 12 16 AD 16


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PDF
2000 - TLCS-90

Abstract:
Text: (07) (F)TLCS-900/L12(F/F´) EX (1) SR 15 SYSM 14 IFF2 13 IFF1 12 IFF0 11 MAX 10 , imm INCF DECF PUSH F/POP F EX F, F CPU900L1-8 2002-02-06 TLCS-900/L1 CPU , ', HL' ) EX ( EX A, A' ) ()( ) () TLCS-900CPU CPU CPU TLCS-900 · CPU · · / LDF imm , 5.1 TLCS-900/L1 LD PUSH dst, src src POP dst LDA LDAR EX MIRR dst, src dst , SUB SBC CP AND OR XOR INC DEC MUL MULS DIV dst, src dst, src dst, src dst, src dst


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PDF TLCS-900/L1 900/L, 900/H, 900/L1, 900/H2CPU TLCS-900 900/H25 TLCS-90 BC001 HL008 tlcs90 HL123 40p03 TLCS-900 tlcs-90 cpu xor a55H BC-001
TLCS-90

Abstract:
Text: 4 5 6 7 B SBC R, r EX R, r BW C AND R, r ADD ADC SUB SBC AND XOR OR CP r , , (mem) 3 EX (mem), R BW ADD ADC SUB SBC AND XOR OR CP BW (mem) ,# 4 MUL R, (mem) BW MULS R , ) ■pn V-fX — =l- K (1651) ii m SZHVNC Xx- h B~ EX F,F' 16 F F' * 1 2. -. - EX BW- EX R,r C8+zz+n :B8+R R * r 2 3. 3. - BW- EX (mem),R 80+zz+mem:30+R (mem) R 2+M 6. 6. - MIRR -W- MIRR r D8+n , +M# 2. 2. 2 3. 4. 6 4. 4. 6 6. 6. 10 7. 8. - SBC BWL BWL BWL BWL BW- SBC R,r SBC n,# SBC R,(mem) SBC


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PDF TLCS-900/H 16tfy 16fcf 8000Hâ TLCS-90 tlcs90 tlcs-90 cpu xor pfhx K1651 MEM34
1997 - M37420

Abstract:
Text: the instruction. In s tr u c tio n s : ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC Ex a m , , RRF, SBC , STA, STX, STY, TST Ex a m p le : Mnemonic ADC$40 Machine code 65 16 40 16 Memory , , LSR, MUL, ORA, ROL, ROR, SBC , STA, STY Ex a m p le : Mnemonic ADC$5E,X Machine code 7516 5E16 , , CMP, DEC, EOR, INC, LDA, LDY, LSR, ORA, ROL, ROR, SBC , STA Ex a m p le : Mnemonic ADC$AD12, X , , EOR, LDA, LDX, ORA, SBC , STA Ex a m p le : Mnemonics ADC$AD12, Y Machine code 7916 12 16 AD 16


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PDF J24532 M37420 M50734 sr 4416 m37451 PH m 8816 m37417 M37421 M37524 bbc 127 324 BA 8A16
XORB

Abstract:
Text: ex =613 AGNO AD3^P0j er 3D P5,/AI7 AD4fl>0, c=t P5(/AI6 AD5/P0S cr 3 P5j/AI5 ADft/POj ex , Register Direct Addressing j— ex . —-——-_ ROR DP 1.2 Displacement Addressing a) Zero Page ex . - A, 18H SFR 000H 0018H b) Di rea Page ex . - ST A, off XX10H RAM xkOQH xx10H 1.3 Pointing Register indirect Addressing a) Data Pointer (DP) Indirect — ex . - SLL [DP] RAM DP I- b) User Stack Pointer (USP) Indirect — ex . - SRL tOH [USP; m USP - 128— ♦ 127 I RAM 22 c) Index


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PDF MSM66201/66P201_ MSM66201 16-bit 10-bit MSM66P201, m-8044 021L02Ã XORB 2TW/170 61727 MSM66P201 P2e txc
MSM66207

Abstract:
Text: vmf AD2*0, CE JE AGNO aoi^oj ex 3D rsyAi7 A04*0, er 3D AD»/*», CE 3D ADt/*), CE 3D P5 , Register Direct Addressing — ex . - ROR DP 1.2 Displacement Addressing a) Zero Page - ex . - A. 18H SFR 000H 0018H b) Direct Page ■ex . - XX10H RAM xxOOH xx10H 1.3 Pointing Register Indirect Addressing a) Data Pointer (DP) Indirect — ex . - su. [DP] ram dp b) User Stack Pointer (USP) Indirect — ex . - 22 c) Index register (XI, X2) Indirect — ex . - INC 300H


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PDF MSM66207/66P207 8/16-BIT MSM66207 16-bit 10-bit MSM66P207, MSM66P207
2011 - SINAMICS - The Seamless and Integrated Drives Family for Every Application

Abstract:
Text: control, maintains its position and monitors standstill. Safe Brake Control ( SBC ) After STO, "Safe , G130/150 STO, SS1 SINAMICS S110 STO, SS1, SS2, SOS, SBC , SLS, SDI, SSM SINAMICS S120 Booksize and Blocksize STO, SS1, SS2, SOS, SBC , SLS, SDI, SSM SINAMICS S120 Chassis and Cabinet , Safety Integrated: STO, SS1, SLS and SBC (without encoder) up to SIL2 according to IEC 61508 and up to , , IP65 EX protection Optional: IEC: Ex nAII T3 (Zone 2) or dust-Ex Zone ( 21,22) Zone 1: IEC


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PDF E20001-A200-M112-X-7600 SINAMICS - The Seamless and Integrated Drives Family for Every Application sinamics s120 siemens logo application examples CU320 converter modbus to profibus simatic sinamics SM150 PLC S7 200 use encoder 3 phase induction motor for rolling mills dc motors for conveyor belts Milling machine control using single phase induction motor
1998 - ColdFire v5

Abstract:
Text: is a multi-cycle bus connecting the processor complex and the SBC , plus any other bus masters. s S - B u s is a simple multi-cycle "slave" bus controlled by the SBC that interfaces to integrated , HW Divide MAC K-to-M CNTRL Debug Unit E-BUS M-BUS SYSTEM BUS CNTRL ( SBC ) ADDR DATA , Unified Cache I Fetch Instr Buf Dec&Sel Op A Gen & Ex B u s C o n t r s Power Management ­ Variable , Dec&Sel Op A Gen & Ex B u s C o n t r J T A G s Power Management ­ Variable frequency of operation ­


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PDF 32-bit 16-bit MC680xl ColdFire v5 asm68k 68ec040 XC68307 MCF5206EFT54 xcf5307 VME bus 68040 scsi DIAB data MCF5307FT90 XC68HC901
TLCS-90

Abstract:
Text: LD r, R A SUB R, r LD r, #3 0 1 2 3 4 5 6 7 B SBC R, r EX R, r BW , CPIR CPD CPDR BW LP BW (nn),(rrV 2 LD R, (mem) wabCdehl 3 EX (mem), R BW ADD ADC SUB SBC , TOSHIBA TLCS-900/L CPU SBC dst, src < Subtract with Carry iir'J-'fitl > Jtjj # : dst<—dst — src , ^e - 7 ^ 3- K OOO SBC OOO SBC OOO sbc R, r r,# (mem), R O O X SBC (mem), # il1 Z , Z 1 1 r 1 1,0,1,1,0 lRl 1 , 1 z , z jJLL ^^Ql0!1!0!1!1 #<7:0> #<15:8> #<23:16> #<31:24> O O O SBC R, (mem) 1 m Z


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PDF TLCS-900/L CPU900L-150 CPU900L-191 900/Lii, 16fcf TLCS-90CI& TLCS-900/LT TLCS-90 SR8800 ycym tlcs90
1996 - tda 8216

Abstract:
Text: is possible only with the ADC and SBC instructions. Use the SEP instruction to set this flag to "1," , , RTL, TBX, TYB, Machine code 18 16 ex . : Mnemonic CLC PS C flag ? ? ? ? ? ? ? ? ? ? ? PS ? ? ? ? ? ? ? ? ? ? 0 ex . : Mnemonic TXA (m="1", x="1") Machine code 8A 16 X DATA L A The high-order byte is not changed. DATA L 8A 16 ex . : Mnemonic TXA (m="0", x , , LDY, AND, MPY, ex . : Mnemonic ADC A, #0A5H (m="1") CLP, CMP, MPYS, ORA, CPX, RLA


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PDF 16-BIT J24532 H-EF436-A KI-9607 tda 8216 tyx 8016 STK 4133 STK 4133 II tda 4816 TDA 12021 stk 654 stk 459 EE16 429 B716A
1996 - mitsubishi 7700 machine instruction

Abstract:
Text: , CMP, MPYS, ORA, CPX, RLA, CPY, SBC , DIV, SEP DIVS, EOR, LDA, LDT, LDX, Instruction : ex , , AND, CMP, DIV, DIVS, EOR, LDA, MPY, MPYS, ORA, SBC , STA Instruction : ex . : Mnemonic ADC A, (1EH , SBC instructions. Use the SEP instruction to set this flag to "1," and use the CLP instruction to , , TXY, RTI, TBS, TYA, RTL, TBX, TYB, Instruction : ex . : Mnemonic CLC PS Machine code 18 16 C flag ? ? ? ? ? ? ? ? ? ? ? PS ? ? ? ? ? ? ? ? ? ? 0 ex . : Mnemonic TXA (m="1", x="1") X


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PDF H-EF436-A KI-9607 mitsubishi 7700 machine instruction tyx 8016 bbc pg 222 tda 7751
bx21

Abstract:
Text: indicates the overflow (V) in an arithmetic operation (ADD, ADC, SUB, SBC , or CP). The flag is set to "1" , "1" if the executed operation is a subtraction (SUB, SBC , CP, or DEC), o Interrupt enable flag (IFF) A , and an alternative register: EX AF,AF1 EXX (5) Registers IX, IY, BX and BY IX and IY are 16 , immediate address, and memory and immediate address (ADO, ADC, SUB, SBC , AND, OR XOR and CP), or increment , [ I i I I 1 1 1 1 1 I 1 I 1 1 1 1 LD LD LD LD LD LD LD LD LD LDW PUSH POP LDA EX EX EXX EX


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PDF 001L7 TMP90C840 TMP90C840N/TMP90C841N TMP90C840F MPU90-20 TMP90C840 T-49-19-08 bx21 MPU90
2005 - Not Available

Abstract:
Text: Output Voltage IDD1 < = 10 mA IDD1 Stop Output Current to Wake-up SBC IDD1 Over Current to Wake-up , Duration SBC in Stop Mode Internal Oscillator Frequency All Modes Except Sleep and Stop (22) Internal Low , Request Mode Delay Between SPI and CAN Normal Mode SBC Normal Mode (24) Delay Between SPI and CAN Normal Mode SBC Normal Mode (24) Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode (VDD1 on and Reset High) SBC in Stop Mode Delay Between CS Wake-up (CS Low to High) and First Accepted API


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PDF MC33989
2005 - MC33989

Abstract:
Text: VDDSTOP2 VDD1 Output Voltage IDD1 < = 10 mA IDD1 Stop Output Current to Wake-up SBC IDD1SWU 10 , Frequency 34 tINT SBC in Stop Mode Internal Oscillator Frequency - 7.0 Interrupt Low , SPI and CAN Normal Mode Symbol SBC Normal Mode Max - - 10 µs - - 10 tWCS SBC in Stop Mode Unit µs tSCANS (22) Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode (VDD1 on and Reset High) Typ tSCANN SBC Normal Mode (22) Delay


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PDF MC33989 MC33989 MJD32C
bx31

Abstract:
Text: SUB HL,mem I SRA mem | | EXX I XOR r,n I SBC HL.rr I SLLA f | EX mem,rr | XOR mem, a I SBC HL,nn i , ) in. an arithmetic operation (ADD, ADC, SUB, SBC , or CP). The flag is set to "1" when the result , executed operation is a subtraction (SUB, SBC , CP, or DEC), o Interrupt enable flag (IFF) A maskable , insturctions that allow the exchange of data between a main register and an alternative register: EX AF,AF1 , , Register A and memory, register and immediate address, and memory and immediate address (ADD, ADC, SUB, SBC


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PDF TMP90C840 TMP90C840N/TMP90C841N TMP90C840F TMP90C840 16-bit aaibfl70 T-49-19-08 T-49-19-59 bx31 TMP90C840N BX21 1X21x1 UO6C P8LC SLAA tmp90c841
2006 - CAN split termination

Abstract:
Text: 10 mA IDD1 Stop Output Current to Wake-up SBC IDD1 Over Current to Wake-up Deglitcher Time Reset , Activation Detected by V2 OFF (22) Interrupt Low Level Duration SBC in Stop Mode Internal Oscillator , SPI and CAN Normal Mode SBC Normal Mode (24) Delay Between SPI and CAN Normal Mode SBC Normal Mode , SBC Normal Request Mode (VDD1 on and Reset High) SBC in Stop Mode Delay Between CS Wake-up (CS Low to High) and First Accepted API Command SBC in Stop Mode Delay Between INT Pulse and First SPI Command


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PDF MC33989 CAN split termination
1997 - 1553B

Abstract:
Text: 3.0 BUS CONTROLLER ARCHITECTURE The S MMIT bus controller ( SBC ) is an interface device linking a MIL-STD-1553 serial data bus to a host microprocessor and/or subsystem. The SBC 's architecture is based , reduce host overhead, the SBC 's RISC-based core automatically executes data handling, message error checking, memory control, and related protocol functions. This section discusses the following SBC , initialize the S understand the internal registers. The SBC registers offer many programmable functions and


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PDF MIL-STD-1553 1553B MIL-STD-1553A
Supplyframe Tracking Pixel