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S3 Vision864

Abstract: S3 vision868 vision968 s3 tech vision864 PD-60 Vision9 CR683 3c3h 928PCI
Text: Corporate Logo, S3 801, S3 805, S3 PS805, S3 805i, S3 928, S3 928PCI, Vision64, Vision864 , Vision866 , PA3 PA4 TGDSDMT 0 0 0 0 7 5 5 0Ö4 # 3 Vision864 Graphics Accelerator S3 In c o rp o , process and can be obtained directly fro m S3 . RGGSD4T QQQG7t3 ISO ELECTRICAL DATA 4-7 Vision864 , Vision864 Graphics Accelerator S 3 In c o rp o ra te d Vision864 Graphics Accelerator October 1994 S3 Incorporated 2770 San Tomas Expressway îanta Clara, CA 95051-0968 d f t _


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PDF Vision864 208-pin S3 Vision864 S3 vision868 vision968 s3 tech PD-60 Vision9 CR683 3c3h 928PCI
S3 vision868

Abstract: S3 Vision864 S3 TRIO64 S3 TRIO32 S3 TRIO 3D S3 TRIO 64 vision968 vision864 S3 TRIO 3d on board S3 TRIO pci
Text: 95051-0968. The S3 Corporate Logo, S3 on Board, S3 on Board design, Vision64, Vision864 , Vision868, Vision964 , S3 Vision868 M ultim edia Accelerator T able 2-1. Register Differences Between the Vision864 and , S 3 In c o rp o ra te d ¿S S3 Vision868 M ultim edia Accelerator Vision868 Multimedia Accelerator April 1995 S3 Incorporated 2770 San T o m as Expressway Santa Clara, CA 95051-0968 ^00504^ DOOCHTD 1SS I S3 Vision868 M ultim edia Accelerator S 3 In c o rp o ra te d N


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PDF Vision868 S3 vision868 S3 Vision864 S3 TRIO64 S3 TRIO32 S3 TRIO 3D S3 TRIO 64 vision968 vision864 S3 TRIO 3d on board S3 TRIO pci
S3 Vision864

Abstract: vision968 S3 TRIO32 S3 TRIO 64 S3 vision868 S3 TRIO 3d on board S3 TRIO 3D S3 TRIO64 7 segment display LTS 542 pin diagram 7 segment display LTS 543 pin configuration
Text: Corporate Logo, S3 on Board, S3 on Board design, Vision64, Vision864 , Vision868, Vision964, Vision968, Trio , S3 Vision968 Multimedia Accelerator S 3 In co rp o ra te d Vision968 Multimedia Accelerator A pril 1995 S3 Incorporated 2770 San Tomas Expressway Santa Clara, CA 95051-0968 ^ 0 5 0 4 ^ 0 0 0 1 31 1 01b I® S 3 In c o rp o ra te d S3 Vision968 Multimedia Accelerator , to 1024, not 1,000 bytes. NOTICES © C o pyright 1995 S3 Incorporated. A ll rights reserved. No


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PDF Vision968 S3 Vision864 S3 TRIO32 S3 TRIO 64 S3 vision868 S3 TRIO 3d on board S3 TRIO 3D S3 TRIO64 7 segment display LTS 542 pin diagram 7 segment display LTS 543 pin configuration
s3 trio64v

Abstract: s3 trio64v VGA BIOS pinout s3 trio64v VGA BIOS trio64v Vision964 S3 vision868 S3 TRIO32 PD-60 S3 Vision864 S3 trio64v vga card
Text: rio r w ritte n consent o f S3 Incorporated, 2770 San Tom as Expwy., Santa Clara CA 95051-0968. The S3 Corporate Logo, S3 801, S3 805, S3 PS805, S3 805i, S3 928, S3 928PCI, Vision64, Vision864 , Vision866 , January 1995 S3 Incorporated 2770 San T om as Expressway Santa Clara, CA 95051-0968 ^ D O ° , 1024, not 1,000 bytes. NOTICES © C o pyright 1994,1995 S3 Incorporated. A ll rights reserved. No , S3 Incorporated and S3 and True Acceleration are registered tradem arks o f S3 Incorporated. O ther


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PDF Vision964 00D10L7 208-pin s3 trio64v s3 trio64v VGA BIOS pinout s3 trio64v VGA BIOS trio64v S3 vision868 S3 TRIO32 PD-60 S3 Vision864 S3 trio64v vga card
1997 - intel 28f160

Abstract: 96hcc AP-646 28F320 AP-645 28F320S5 28F320S3 28F160S5 28F160S3 bsr27
Text: S3 /S5. 11 4.5 Command Queuing , Migration to S3 /S5. 6 Table 2. Software Checklist for the SA/SV Migration to the S3 /S5 . 7 Table 3. 3 Volt/5 Volt FlashFileTM Memory Pinout Differences , Table 6. Summary of Command Changes Between the SA/SV and the S3 /S5 . 9 Table 7. Identifier Code , Cross Reference: SA/SV to S3 /S5 . 14 Table 10. VCC Voltage Comparison


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PDF AP-645 28F160S3, 28F320S3, 28F160S5, 28F320S5) 28F016SV 16-Mbit 28F016SA intel 28f160 96hcc AP-646 28F320 AP-645 28F320S5 28F320S3 28F160S5 28F160S3 bsr27
XF0506-S3

Abstract: S3 63 A XFMRS 1416
Text: µH ADC A DCR OHMS B C MAX (ALL IN INCHES) 6XF4709- S3 6XF6809- S3 6XF0016- S3 6XF0026- S3 6XF0056- S3 6XF0086- S3 6XF0106- S3 6XF0156- S3 6XF0206- S3 6XF0256- S3 6XF0336- S3 6XF0506- S3 6XF0686- S3 6XF1006- S3 6XF1506- S3 6XF2006- S3 6XF3006- S3 .42 .75 1.18 2.30 4.70 7.94 10.58 , .235 7XF4709- S3 7XF6809- S3 7XF0016- S3 7XF0026- S3 7XF0056- S3 7XF0086- S3 7XF0106- S3 7XF0156- S3 7XF0206- S3 7XF0256- S3 7XF0336- S3 7XF0506- S3 7XF0686- S3 7XF1006- S3 7XF1506- S3 7XF2006- S3 7XF3006- S3


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PDF 6XF4709-S3 6XF6809-S3 6XF0016-S3 6XF0026-S3 6XF0056-S3 6XF0086-S3 6XF0106-S3 6XF0156-S3 6XF0206-S3 6XF0256-S3 XF0506-S3 S3 63 A XFMRS 1416
2005 - 82801AA

Abstract: MIC2010 MIC2010-1PCQS MIC2010-2PCQS MIC2070
Text: requirements for USB Wakeup from the ACPI S3 state. The MIC2010 will directly switch its two outputs between , continuous output current specification. In the S3 state the current-limit can be reduced to a value , make-before-break switching to ensure glitch-free transitions between the S3 and S0 states. Each channel is also , independent switches · Integrated switching matrix supports ACPI S0/ S3 state transitions without external , OUT1 ON/OFF 1 EN1 EN2 S3 # RSET1 GND OUT2 ON/OFF 2 Downstream USB Port 1 S3


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PDF MIC2010/2070 MIC2010/MIC2070 MIC2010 500mA M9999-101104 82801AA MIC2010-1PCQS MIC2010-2PCQS MIC2070
2005 - Not Available

Abstract: No abstract text available
Text: requirements for USB Wakeup from the ACPI S3 state. The MIC2010 will directly switch its two outputs between , continuous output current specification. In the S3 state the current-limit can be reduced to a value , make-before-break switching to ensure glitch-free transitions between the S3 and S0 states. Each channel is also , independent switches • Integrated switching matrix supports ACPI S0/ S3 state transitions without external , MAIN D– 100µF AUX OUT1 ON/OFF 1 EN1 EN2 S3 # CONTROL S3 # GND OUT2 ON


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PDF MIC2010/2070 MIC2010/MIC2070 MIC2010 500mA M9999-101104
1997 - 96hcc

Abstract: AP-645 28F160SV intel 28f160 s5 29220* intel 28F320S5 28F320S3 28F160S5 28F160S3 28F016SV
Text: .11 4.4.7 STS Configuration .11 4.4.8 Commands Not Supported on the S3 /S5 , for SA/SV Migration to S3 /S5 .6 Table 2. Software Checklist for the SA/SV Migration to the S3 /S5 .7 Table 3. Word-Wide FlashFileTM Memory Pinout , /320S3: Voltage Combinations 8 Table 6. Summary of Command Changes Between the SA/SV and the S3 /S5 , .12 Table 9. Status Register Bit Cross Reference: SA/SV to S3 /S5 .14


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PDF AP-645 28F160S3, 28F320S3, 28F160S5, 28F320S5) AP-393 28F016SV 28F016SA AP-375 28F008SA 96hcc AP-645 28F160SV intel 28f160 s5 29220* intel 28F320S5 28F320S3 28F160S5 28F160S3
au6332

Abstract: Transcend microSD microsd usb adapter SMI331 microsd adapter microsd chip manufacturer microsd adapter usb reset nand flash transcend microsd reader microSD card reader
Text: TS1~2GUSD- S3 microSD Memory Card + Reader S3 Description Features · ROHS compliant , Inc. 1 Reserved TS1~2GUSD- S3 microSD Memory Card + Reader S3 Architecture Transcend Information Inc. 2 TS1~2GUSD- S3 microSD Memory Card + Reader S3 Bus Operating Conditions · , cards CL 3 Remark TS1~2GUSD- S3 microSD Memory Card + Reader S3 · Bus Signal Levels As , V VSS ­ 0.3 0.25* VDD V 4 TS1~2GUSD- S3 microSD Memory Card + Reader S3 · Bus


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2005 - MIC2012CM

Abstract: No abstract text available
Text: Wakeup from the ACPI S3 state. The MIC2012 will directly switch its two outputs between a 5V main supply , set at 500mA minimum per channel satisfying the USB continuous output current specification. In the S3 , conditions. The MIC2012 provides make-before-break switching to ensure glitch-free transitions between the S3 , Integrated switching matrix supports ACPI S0/ S3 state transitions without external FET circuits , Motherboards Typical Application ATX Power Supply 5V MAIN 5V STANDBY MIC2012P MAIN AUX S3 Control S3


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PDF MIC2012 MIC2012/MIC2072 MIC2012 500mA 100mA MIC2012/2072 MIC2012CM
2001 - 82801AA

Abstract: MIC2010 MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
Text: distribution requirements for USB Wakeup from the ACPI S3 state. The MIC2010 will directly switch its two , continuous output current specification. In the S3 state the current-limit can be reduced to a value , make-before-break switching to ensure glitch-free transitions between the S3 and S0 states. Each channel is also , independent switches · Integrated switching matrix supports ACPI S0/ S3 state transitions without external , EN1 EN2 S3 # RSET1 GND OUT2 ON/OFF 2 Downstream USB Port 1 S3 # CONTROL VBUS


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PDF MIC2010/2070 MIC2010/MIC2070 MIC2010 500mA resis20) 16-Pin 82801AA MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
2002 - XAPP416

Abstract: RAMB16s RAMB16 XC2V40 DOB10 DOB20
Text: I - - - - I - - S3 - - S3 - R S3 - - S3 - - S3 - - S3 - R S3 - - S3 - - I - I - - S2 T - S2 T M S2 T , - I - I - - S0 T - S0 T - S0 T - S0 T - S0 T - S0 T - S0 T - S0 T - I - I - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - I - I - - S2 T - S2 T - S2 T - S2 T - S2 T - S2 T - S2 T - S2 T - , T - S0 T - S0 T - S0 T - S0 T - I - I - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - I , I - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - S3 - - I - I - - S2 T - S2 T - S2 T - S2 T -


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PDF XAPP416 700ns 686ns 646ns 659ns 668ns XAPP416 RAMB16s RAMB16 XC2V40 DOB10 DOB20
sfp s1.1

Abstract: S3 L13 SFP EVAL BOARD STS-48 XRT91L80 power supply tester schematic diagram stm16 sfp
Text: . 9 Table 1.2 Dipswitch S3 , Receive 4-bit Parallel Differential Bus Interface S1 S2 and S3 Control Dipswitches Evaluation board , XRT91L80 hardware control pins are interfaced to three control dipswitches (S1, S2, and S3 ). The logical , RLOOPP xxxxxxxx DLOOP HW / HOST - S3 OFF / ON POLARITY xxxxxxxx LOSEXT LPTIMEJA DISRD -LOOPBW - S2-1 S2-2 S2-3 S2-4 S2-5 S2-6 S2-7 S2-8 S3


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PDF EVM-91L80 STS-48/STM-16 XRT91L80 XRT91L80 sfp s1.1 S3 L13 SFP EVAL BOARD STS-48 power supply tester schematic diagram stm16 sfp
2012 - MIC2012CM

Abstract: 82801AA MIC2012 MIC2012BM MIC2072 MIC2012YM
Text: requirements for USB Wakeup from the ACPI S3 state. The MIC2012 will directly switch its two outputs between , output current specification. In the S3 state the current-limit can be reduced to only 100mA per channel , ensure glitch-free transitions between the S3 and S0 states. Each channel is also thermally isolated , Recognized Component Two completely independent switches Integrated switching matrix supports ACPI S0/ S3 , Typical Application ATX Power Supply 5V MAIN VBUS 5V STANDBY D+ MIC2012P MAIN AUX S3


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PDF MIC2012 MIC2012/MIC2072 MIC2012 500mA 100mA MIC2012/2072 MIC2012CM 82801AA MIC2012BM MIC2072 MIC2012YM
2003 - AL3102

Abstract: Wavefront Semiconductor AL3101 11010-1c Wavefront al3101 0104-30 s1bc S324 011101CCCCCCCCCCCCCCCCCCCCCC0MMMMMMMMMMM
Text: Constant Format: S3 .24 Value stored in U: A Value quantized to 22-bits for multiply: N/A Code , Format: S3 .18 Value stored in U: A Value quantized to 22-bits for multiply: N/A Code , memory_address Operation: A -> memory_address, 1.0 * A + constant Constant Format: S3 .18 Value stored in U: A , > memory_address, A -> B, 1.0 * A + constant Constant Format: S3 .18 Value stored in U: A Value quantized to 22 , + constant Constant Format: S3 .24 Value stored in U: B Value quantized to 22-bits for multiply: N


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PDF AL3101 AL3102) AL3102 Wavefront Semiconductor 11010-1c Wavefront al3101 0104-30 s1bc S324 011101CCCCCCCCCCCCCCCCCCCCCC0MMMMMMMMMMM
2001 - 82801AA

Abstract: MIC2010 MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
Text: distribution requirements for USB Wakeup from the ACPI S3 state. The MIC2010 will directly switch its two , continuous output current specification. In the S3 state the current-limit can be reduced to a value , make-before-break switching to ensure glitch-free transitions between the S3 and S0 states. Each channel is also , independent switches · Integrated switching matrix supports ACPI S0/ S3 state transitions without external , EN1 EN2 S3 # RSET1 GND OUT2 ON/OFF 2 Downstream USB Port 1 S3 # CONTROL VBUS


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PDF MIC2010/2070 MIC2010/MIC2070 MIC2010 500mA resis20) 16-Pin 82801AA MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
2000 - resume

Abstract: No abstract text available
Text: devices in IAPC systems that are going to the S3 (system) sleep state. There are two main types of tests , the PC be put into S3 manually, using the power button. The switch test also wakes the PC manually , for the standby state. This test specifies, for example, that the system will enter S3 after a , known-good device and must work well in a system that supports S3 . Intel's site for the Reference Platform , correct power-management behavior in S3 systems. These tests verify that the graphics hardware and driver


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PDF
c06r

Abstract: 74AC11181 74AC11181D 74AC11181N 74ACT11181D 74ACT11181N SG-45 DIODE C06 15 74ACT11181
Text: the four Function Select inputs (S0 - S3 ) and the Mode Control input (M) and can perform PIN , [Ï3 M s2 C-rfl« m s3 Active-High Operands 28 27 26 2S 24 23 20 1 1 1 1 1 1 1 19 I 1 c , inputs 18, 17, 16, 15 Sq- S3 Function select inputs 1 Cn Carry input 14 Cn+4 Carry output 3 A = B , ARITHMETIC" LOGIC (M: = L) S3 S2 S1 SO (M = H) Cn = L Cn = H (no carry) (with carry) L L L L à , ACTIVE HIGH INPUTS & OUTPUTS SELECTION ARITHMETIC* LOGIC (M: = L) S3 S2 S1 SO (M = H) Cn=H


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PDF 74AC/ACT11181 10MHz c06r 74AC11181 74AC11181D 74AC11181N 74ACT11181D 74ACT11181N SG-45 DIODE C06 15 74ACT11181
2000 - MIC2012CM

Abstract: 82801AA MIC2012 MIC2012-1CQS MIC2012PCM MIC2072
Text: distribution requirements for USB Wakeup from the ACPI S3 state. The MIC2012 will directly switch its two , continuous output current specification. In the S3 state the current-limit can be reduced to only 100mA per , ensure glitch-free transitions between the S3 and S0 states. Each channel is also thermally isolated , Integrated switching matrix supports ACPI S0/ S3 state transitions without external FET circuits · , 5V STANDBY D+ MIC2012P MAIN AUX S3 Control D­ OUT1 OUT2 Downstream USB Port 1


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PDF MIC2012 MIC2012/MIC2072 MIC2012 500mA 100mA MIC2012/2072 MIC2012CM 82801AA MIC2012-1CQS MIC2012PCM MIC2072
t416

Abstract: 74HCT00 2N2222 2N2907 AIC1730 MT18LSDT1672 PC MOTHERBOARD POWER DISTRIBUTION PC MOTHERBOARD diagram s3 application sheet
Text: designated S0, S3 and S5. S0 is the full-power state, power. The 3.3V SDRAM is generated by either one , turned on as a switch. That makes input and output connected. When the main power is absent, the S3 and S5 linear regulator is activated and generating a S3 is a state in which the processor is , U1 C1 1 VIN 2 GND 1mF 3 CTL S3 # 4 NB 5 4 9 5 AIC1730 Q3 , switch (MOSFET) and LDO 5VSBY PWRGOOD are controlled by the S3 #, S5# and PWRGOOD (PWR_OK) lines


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PDF AN00-007 AIC1730 220mF t416 74HCT00 2N2222 2N2907 MT18LSDT1672 PC MOTHERBOARD POWER DISTRIBUTION PC MOTHERBOARD diagram s3 application sheet
2000 - 82801AA

Abstract: MIC2010 MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
Text: distribution requirements for USB Wakeup from the ACPI S3 state. The MIC2010 will directly switch its two , continuous output current specification. In the S3 state the current-limit can be reduced to a value , make-before-break switching to ensure glitch-free transitions between the S3 and S0 states. Each channel is also , independent switches · Integrated switching matrix supports ACPI S0/ S3 state transitions without external , EN1 EN2 S3 # CONTROL S3 # GND OUT2 ON/OFF 2 Downstream USB Port 1 VBUS FAULT1


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PDF MIC2010/2070 MIC2010/MIC2070 MIC2010 500mA res20) 16-Pin 82801AA MIC2010-1CQS MIC2010-1PCQS MIC2010-2CQS MIC2070
2012 - QFN40-P-0606-0

Abstract: No abstract text available
Text: : Selectable by external terminal) Programable softstart time by external capacitor Supports S0, S3 ,S4,S5 states , PGND-1 EFUSEVDD TFUSE TSDA TSCL TSELT S3 S5 DISC TEST-1 TEST-2 TEST-3 39 36 37 38 40 32 33 34 1 2 , PVDD-2 9 PVDD-2 10 NC VDDQOUT VDDQOUT VDDQOUT PGND-1 PGND-1 PGND-1 PGND-2 PGND-2 VTT VTT 30 FSEL S3 , of the TC7731. 30 31 32 33 34 35 36 37 38 39 40 SGND FSEL S3 S5 DISC VDD TFUSE TSDA TSCL EFUSEVDD , converter. L: Set switching frequency 500 kHz. H: Set switching frequency 1.0 MHz. Suspend ( S3 ) control


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PDF TC7731FTG QFN40-P-0606-0
352068-1

Abstract: GR-1217-CORE GR-1217 CompactPCI 352068-1 S31131 telcordia GR-1217-CORE s3 application sheet
Text: 20,0- -21,! ~~i r ni m M M I SI S3 S3 S3 S3 S3 S3 S311313IX 13 S3 S3 S3 S3 S3 S3 S3 S3 S3 K lg S3 S3 S3 S3 S3 S3 S3 S3 S3 K ¿b-Ô-Ô-Ô-Ô-^ T/Vr —i-â>-Ô-Ô-Ô-Ô- -10 x 2,0 = 20


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PDF -12x4 26MAR1 27jum 20JAN97 352068-1 GR-1217-CORE GR-1217 CompactPCI 352068-1 S31131 telcordia GR-1217-CORE s3 application sheet
Application Notes SN74181

Abstract: 54181 texas 74 series logic gates sn74181 Application Notes SN74182 Alu 181 SN54LS181 SN54S181 SN74LS181 SN74S181
Text: PACKAGE SN74LS181. SN74S181 . . . DW. J OR N PACKAGE (TOP VIEW) BO c 1 U24 3 Vcc AO c 2 23 D Al S3 c 3 , . These operations are selected by the four function-select lines (SO, SI, S2, S3 ) and include addition , , the ALU must be placed in the subtract mode by placing the function select inputs S3 , S2. S1, SO at L , functions are selected by use of the four function-select inputs (SO, S1 ,S2, S3 ) with the mode-control input , ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS signal designations (continued) I I S3 S2 SI SO AO F A1 1 Ã


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PDF SN54181, SN54LS181, SN54S181, SN74181, SN74LS181 SN74S181 SN54181. SN54LS181. SN54S181 SN74181 Application Notes SN74181 54181 texas 74 series logic gates sn74181 Application Notes SN74182 Alu 181 SN54LS181 SN54S181
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