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Part Manufacturer Supplier Stock Best Price Price Each Buy Part
TDRSRXB-240A Magnecraft Allied Electronics & Automation - $32.62 $32.62
TDRSRXB-240V Magnecraft Master Electronics 9 $33.69 $17.10
TDRSRXB-24V Magnecraft Allied Electronics & Automation - $53.92 $41.10
TDRSRXB-24V Magnecraft Master Electronics 13 $59.65 $55.42

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RXB 24 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1993 - INS8250

Abstract: RXB 24 ST16C550 ST16C450 ST16C2552IJ44 ST16C2552CQ48 ST16C2552CJ44 ST16C2552 NS16C552 NS16C550
Text: CDB* INTB 17 29 DSRB* 28 CTSB* 27 DTRB* 26 TXB 25 RXB 24 IOR* 23 , ° C -40° C to + 85° C 3-135 15 16 17 18 19 20 21 22 23 24 CS* MFB* IOW* RESET GND RTSB* IOR* RXB TXB DTRB* CTSB* ORDERING INFORMATION , * 24 I Read strobe. (active low) A low level on this pin transfers the contents of the ST16C2552 , capable of taking any clock input from DC- 24 MHz and dividing it by any divisor from 1 to 216 -1. The


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PDF ST16C2552 ST16C2552CJ44 ST16C2552 INS8250 RXB 24 ST16C550 ST16C450 ST16C2552IJ44 ST16C2552CQ48 ST16C2552CJ44 NS16C552 NS16C550
2006 - AN3099

Abstract: DM9161E MSC7116 MSC7119 0x50020000 flushing ring MC71
Text: Register 30 29 28 27 26 25 24 23 HBERR BABR BABT GRA TFINT TXB RFINT RXB TYPE , TXB 26 0 RFINT 25 0 RXB 24 0 MII 23 0 - 22 0 A graceful stop , Register 31 30 29 28 27 26 25 24 23 ENET_BASE + 0x084 22 21 - SET , Bit Transmit Control Register 31 30 29 28 27 26 25 24 ENET_BASE + 0x0C4 , TMD - R/W R R/W R TYPE SET 29 28 25 24 23 22 ENET_BASE +


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PDF AN3099 MSC711x MSC7113, MSC7116, MSC7119. AN3099 DM9161E MSC7116 MSC7119 0x50020000 flushing ring MC71
2006 - DM9161E

Abstract: TDA 2010 AN3099 MSC7116 MSC7119
Text: Register 30 29 28 27 26 25 24 23 HBERR BABR BABT GRA TFINT TXB RFINT RXB TYPE , . 0 TXB 26 0 RFINT 25 0 RXB 24 0 MII 23 0 - 22 0 A graceful , . RCTL Bit Receive Control Register 31 30 29 28 27 26 25 24 23 ENET_BASE , ; TCTL Bit Transmit Control Register 31 30 29 28 27 26 25 24 ENET_BASE + , TAG1 TAG0 - TMD - R/W R R/W R TYPE SET 29 28 25 24 23 22


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PDF MSC711x MSC7113, MSC7116, MSC7119. MSC711XADS DM9161E TDA 2010 AN3099 MSC7116 MSC7119
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2002 - PLL 2400 MHZ

Abstract: No abstract text available
Text: Footprint 4 mm × 4 mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 , TLK1002RGE TLK1002RGER PACKAGE 24 pin 4 mm × 4 mm QFN, tube 24 pin 4 mm × 4 mm QFN, tape and reel Please , stage + - RXB + RXB - reference voltage and bias current generation VDD GND ENA LBA VDD , serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input , LBB is pulled low, the retimed input data signal applied to RXB +/ RXB ­ is available at TXA+/TXA­ and


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PDF TLK1002 SLLS626 24-Lead PLL 2400 MHZ
PM-DB2791

Abstract: MIL-STD-1553 schematic fpga 3C80 555 timer project 3EC0 holt ic 6110 Holt 1553 Controller - HI6110 6110RT_FPGA_2.ZIP 1A80 an555
Text: INTEGRATED CIRCUITS 9 AN-555 Mode Code commands MC RXB mcode 16 17 18 19 20 21 22 23 24 25 26 27 28 29 , RxB Int Flag[15] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4006 RxB Int Flag[31] 30 29 28 27 26 25 24 23 22 , 20 19 18 17 16 402C 400E MC RxB Int Flag[31] 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 402E MC RxB , RTAP GND E2 G6 D1 E3 E4 F6 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 , 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60


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PDF AN-555 HI-6110 MIL-STD-1553 PM-DB2791 MIL-STD-1553 schematic fpga 3C80 555 timer project 3EC0 holt ic 6110 Holt 1553 Controller - HI6110 6110RT_FPGA_2.ZIP 1A80 an555
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2005 - TLK1002A

Abstract: TLK1002ARGER TLK1002ARGERG4 TLK1002ARGET TLK1002ARGETG4
Text: 70°C Small Footprint 4 mm × 4 mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in , conditioning PLL DIN input buffer stage + 2 SEL RXB + - I1 I2 2 ICLK MUX 2 2 RXB - reference voltage and bias current generation VDD ENA LBA GND VDD GND LBB , data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages , +/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB +/ RXB ­ is available at TXA


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PDF TLK1002A SLLS661 24-Lead TLK1002A TLK1002ARGER TLK1002ARGERG4 TLK1002ARGET TLK1002ARGETG4
2005 - TLK1002A

Abstract: TLK1002ARGER TLK1002ARGERG4 TLK1002ARGET TLK1002ARGETG4 synthesizer pll
Text: 70°C Small Footprint 4 mm × 4 mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in , conditioning PLL DIN input buffer stage + 2 SEL RXB + - I1 I2 2 ICLK MUX 2 2 RXB - reference voltage and bias current generation VDD ENA LBA GND VDD GND LBB , data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages , +/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB +/ RXB ­ is available at TXA


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PDF TLK1002A SLLS661 24-Lead TLK1002A TLK1002ARGER TLK1002ARGERG4 TLK1002ARGET TLK1002ARGETG4 synthesizer pll
2005 - TLK100

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead TLK100
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2013 - Not Available

Abstract: No abstract text available
Text: 1 24 RXB LAD3 2 23 DTRB#/PS_2E0_IRQB LAD2 3 22 RTSB#/PS_CONF_KEY1 , software. See Table 1 ’UART Power On Configuration’. RXB 24 I UART Channel B Receive data , Q B R X F IF O W D TO U T#/ PS_W D T RXB R T S B # /P S _ C O N F _ K E Y 1 /R S 4 8 5 , during reset or idle (no data). ANCILLARY SIGNALS CLKIN 9 I Clock input 24 MHz or 48 MHz , write (0x4F, 0x0); //Select the input clock frequency 24 MHz write (0x4E, 0x7); //Select the


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PDF XR28V382 128-BYTE 16-bit
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2013 - Not Available

Abstract: No abstract text available
Text: 1 24 RXB LAD3 2 23 DTRB#/PS_2E0_IRQB LAD2 3 22 RTSB#/PS_CONF_KEY1 , software. See Table 1 ’UART Power On Configuration’. RXB 24 I UART Channel B Receive data , Q B R X F IF O W D TO U T#/ PS_W D T RXB R T S B # /P S _ C O N F _ K E Y 1 /R S 4 8 5 , during reset or idle (no data). ANCILLARY SIGNALS CLKIN 9 I Clock input 24 MHz or 48 MHz , write (0x4F, 0x0); //Select the input clock frequency 24 MHz write (0x4E, 0x7); //Select the


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PDF XR28V382 128-BYTE 16-bit
2005 - TLK1002A

Abstract: TLK1002ARGER TLK1002ARGET TLK1002ARGETG4
Text: 70°C Small Footprint 4 mm × 4 mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in , conditioning PLL DIN input buffer stage + 2 SEL RXB + - I1 I2 2 ICLK MUX 2 2 RXB - reference voltage and bias current generation VDD ENA LBA GND VDD GND LBB , data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages , +/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB +/ RXB ­ is available at TXA


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PDF TLK1002A SLLS661 24-Lead 25Amplifiers TLK1002A TLK1002ARGER TLK1002ARGET TLK1002ARGETG4
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2001 - 4k23

Abstract: RXB 24 AK2048D REF25 code lock circuit CMOS 2MCMI
Text: input RXA(33) EQL. REF25(31) RXB (29) 1:1CT C0 VDD VSS VDD RVSS(42) TVSS( 24 , CLOCK RECOVER RXB LOS RDATA RCRV RCLK RESET VREF RST REF25 LOCK LOCK , NC 5 29 RXB NC 6 28 NC NC 7 27 NC NC 8 26 TXA TDATA 9 25 TVDD TCLK 10 24 TVSS TCRV 11 23 TXB (TOP VIEW) 12 14 , 4k 23 TXB O Analog 15pF *1) 24 TVSS - 25 TVDD - 26 TXA O


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PDF AK2048] AK2048D 048Mbps 400mW 44pin REF25 MS0073-E-00 AK2048D 4k23 RXB 24 REF25 code lock circuit CMOS 2MCMI
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
2013 - Not Available

Abstract: No abstract text available
Text: 27 26 25 GND 1 24 RXB LAD3 2 23 DTRB#/PS_2E0_IRQB LAD2 3 22 , modified by the software. See Table 1 ’UART Power On Configuration’. RXB 24 I UART Channel , F IF O T X B / P S _ 2 F 8 _ IR Q B R X F IF O W D TO U T#/ PS_W D T RXB R T S B # /P , during reset or idle (no data). ANCILLARY SIGNALS CLKIN 9 I Clock input 24 MHz or 48 MHz , write (0x4F, 0x0); //Select the input clock frequency 24 MHz write (0x4E, 0x7); //Select the


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PDF XR28V382 128-BYTE 16-bit
1996 - MH89793

Abstract: MT8979 MT9041 MT9079 PCM30 RJ48C RZA 18 RJ48
Text: RxA TZD2 TZC1 E2o TZD1 TZA1 F0i C4i 26 21 VSS LOSP 24 13 TLA RxB , Driver 6dB TLA Pad TLB LOS LOSP RxP Line RxA RxB Receiver Receive Isolation , TZB2 TZD1 TZC1 TZA1 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RZB RZA RxD LOS VSS RxA RxB E2o VDD LOSP RxP E2oP TXB , centre of RxD. A logic high selects E2o with a rising edge in the centre of RxD. 18 RxP RxA/ RxB


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PDF MH89793 2048kbit/s MT8979, MT9079 MH89793 MT8979 MT9041 PCM30 RJ48C RZA 18 RJ48
2005 - Not Available

Abstract: No abstract text available
Text: mm 24 -Lead QFN Package APPLICATIONS · · Resynchronization in Both Directions for 1.25 Gbps Links , 2 input buffer stage + - RXB + RXB - reference voltage and bias current generation VDD GND , Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA­ or RXB +/ RXB ­ respectively. The input stages provide on-chip differential 100- termination. The outputs of the , output ports TXB+/TXB­ and TXA+/TXA­. If LBB is pulled low, the retimed input data signal applied to RXB


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PDF TLK1002A SLLS661 24-Lead
Supplyframe Tracking Pixel