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1998 - Not Available

Abstract: No abstract text available
Text: /V/RTP01 P50/TA0OUT /W/ RTP00 P47 P46 P45 P44 P43 P42/1 P41/RDY 1 24 23 22 21 , / RTP00 P47 P46 P45 P44 P43 P42/1 P41/RDY 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85


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PDF M37753M8C-XXXFP/HP 3M37753M8C-XXXFP/HP P9P11 P10/A8/D8P17/A15/D15 P10/A8P1 7/A15 P20/A16/D0P23/A19/D3 P20/A16P23/A19 P24/A20/D4 P27/A23/D7
2010 - A5268

Abstract: minicube2 circuit schematic 16845 70F3828 uPD70F3826 TOA-B10 saturation instructions PD70F3826
Text: /SCKF0/TIAA40/TOAA40/RTP02 P41/SOF0/RXDC3/SCL01/RTP01 P40/SIF0/TXDC3/SDA01/ RTP00 P37/RXDC2/SCL02 , /SDA01/ RTP00 P76/ANI6 58 51 P75/ANI5 59 P41/SOF0/RXDC3/SCL01/RTP01 P74/ANI4 60 52 , /SCL02(/CRXD0Note3) P36/TXDC2/SDA02(/CTXD0Note3) P40/SIF0/TXDC3/SDA01/ RTP00 P41/SOF0/RXDC3/SCL01 , P42/SCKF0/TIAA40/TOAA40/RTP02 P41/SOF0/RXDC3/SCL01/RTP01 P40/SIF0/TXDC3/SDA01/ RTP00 PDL7 PDL6 P37 , Output RTCDIV: RTP00 to RTP05: Real-time Output Port R01DS0029EJ0001 Rev.0.01 Sep 30, 2010


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PDF PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, R01DS0029EJ0001 70F3832, 70F3833, 70F3834, A5268 minicube2 circuit schematic 16845 70F3828 uPD70F3826 TOA-B10 saturation instructions PD70F3826
2005 - TI031

Abstract: uPD70F3732GC TI020 UPD70F3732GC-8EA NEC Electronics uPD Series UPD70F3732 tm03 TI021
Text: /TI010/TO01 P36 P37 EVSS EVDD P38/SDA0 P39/SCL0 P50/KR0/TI011/ RTP00 P51/KR1/TI50/RTP01 P52/KR2/TO50/RTP02 , / RTP00 P51/KR1/TI50/RTP01 P52/KR2/TO50/RTP02 P53/KR3/SIA0/RTP03 P54/KR4/SOA0/RTP04 P55/KR5/SCKA0/RTP05 , as N-ch open-drain output in 1-bit units. TI011/ RTP00 /KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03 , KR2 KR3 KR4 KR5 KR6 KR7 NMI RD REGC RESET RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RXD0 RXD1 RXD2 SCK00 , /A13 P914/A14 P915/A15 P31/RXD0/TO03 P50/TI011/ RTP00 P51/TI50/RTP01 P52/TO50/RTP02 P53/SIA0/RTP03 P54


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PDF V850ES/KG2 32-BIT V850ES/KG2 V850ES 20MHz PD70F3731 TI031 uPD70F3732GC TI020 UPD70F3732GC-8EA NEC Electronics uPD Series UPD70F3732 tm03 TI021
2010 - 64pinLQFP

Abstract: PD70F3806 FLMD01 PD70F3793 64pinFBGA PD70F3804K8-5B4-AX PD70F3808 TOAB10 512K-256K nec 6b4
Text: P50/TIQ01/KR0/TOQ01/ RTP00 1 11 1. 2. 12 13 14 15 16 17 18 19 20 , P42/SCKB0 P90/KR6/TXDA1/SDA02 P91/KR7/RXDA1/SCL02 P50/TIQ01/KR0/TOQ01/ RTP00 24 P41/SOB0 , /SCKB0 P90/KR6/TXDA1/SDA02 P50/TIQ01/KR0/TOQ01/ RTP00 P91/KR7/RXDA1/SCL02 P51/TIQ02/KR1/TOQ02 , /INTP0/ADTRG P910/SIB3 P93/TIP40/TOP40 33 15 P50/TIQ01/KR0/TOQ01/ RTP00 34 14 P911 , P03/INTP02/ADTRG/EXCLK P41/SOF0/RXDC3/SCL01/RTP01 73 28 3 P40/SIF0/TXDC3/SDA01/ RTP00


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PDF V850ES/Jx3 V850ES/Jx3-H, V850ES/Jx3-L, V850ES/Jx3-E V850ES/Jx3-H V850ES/Jx3-HUSB2 V850ES/Jx3-L V850ES/Jx3-EMAC 64pinLQFP PD70F3806 FLMD01 PD70F3793 64pinFBGA PD70F3804K8-5B4-AX PD70F3808 TOAB10 512K-256K nec 6b4
2001 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF 16-BIT
2001 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF
2007 - 70F3738

Abstract: PD70F3738 TIP20 PD70F3736 minicube2 schematic PD70F3735 PD70F3737GC-UEU-AX minicube2 circuit schematic saturation instructions TIP-40
Text: P55/SCKB2/KR5/RTP05/DMS P50/TIQ01/KR0/TOQ01/ RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P90/KR6/TXDA1 , P50/TIQ01/KR0/TOQ01/ RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2/TOQ03/RTP02/DDI P53/SIB2/TIQ00/KR3 , EVDD P38/TXDA2/SDA00 P39/RXDA2/SCL00 P50/TIQ01/KR0/TOQ01/ RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2 , : REGC: RESET: RTP00 to RTP05: SCKB0 to SCKB4: SCL00 to SCL02: SDA00 to SDA02: SIB0 to SIB4: SOB0 to SOB4 , shifter System registers General-purpose registers 32 bits × 32 Note 2 DMAC RTP00 to RTP05 RTO


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PDF PD70F3735, 70F3736, 70F3737, 70F3738 V850ES/JF3-L, V850ES/JG3-L 32-BIT 70F3736 V850ES/JF3-L) 70F3738 PD70F3738 TIP20 PD70F3736 minicube2 schematic PD70F3735 PD70F3737GC-UEU-AX minicube2 circuit schematic saturation instructions TIP-40
2010 - Not Available

Abstract: No abstract text available
Text: P42/SCKF0/TIAA40/TOAA40/RTP02 P41/SOF0/RXDC3/SCL01/RTP01 P40/SIF0/TXDC3/SDA01/ RTP00 P37/RXDC2 , (/CRXD0Note3) P77/ANI7 57 P40/SIF0/TXDC3/SDA01/ RTP00 P76/ANI6 58 51 P75/ANI5 59 P41/SOF0 , /SDA01/ RTP00 P41/SOF0/RXDC3/SCL01/RTP01 P42/SCKF0/TIAA40/TOAA40/RTP02 P79/ANI9 P78/ANI8 , /SCL01/RTP01 P40/SIF0/TXDC3/SDA01/ RTP00 PDL7 PDL6 P37/RXDC2/SCL2(/CRXD0Note3) P36/TXDC2/SDA2 , : Regulator Control RESET: Reset RTC1HZ, RTCCL, Real-time Counter Clock Output RTCDIV: RTP00


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PDF PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, R01DS0029EJ0001 70F3832, 70F3833, 70F3834,
2010 - TIP20

Abstract: TIP40 tip21 PD70F3738 PD70F3842 70F3842 I2C01 L3P05 sib2 PD70F3792
Text: Output ANI0-ANI11 Analog Input RTCDIV ANO0, ANO1 Analog Output RTP00-RTP05 Real-time , TOP00-TOP50, TOP01-TOP51 16 P 6ch 16 M 1ch RTP00-RTP05 SOB0/SCL01 SIB0/SDA01 SCKB0 , P36/TXDA3 P37/RXDA3 EVSS EVDD P38/TXDA2/SDA00 P39/RXDA2/SCL00 P50/TIQ01/KR0/TOQ01/ RTP00 P51 , /TIP40/TOP40/RXDA4 L6 EVDD H2 XT2 J10 P98/A8/SOB1 L7 P50/TIQ01/KR0/TOQ01/ RTP00 H3 , V P50 TIQ01/KR0/TOQ01/ RTP00 37 L7 P51 6 TIQ02/KR1/TOQ02/RTP01 38 K7 P52


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PDF PD70F3841, 70F3842 V850ES/JG3-L) R01DS0030JJ0001 70F3842V850ES/JG3-LROM/RAM /DD/ADMA32 V850ES/JG3-L1 V850ES/JG3-L TIP20 TIP40 tip21 PD70F3738 PD70F3842 70F3842 I2C01 L3P05 sib2 PD70F3792
2003 - TI041

Abstract: TI040 gtc100 CA850 B45 P03 KG13 U16055J U15260E U15083J V850ES
Text: P50/TI011/ RTP00 /KR0 A 38 P51/TI50/RTP01/KR1 A 39 P52/TO50/RTP02/KR2 A 40 36 , A 37 P50/TI011/ RTP00 /KR0 A 38 P51/TI50/RTP01/KR1 A 39 P52/TO50/RTP02/KR2 , 31 EVDD D 32 P50/TI011/ RTP00 /KR0 A 33 P51/TI50/RTP01/KR1 A 34 P52/TO50


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PDF IE-703217-G1-EM1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 U16594JJ1V0UM001 U16594JJ1V0UM V850ES/KF1, V850ES/KG1, V850ES/KJ1NEC TI041 TI040 gtc100 CA850 B45 P03 KG13 U16055J U15260E U15083J V850ES
1996 - 6D16

Abstract: M37733S4BFP
Text: /TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/ RTP00 P47 P46 P45 P44 P43 P42/ 1 P83 , selection bit is set to "1", RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , data register 0 (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and , T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data


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PDF H-LF432-A KI-9607 6D16 M37733S4BFP
2000 - Not Available

Abstract: No abstract text available
Text: 1 RESET XT1 XT2 VDD X2 X1 VSS P100/ RTP00 P101/RTP01 P102/RTP02 P103/RTP03 P104/RTP04 , RESET: Reset CLKOUT: Clock Output RTP00 to RTP07,: Real-time Output Port CLO: Clock , Key return function A/D converter CG Watch timer Watchdog timer RTP PWM RTP00 to RTP07 , specified in 1-bit units. RTP00 RTP01 P102 RTP02 P103 RTP03 P104 RTP04 P105 , LBEN NMI RESET RTP00 to RTP07 System reset input – P100 to P107 Real-time output port


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PDF PD70F3040, 70F3040Y V850/SV1 32-/16-BIT PD70F3040 PD70F3040Y PD703039, PD703039Y, 703040Y, 703041Y,
1996 - M37733S4LHP

Abstract: No abstract text available
Text: selection bit is set to "1", RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , data register 0 (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and , T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data , output mode register to "1". RTP00 , RTP01, RTP02, and RTP03 are applied pulse width modulation by timer


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PDF H-LF434-A KI-9607 M37733S4LHP
2005 - TI041

Abstract: TI051 TI040 P614 RTP14 uPD70F3734 UPD70F3734GJ-UEN-A p615 csi02 tm03
Text: . P50/TI011/ RTP00 /KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2/DDINote 4 P53/SIA0/RTP03/KR3/DDONote 4 P54 , / RTP00 /KR0 TI50/RTP01/KR1 TO50/RTP02/KR2/DDI Note 3 SIA0/RTP03/KR3/DDO Note 3 SOA0/RTP04/KR4 , RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RXD0 RXD1 87 88 18 19 20 21 74 , /DRST P06 P913/A13 P914/A14 P915/A15 P31/RXD0/TO03 P50/TI011/ RTP00 P51/TI50/RTP01 P52/TO50/RTP02/DDI , / RTP00 /KR0 Capture trigger input/external event input for TM02 P92/A2/TO02 Capture trigger input for


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PDF V850ES/KJ2 32-BIT V850ES/KJ2 V850ES 20MHz PD70F3733 TI041 TI051 TI040 P614 RTP14 uPD70F3734 UPD70F3734GJ-UEN-A p615 csi02 tm03
Not Available

Abstract: No abstract text available
Text: 63 64 AVREF0 AVSS P40/SIF0/TXDC3/SDA01/ RTP00 P41/SOF0/RXDC3/SCL01/RTP01 P42/SCKF0/TIAA40 , P40/SIF0/TXDC3/SDA01/ RTP00 P41/SOF0/RXDC3/SCL01RTP01 P42/SCKF0/TIAA40/TOAA40/RTP02 P43/SIE0/TXDC4 , : PDL0 to PDL15: RD: REGC: RESET: RTC1HZ, RTCCL, RTCDIV: RTP00 to RTP07: Address Bus Address , TOT00, TOT01 16-bit timer/counter T : 1 ch Ports A/D converter RTC1HZ RTCCL RTCDIV RTP00 , , TOT01 16-bit timer/counter T : 1 ch Ports A/D converter RTC1HZ RTCCL RTCDIV RTP00 to


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PDF PD70F3778 70F3779 70F3780 70F3781 70F3782, 70F3783 70F3784 70F3785 70F3786 V850ES/JH3-E,
nec p181

Abstract: NEC 10F p31 NEC 10F p05 P190 v850 port sampling P181 Japan uPD703039 P150 uPD70F3040 uPD70F3040Y
Text: /VSOUT P166/HSOUT0 P167/HSOUT1 VPPNote 1 RESET XT1 XT2 VDD X2 X1 VSS P100/ RTP00 P101/RTP01 , : Read BVSS: Bus Interface Ground RESET: Reset CLKOUT: Clock Output RTP00 to RTP07 , Watchdog timer RTP PWM RTP00 to RTP07, RTP10 to RTP17 RTPTRG0, RTPTRG1 Notes 1. 256 KB (Flash , specified in 1-bit units. RTP00 RTP01 P102 RTP02 P103 RTP03 P104 RTP04 P105 , Yes LBEN NMI RESET RTP00 to RTP07 System reset input ­ P100 to P107 Real-time output


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PDF PD70F3040, 70F3040Y V850/SV1 32-/16-BIT PD70F3040 PD70F3040Y PD703039, PD703039Y, 703040Y, 703041Y, nec p181 NEC 10F p31 NEC 10F p05 P190 v850 port sampling P181 Japan uPD703039 P150 uPD70F3040 uPD70F3040Y
1996 - M37733S4BFP

Abstract: 80P6N
Text: /TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/ RTP00 P47 P46 P45 P44 P43 P42/ 1 P83 , , RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , RTP01, RTP02, and RTP03 are used , (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and RTP03 is output to the , Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data register 0


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PDF M37733S4BFP 16-BIT M37733S4BFP H-LF432-A KI-9607 80P6N
1996 - M37733S4LHP

Abstract: No abstract text available
Text: , RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , RTP01, RTP02, and RTP03 are used , (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and RTP03 is output to the , Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data register 0 , to "1". RTP00 , RTP01, RTP02, and RTP03 are applied pulse width modulation by timer A1 by setting


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PDF M37733S4LHP 16-BIT q10-bit q12-bit 80-pin 80P6D-A M37733S4LHP H-LF434-A KI-9607
1996 - M37733S4BFP

Abstract: No abstract text available
Text: /TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/ RTP00 P47 P46 P45 P44 P43 P42/ 1 P83 , selection bit is set to "1", RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , data register 0 (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and , T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data


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PDF H-LF432-A KI-9607 M37733S4BFP
1996 - M37733S4BFP

Abstract: 8016 nec
Text: /TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/ RTP00 P47 P46 P45 P44 P43 P42/ 1 P83 , selection bit is set to "1", RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , data register 0 (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and , T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data


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PDF H-LF432-A KI-9607 M37733S4BFP 8016 nec
S-80129ANMC-JCOxG

Abstract: tip21 TOP20 P913 upd70f3738gc-ueu-ax P911 P910 P711 TOP202 TIP40
Text: /TOP11 P36 P37 EVSS_1 EVDD_1 P38/TXDA2/SDA00 P39/RXDA2/SCL00 P50/TIQ01/KR0/TOQ01/ RTP00 P51/TIQ02


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PDF CSTCR5M00G53x PDL10 PDL12 PDL14 LC-22-G-RED TSM-108-01-L-DH 10Kohm LC-22-G-BLACK S-80129ANMC-JCOxG S-80129ANMC-JCOxG tip21 TOP20 P913 upd70f3738gc-ueu-ax P911 P910 P711 TOP202 TIP40
1996 - M37735S4BFP

Abstract: No abstract text available
Text: /RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT / RTP00 P47 P46 P45 P44 P43 P42/ 1 P83/TXD0 , "1", RTP1 0, RTP11, RTP12 , and RTP13, and RTP00 , RTP01, RTP02, and RTP03 are used as pulse output ports , ) corresponding to RTP00 , RTP01, RTP02 , and RTP03 is output to the ports each time the counter of timer A0 , ) D8 Data bus (odd) D T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 , A3 (bit 5) of the waveform output mode register to "1". RTP00 , RTP01, RTP02, and RTP03 are applied


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PDF H-LF426-A KI-9606 M37735S4BFP
1996 - M37733S4LHP

Abstract: No abstract text available
Text: selection bit is set to "1", RTP00 , RTP0 1, RTP0 2, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00 , data register 0 (low-order four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02, and , T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 (P54) Pulse output data , output mode register to "1". RTP00 , RTP01, RTP02, and RTP03 are applied pulse width modulation by timer


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PDF H-LF434-A KI-9607 M37733S4LHP
1996 - rom 6216

Abstract: M37735S4BFP FFFF16
Text: /RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT / RTP00 P47 P46 P45 P44 P43 P42/ 1 P83/TXD0 , "1", RTP1 0, RTP11, RTP12 , and RTP13, and RTP00 , RTP01, RTP02, and RTP03 are used as pulse output ports , ) corresponding to RTP00 , RTP01, RTP02 , and RTP03 is output to the ports each time the counter of timer A0 , ) D8 Data bus (odd) D T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 , A3 (bit 5) of the waveform output mode register to "1". RTP00 , RTP01, RTP02, and RTP03 are applied


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PDF H-LF426-A KI-9606 rom 6216 M37735S4BFP FFFF16
1996 - M37735S4BFP

Abstract: No abstract text available
Text: /RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT / RTP00 P47 P46 P45 P44 P43 P42/ 1 P83/TXD0 , "1", RTP1 0, RTP11, RTP12 , and RTP13, and RTP00 , RTP01, RTP02, and RTP03 are used as pulse output ports , ) corresponding to RTP00 , RTP01, RTP02 , and RTP03 is output to the ports each time the counter of timer A0 , ) D8 Data bus (odd) D T Q D2 Data bus (even) D3 D Q RTP00 (P50) T RTP10 , A3 (bit 5) of the waveform output mode register to "1". RTP00 , RTP01, RTP02, and RTP03 are applied


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PDF H-LF426-A KI-9606 M37735S4BFP
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