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lc3664* sanyo

Abstract: N191 N3216B 321S IC LM 317 DIP28 lc3664r sanyo lc3664r-12
Text: ^ *»«> — — ^. SKS"8192'-KX8f.y h SRAM LC3664RS, RSL -10/12/15 // IttE LC3664R,RL,RM(RML,RS, RSL - 10 , , RSL - J 0 LC3664R,RL,RM,RML,RS, RSL -12 LCaeeiR.RL.RM^RML.RS.RSL-lS IC3664R,RM,RS LC3664RL,RML, RSL ÖV , : MFP28 HJBOI 3133 [LC3G64RS, RSL ] (unil: mm) 26 rr 'cj WU'LJ1 uuuuuuutj yir 2.54 as T.2 SANYO , .3216-1/7 LC3664R,RL,RM,RML,RS, RSL mm í - H en CE2 wr I/O "J — K +}■>f ^ ^ L H L H r-ïfot , AH M ot Si aio S cëï ¡s r/07 Tg 1/06 Ï5] 1/05 Ts] 1/04 (CP view 'W ■J - K é flf MMMÀÃ


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PDF N3216B 3216B 3216At LC3664RS RSL-10/12/15 LC3664R 12/15U8192X8 RSL-12 lc3664* sanyo N191 N3216B 321S IC LM 317 DIP28 sanyo lc3664r-12
SIEMENS WF 470

Abstract: No abstract text available
Text: ; programmable by an external resistor connected from pin RSL to VC cTransmitter The TLE 6255 GG contains a , 9 Vcc RSL 10 ^batt Battery Supply Voltage; external blocking capacitor necessary (see , Configuration (top view) o GND TxD 14 CANH 11 LOAD 10 Kiati 9 RSL 8 , Converter RSL Time Out Circuit TxD 12 CANH Mode-Logic M1 Mode L FeedbackLoop , batt - 0 .3 40 V CAN bus input/output voltage ^C N AH -2 8 28 V - Load


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PDF 067006-A9352 P-DSO-14 0S35bQ5 P-DSO-14-4 S235b05 SIEMENS WF 470
rosan

Abstract: No abstract text available
Text: 610 LCFM A33 Gnd B33 Gnd AH SVdd BS6 SVdd A79 RCTM B79 NC Al 1 Gnd 611 Gnd A34 LSCK B34 LCMD A57 SWP , , B90 A92, B92 LDQA8 to 0 I/O RSL Data bus A. A 9-pin bus carrying a byte of read or write data between the Channel and the RDRAM. A2, B2, A4, 84, A6, B6, A8, B8.A10 LCFM 1 RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. BIO LCFMN 1 RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. B12 VREF


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PDF 432-WORD 18-BIT 18-bit TC59RM718MB 32M-wordXl8 600MHz 16cycles) 32M-wordX18 711MHz rosan
Not Available

Abstract: No abstract text available
Text: to 0 I/O RSL Data bus A. A 9-pin bus carrying a byte of read or write data between the Channel and the RDRAM. LCFM 1 RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. LCFMN 1 VREF LCTMN 1 RSL Logic threshold reference voltage for RSL signals. Clock to master. Interface clock used for


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PDF 728-WORD 18-BIT 18-bit TC59RM818MB 256MB 184pin
Not Available

Abstract: No abstract text available
Text: = 191K, C3 = 6800pF 461 512 563 Hz High Frequency 2 ÍH 2 R3=191K, C3 = 6800pF , relation tH = 1/(1.504 R j - C 3 ) voltage re­ i mains constant independent of RSL . Pin 2 of the KA2411 allows connection of an external resistor RSL , which is used to program the slope of the supply current , plot with RSl < 6.8kQ and shows an increase in the current drawn up to the initiation voltage VS|. , RSL above 6.8kfi initiation current decreases but is unchanged again after triggering. APPLICATION


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PDF KA2410 KA2410/KA2411 KA2410) KA2411 00307bS KA2410
Not Available

Abstract: No abstract text available
Text: •c -20to-(-70 —5 5 to M 2 5 t o 0.8t 40mmD ■ELECTR IC AL CHARACTERISTICS •H , - 606 Hz - 752 Hz min. typ. m ax. Unit •H A 16804P S Item , Isus Vs = 15V Output “H ” Voltage V OH Vs = 24 V, Io h = O utput “L” Voltage , ith R s L = 2 0 k f i O utput “H ” Voltage VoH V s=36V , I oh = —10mA O utput â , \ VHA16802PS/ RSL (HA16805PS) c Output 7 3 Low Freq. Time Constant □ 6 4 5 Vcc


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PDF HA16802PS, HA16804PS, HA16805PS/F HA16802PS/HA16804PS/ HA16805PS 16805PS/F HA16802PS
toshiba a75

Abstract: ejdalf
Text: A86, B86, A88, B88, A90, 890 A92, B92 LDQA8 to 0 I/O RSL Data bus A. A 9-pin bus carrying a byte , RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. LCFMN RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity._ 812 VREF Logic threshold reference voltage for RSL signals. A51.B51 LCTMN RSL Clock to master. Interface clock used for taransmitting RSL signals to the Channel. Negative polarity


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PDF 864-WORD 18-BIT 18-bit TC59RM718MB 64M-wordXl8 600MHz 16cycles) 711MHz toshiba a75 ejdalf
Not Available

Abstract: No abstract text available
Text: 16 or 18 bits. The use of Rambus Signaling Level ( RSL ) technology permits 600 MHz, 711 MHz or 800 , ‘S1designator instead of ‘R 1followed by ‘h yphen(-)1indicates low power modules. Table 1: Part Number by , I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. LCFMN B12 I RSL Clock from master. Interface clock used for receiving RSL , , A22, B22, A24 I RSL Column bus. 5-bit bus containing control and address infor­ mation for


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PDF KMMR16R84 KMMR18R84 4/6/8/12/16d 128Mb 144Mb 128Mb/144Mb
MIG toshiba

Abstract: ABB B45 THMR1E16-6 THMR1E16-7 B75 ABB hiab 837 B34 toshiba mig
Text: , B90 A92, B92 LDQA8 to 0 I/O RSL Data bus A. A 9-pin bus carrying a byte of read or write data between the Channel and the RDRAM. A2, B2,A4, B4, A6, B6, A8, B8.A10 LCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. B10 LCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. B12 VREF Logic threshold reference voltage for RSL signals. A51.B51 LCTMN I RSL Clock to master. Interface clock


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PDF THMR1E16-6/-7/-8 128M-word 600MHz 711MHz 800MHz 16cydes) -16CSP MIG toshiba ABB B45 THMR1E16-6 THMR1E16-7 B75 ABB hiab 837 B34 toshiba mig
4419 power ic

Abstract: EN4419 4419 stk733c STK733 RSL AH Chopper Regulator FET scrrr
Text: 0.1/uF /50V l,uF/50V lOOOpF LI 200^H (HP-054/TOKIN) Rsl 0.05Ì1 ri ion Note) Since the 5 pin is , 1000 Pd-I0 Vin(DC)=35V LI=200/ AH (0.05£ RSi=0.05Q i) _ < 4 , €¢ Current detection resistor Rsl is tied in with both pin 3 and pin 4 (protects resistor detection at , Resistor Rsl (1) Due to the large current flow, attention should be paid to consumption. (2) One should


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PDF EN4419 STK733C STK733C 4419 power ic EN4419 4419 STK733 RSL AH Chopper Regulator FET scrrr
1999 - DSASW00264742

Abstract: NiH2 battery 1N5816 1N6392 1N5816 diode
Text: , with cells of 50 to 100 Ah already in orbit, and cells of 250 to 400 Ah now in development and , The HPM cell bypass device has become the standard for NiH2 cells with capacity ranges up to 100 Ah , than 100 Ah , where there is insufficient thermal mass in the satellite to dissipate the heat generated by the Schottky bypass. For example, for a 250 Ah cell, even a low VFSchottky would dissipate over 100 watts. THERMALLY ACTIVATED CELL BYPASS The bypass for high capacity (>100 Ah ) NiH2 cells


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PDF 1998/Winter Typically15. ESPC-98. DSASW00264742 NiH2 battery 1N5816 1N6392 1N5816 diode
hfdw

Abstract: No abstract text available
Text: Logic ( RSL ) technology permits 600MHz transfer rates while using conventional system and board design , ) □ Rambus Signaling Level ( RSL ) interface Part Numbers □ Synchronous, concurrent protocol , the address field, command field, and other control fields. These are RSL signals3. CLK (RXCLK) I Receive clock. All input packets are aligned to this clock. This is an RSL signal.a CLK (TXCLK) I Transmit clock DOUT packets are aligned with this clock. This is an RSL signal.a VREF


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PDF 16/18Mbit 64/72Mbit 16/18/64/72-M 600MHz hfdw
Delphi PA66 gf14

Abstract: No abstract text available
Text: 24 23 22 21 19 20 17 IB 16 15 14 12 13 V 10 11 7 8 MISSING SYMBOLS SYMBOL DEFINITION A DIMENSION WITHOUT AN INSPECTION REPORT SYMBOL ( ) DOES NOT REQUIRE INSPECTION. IT MAY BE CONTROLLED ON THE INDIVIDUAL COMPONENT DRAWING. M ûlûlüllûflûflû ünü cun47.8 H ■H 54X 8. 1 12JN03 20 - 15MY06 R REVISION HISTORY , 02 - - ALL PARTS - CLARIFIED DIM 7 REQUIREMENTS 242088 AKJ AKJ RSL 03 - - 55


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PDF cun47 12JN03 15MY06 Delphi PA66 gf14
modu amp

Abstract: HV100 T5200 AMP MODU .25 C2153 Nr 6200 AMP MODU 2 CONT AMP
Text: . 54 m rsl IMM liii 1-1-r LD oj CN-n X 2. 54 ±0.08 e-o-o—o I I e-e— Œ -4- - è- ^ , SEE NOTES PARTNUHBER AMP-HOLLAND B.V. ' »-H *r togfibo«ch, Th# Wthrlqnda. THIS BMW INS IO UNE USL


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PDF C-215309 modu amp HV100 T5200 AMP MODU .25 C2153 Nr 6200 AMP MODU 2 CONT AMP
Not Available

Abstract: No abstract text available
Text: š i i Rx+ r L Rx- j- RECEIVER RxC RSL I ENABLE RxE PO+ i RxD i CLK Tx , s s m DO+ [ T 3?| RSL DO- | T 38] JAB CLK ( T 3 7 ] XMT LPBK Q5 3&j CLS G N , RSL NC JAB CLK XMT LPBK CLS NC RCV Rx+ RXD Rx- RxC NC RxE , interfaces. This pin has an internal pulldown resistor to GN D. RSL RPOL This pin must be grounded at all times. Receive squelch level select input. Pin has internal pullup resistor to VCC. RSL =


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PDF ML2652/ML2653 10Base-T ML2652, 10Base-T) ML2652 CA95131
2002 - A101

Abstract: A102
Text: extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level ( RSL , Description Signal Module connector pads I/O Type CFM_THRU_L A14 I RSL CFM_THRU_R B54 I RSL CFMN_THRU_L A16 I RSL CFMN_THRU_R B52 I RSL Description , , A22, B22, I A24 RSL COL4_THRU_R. COL0_THRU_R B48, A48, B46, A46, I B44 RSL CTM_THRU_L B14 I RSL CTM_THRU_R A54 I RSL CTMN_THRU_L B12 I RSL


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PDF 256MB 32-bit EBR25UC8ABKD 1066MHz 800MHz 925mm E0309E11 A101 A102
2002 - Not Available

Abstract: No abstract text available
Text: Level ( RSL ) technology permits the use of conventional system and board design technologies. The 32 , Description Signal CFM_THRU_L Module connector pads A14 I/O I Type RSL Description Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the , clock used for receiving RSL signals from the controller. Positive polarity. Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the


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PDF 512MB 32-bit EBR51UC8ABKD EBR51UC8ABKD 288Mb 1066MHz 800MH M01E0107
1999 - siemens a55

Abstract: siemens A70 marking b28 siemens a57 siemens b38
Text: Rambus Signaling Level ( RSL ) technology permits 600MHz to 800MHz transfer rates while using conventional , , B46, A47, B47, A48, B48, A49, B49, A50, B50 B83 B81 I I RSL RSL RSL I I I I I I RSL RSL VCMOS RSL RSL RSL I/O Type Description Ground reference for RDRAM core and interface. 72 PCB connector pads. LCFM , master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial


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PDF HYR16xx30/HYR18xx20G 128Mb/ 144Mb 600MHz 800MHz 128MB, HYR16xx30G/HYR18xx20G siemens a55 siemens A70 marking b28 siemens a57 siemens b38
2003 - rdram

Abstract: RDRAM 32 Bit RIMM4800 Module marking A97 A101 A102 A103 A104 B100 B101 B102
Text: 16M words by 16 or 18 bits. The use of Rambus Signaling Level ( RSL ) technology permits the use of , : Module Connector Pad Description Signal Module Connector Pads CFM_THRU_L A14 RSL Clock From Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. RSL Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Negative


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PDF 256/288Mb RIMM4800 256Mb/288Mb 1200MHz DL0164 DL0164 rdram RDRAM 32 Bit RIMM4800 Module marking A97 A101 A102 A103 A104 B100 B101 B102
2002 - Not Available

Abstract: No abstract text available
Text: of Rambus Signaling Level ( RSL ) technology permits the use of conventional system and board design , I RSL CFM_THRU_R B54 I RSL CFMN_THRU_L A16 I RSL CFMN_THRU_R B52 I RSL CMD_THRU_L B2 I VCMOS CMD_THRU_R A73 I VCMOS COL4_THRU_L. COL0_THRU_L A20, B20, A22, B22, I A24 RSL COL4_THRU_R. COL0_THRU_R B48, A48, B46, A46, I B44 RSL CTM_THRU_L B14 I RSL CTM_THRU_R A54 I RSL CTMN_THRU_L B12 I


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PDF 128MB 32-bit MC-4R128FKK8K 800MHz 925mm M01E0107 E0252N10
2002 - Not Available

Abstract: No abstract text available
Text: Level ( RSL ) technology permits the use of conventional system and board design technologies. The 32 , Description Signal CFM_THRU_L Module connector pads A14 I/O I Type RSL Description Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the , clock used for receiving RSL signals from the controller. Positive polarity. Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the


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PDF 256MB 32-bit EBR25UC8ABKD EBR25UC8ABKD 288Mb 1066MHz 800MHz M01E0107
2002 - Not Available

Abstract: No abstract text available
Text: Level ( RSL ) technology permits the use of conventional system and board design technologies. The 32 , Signal CFM_THRU_L Module connector pads A14 I/O I Type RSL Description Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller , used for receiving RSL signals from the controller. Positive polarity. Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller


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PDF 128MB 32-bit EBR12UC8ABKD EBR12UC8ABKD 288Mb 1066MHz 800MHz E0314E10
2002 - A101

Abstract: A102 A103 MC-4R512FKK8K MC-4R512FKK8K-840 PD488588FF
Text: bits. The use of Rambus Signaling Level ( RSL ) technology permits the use of conventional system and , Type CFM_THRU_L A14 I RSL CFM_THRU_R B54 I RSL CFMN_THRU_L A16 I RSL CFMN_THRU_R B52 I RSL Description EO B2 I VCMOS CMD_THRU_R A73 I VCMOS COL4_THRU_L. COL0_THRU_L A20, B20, A22, B22, I A24 RSL COL4_THRU_R. COL0_THRU_R B48, A48, B46, A46, I B44 RSL CTM_THRU_L B14 I RSL CTM_THRU_R A54 I RSL


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PDF 512MB 32-bit MC-4R512FKK8K 800MHz 925mm E0254N11 A101 A102 A103 MC-4R512FKK8K MC-4R512FKK8K-840 PD488588FF
2002 - Not Available

Abstract: No abstract text available
Text: of Rambus Signaling Level ( RSL ) technology permits the use of conventional system and board design , I RSL CFM_THRU_R B54 I RSL CFMN_THRU_L A16 I RSL CFMN_THRU_R B52 I RSL CMD_THRU_L B2 I VCMOS CMD_THRU_R A73 I VCMOS COL4_THRU_L. COL0_THRU_L A20, B20, A22, B22, I A24 RSL COL4_THRU_R. COL0_THRU_R B48, A48, B46, A46, I B44 RSL CTM_THRU_L B14 I RSL CTM_THRU_R A54 I RSL CTMN_THRU_L B12 I


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PDF 256MB 32-bit MC-4R256FKK6K 800MHz 925mm M01E0107 E0268N10
2002 - Not Available

Abstract: No abstract text available
Text: high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level ( RSL ) technology , , A41, B41 RSL RSL VCMOS RSL A18, B18, A20, B20, A22 I I RSL RSL RSL RSL RSL I A2, B2 , ­ RSL RSL VCMOS RSL RSL RSL B63, A63, B61, A61, B59 I I I Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command used to read


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PDF 128MB EBR12EC8ABSA EBR12EC8ABSA 1066MHz 800MHz E0321E10 M01E0107
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