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RRU 3939 Datasheets Context Search

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3tc48

Abstract: 88CS42N
Text: instruction: 181 kinds, 842 instructions In te rru p t sources 35 (6 external, 29 internal) In p u t/O u tp , al by an in te rru p t O p e ratin g voltage: 4 .5 to 5.5 V ( a tS to 20 MHz) 88CS42-2 , utpu t mode bitwise. · W h en using as external in te rru p t, tim e r/c o u n te r, or position signal , o utpu t High-speed PW M1 o u tp u t External in te rru p t inp ut 0 External in te rru p t 1 input External in te rru p t 2 in p u t or tim er/co un ter 1 input Tim er/counter 5 input or divider o utput Tim


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PDF TMP88CS42 TMP88CS42N/F TMP88CS42 TLCS-870/X 10-bit TMP88CS42F TMP88CS42N P-SDIP64-750-1 TMP88PS42N P-QFP64-1420-1 3tc48 88CS42N
Not Available

Abstract: No abstract text available
Text: rru p t request pin 0: In te rru p t request pin w ith p ro g ra m m ab le level/rising ed g e , : O u tp u t pin fo r t im e r 0 or 1 /T 0 1 P72 In p u t/o u tp u t In te rru p t request pin 1: Rising-edge in te rru p t request pin In p u t 1 In p u t/o u tp u t In te rru p t request pin 2: Rising-edge in te rru p t request pin _J Port 73: I/O p o rt / TI4 In p u t T , / CTSO Port 75: I/O p o rt In p u t/o u tp u t In te rru p t request pin 4: Rising-edge in te


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PDF TMP95CS64/TMP95C265 16-Bit TMP95CS64F /TMP95C265F TMP95CS64/265 TMP95CS64 TMP95C265 100-pin
RRU 11

Abstract: No abstract text available
Text: single-chip m icrocom puter TLCS-870/X series m icrocom puter ♦ in te rru p t sources: 23 (5 external, 18 , u tp u t (PDO) mode ♦ T im e base tim e r (in te rru p t frequency: 1 to 16384 Hz) ♦ W a tc h , €¢ IDLE mode: Stops CPU b u t continues o peration o f peripheral hardw are. Released by in te rru p t , , External interrupt 3 input external in te rru p t in p u t, or tim e r/ counter input, set output , circuit, and in te rru p t control circuit. This chapter describes th e CPU core, program memory, data m


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PDF TMP88CH47 TMP88CH47N, TMP88CH47F TMP88CH47N 10-bit TMP88CH47N P-SDIP42-600-1 TMP88PH47N P-QFP-1414-0 RRU 11
p82c59a

Abstract: P82C59 icw1
Text: P82C59AP-2/AM -2 (h erein a fter referred to as TM P82C59A) is a program m able in te rru p t controller. It h an d les up to eig h t vectored p rio rity in te rru p ts for th e M PU. It is cascadable for up to 64 vectored p rio rity in te rru p ts w ith o u t ad d itio n al circuitry. FEA TU RES · · · · · · E ig h t Level P rio rity C ontroller. E xpandable to 64 Level. In te rru p t Modes, In te rru p t M , puter In te rru p t Sequence. TTL Com patible. 2. PIN CONNECTIONS (TOP VIEW ) TMP82C59AP


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PDF TMP82C59AP-2/TMP82C59AM-2 TMP82C59A P82C59AP-2/AM P82C59A) MPU85-195 DIP28-P-600 MPU85-196 OP28-P-45Q p82c59a P82C59 icw1
RRU 11

Abstract: No abstract text available
Text: ! Semiconductor OPERATION GENERAL The U S C 6 8 H C 9 0 8 in te rfa c e s 7 channels o f in te rru p t d ire c , ito rs all the sp e cifie d in te rru p t channels. W hen an in te rru p t is received th a t has a higher p rio rity th e n any cu rre n tly pending or in service an in te rru p t request is tra n s m itte d to th e processor. W hen th e in te rru p t is a ckn o w le d g e d th e PIC a u to m a tica lly responds by tra n s m ittin g th e in te rru p t v e c to r num ber to the processor. The U S C 6 8 H C 9 0


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PDF USC68HC908 68HC908 RRU 11
RBS 3116

Abstract: jrs 31-30 A
Text: 1-byte jum p /subroutine -call (Short relative jum p / Vector ca 11 in te rru p t sources (External : 3, In te rn a l: 8 ) · All sources have independent latches each, and nested in te rru p t control is available. · Edge-selectable external in te rru p ts w ith noise reject · High-speed task , a tc h d o g Timer · In te rru p t source / reset o u tp u t (program m able) O n-screen display , clock controller, an in te rru p t controller, and a w atchdog tim er. This section provides a


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PDF TMP87CC31/H31 TMP87CC31N, TMP87CH31N 87CC31/H31 TMP87CC31N TMP87CH31N SDIP42-P-600-1 TMP87PM36N TLCS-870 RBS 3116 jrs 31-30 A
Not Available

Abstract: No abstract text available
Text: icrocom puter TLCS-870/X series m icrocom puter ♦ in te rru p t sources: 24 (6 external, 18 Internal , e r (in te rru p t frequency: 1 to 16384 Hz) ♦ W a tc h d o g tim e r ♦ Divider o u tp u t fu , :Stops CPU b u t continues o pe ra tion o f p eripheral h ardw are. Released by in te rru p t (restarts , (Input) External in te rru p t4 input or tim e r / to 1 . counter 4 input External in te rru p , . CPU Core Functions The CPU core consists o f th e CPU, system clock control circuit, and in te rru p


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PDF K48/M48 TMP88CK48N, TMP88CM48N TMP88CK48F, TMP88CM48F TMP88CM48N, TMP88CM48F, 10-bit
Not Available

Abstract: No abstract text available
Text: ro u tin e -c a ll (Short relative jum p /V e cto r call) • 14 in te rru p t sources (External : 5, In te rn a l: 9) • All sources have independent latches each, and nested in te rru p t control is available. • 3 edge-selectable external in te rru p ts w ith noise reject • High-speed task switching , T im e Base Timer (Interru pt frequency : 1 Hz to 16 kHz) ♦ W a tc h d o g Timer • In te rru p , o f a CPU, a system clock controller, an in te rru p t controller, and a w atchdog tim er. This


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PDF M38/P38/S38 TMP87CM38N/F* TMP87CP38N/F* TMP87CS38N/F* 87CM38/P38/S38 P87CM 38N/F* SDIP42-P-600-1
Not Available

Abstract: No abstract text available
Text: output: 2 ports W atchdog tim er B u s w idth / w a it controller: 3 blocks In te rru p t functions , register to 111. (Sets m ask register to in te rru p t le ve l 7.) • M A X b it of status register , determ ined by the com binations between the states of in te rru p t m ask register < IF F 2 to 0> and , €¢ Released by requesting an in te rru p t The operating released from the h a lt mode depends on the in te rru p t enabled status. W h e n the in te rru p t request le ve l set before executing the H A L


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PDF TMP93CS32 16-bit 64-pin P-QFP64-1414-0 900/L TLCS-90 16M-byte
Not Available

Abstract: No abstract text available
Text: 0 8 in te rfa ce s 7 channels o f in te rru p t d ire c tly to the 6 8 0 0 0 m icro p ro cesso r. A fte r th e PIC is program m ed it c o n tin u o u sly m on ito rs all th e sp e cifie d in te rru p t channels. W hen an in te rru p t is received th a t has a h igher p rio rity th e n any c u rre n tly pending or in service an in te rru p t req u e st is tra n s m itte d to th e processor. W hen th e in te rru p t is a c k n o w le d g e d th e PIC a u to m a tic a lly responds by tra n s m ittin g th e in


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PDF USC68HC908 68HC908
la 4620 ic to machine

Abstract: No abstract text available
Text: cto r call) 14 in te rru p t sources (External: 6 , Internal: 8 ) · All sources have independent latches each, and nested in te rru p t control is available. · 4 edge-selectable external in te rru p ts w , CPU core consists o f a CPU, a system clock controller, an in te rru p t controller, and a w atchdog , eripheral control registers P eripheral status registers System control registers In te rru p t control , rru p ts / reset (16 vectors) E n try area fo r page call in s tru c tio n s 87CH46/H47/H47L


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PDF P87C447/847/H47/84717H47 TMP87C447U, TMP87C847U, TMP87CH47U, TMP87C847LU, TMP87CH47LU 87C447/847/H47 TMP87C447U TMP87C847U TMP87CH47U la 4620 ic to machine
Not Available

Abstract: No abstract text available
Text: I/O lines Two external in te rru p t in p u t Two 8-bit program m able tim er/event c o u n te r , , PBO and PB1 can be set as in p u t pins or as external in te rru p t control pins (INTO) and (IN TI , im er Period tlNT In te rru p t Pulse W idth Note: t SYS= 1/fsYS 8 August 18, 1999 , t, an external in te rru p t, or re tu rn in g from a subroutine, th e PC m anipulates th e program , Location 004H Location 004H is reserved for th e external in ­ te rru p t service program . If th e INTO


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PDF HT49C50
FFF84

Abstract: No abstract text available
Text: f fo u r channels o f m icro D M A start \ vecto r register is set to FCH. In te rru p t v ecto r v a lu e "V " read In te rru p t request F/F clear PUSH G en eral-p u rp o se in te rru p t processing PUSH PC SR S R < IF F 2 :0 > < - Level o f accepted in te rru p t + 1 INTNEST«-INTNEST + 1 , rru p t (INTTCO to 3) L PC < r- (FFFFOOH + V) Interrupt processing program RETI , interrupts (INT1 in te rru p t processing) W h e n th e CPU accepts an in te rru p t, it sets IFF to th e p


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PDF TMP95CS54 16-Bit TMP95CS54F TMP95CS54 100-pin 900/H TLCS-90/900 FFF84
063-D

Abstract: No abstract text available
Text: c to r call) 14 in te rru p t sources (External: 5, Internal: 9) · All sources have indep en d en t latches each, and nested in te rru p t control is available. · 3 edge-selectable external in te rru p ts w , Tim er (In te rru p t frequency: 1 Hz to 16 kHz) Divider o u tp u t fu n ctio n (frequency: 1kHz to 8 kHz) W a tc h d o g Timer · In te rru p t source/reset o u tp u t (program m able) 000707EBA1 · , port, a HSO o u tp u t, a SIO in p u t / o u t p u t , tim e r/c o u n te r inp ut, or an in te rru p t


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PDF TMP87CM71/N71/P71/S71 P87CM71F, TMP87CN71 TMP87CP71 TMP87CS71F TMP87CM71/N71/P71/S71 TMP87CM71F TMP87CN71F TMP87CP71F TMP87CS71F 063-D
diode c446

Abstract: la 4620 ic to machine C03 EH
Text: /V e cto r call) 14 in te rru p t sources (External: 6 , Internal: 8 ) · All sources have independent latches each, and nested in te rru p t control is available. · 4 edge-selectable external in te rru p ts w ith noise reject · High-speed task switching by register bank changeover 5 In p u t/O u tp , (Inte rru p t frequency: 1 Hz to 16 kHz) Divider o u tp u t functio n (frequency: 1kHz to 8 kHz) W a , CPU, a system clock controller, an in te rru p t controller, and a w atchdog tim er. This section


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PDF P87C446/846/H TMP87C446N, TMP87C846N, TMP87CH46N 87C446/846/H46 TMP87C446N TMP87C846N TMP87CH46N P-SDIP42-600-1 TMP87PH46N diode c446 la 4620 ic to machine C03 EH
til 808 segment

Abstract: No abstract text available
Text: 01-22 TO SH IB A TM P87C408/808/408L/808L 10 in te rru p t sources (External: 4, Internal: 6) · All sources have indep en d en t latches each, and nested in te rru p t control is available. · , modes Time Base Timer · In te rru p t frequency types: 8 types (1 to 16384 Hz) Divider o u tp u t fu n , TM P87C408/808/408L/808L The CPU core consists o f a CPU, a system clock controlle r, an in te rru , registers Peripheral hardw are status registers System co n tro l registers In te rru p t co n tro l


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PDF P87C408/808/408L/808L TMP87C408M, TMP87C408N, TMP87C808M, TMP87C808N TMP87C408LM, TMP87C408LN, TMP87C808LM, TMP87C808LN TMP87C408/808/408I til 808 segment
Not Available

Abstract: No abstract text available
Text: ™¦ 6 in te rru p t sources (External: 2, In te rn a l: 4) A ll sources have independent latches each, and m u ltiple in te rru p t control is available. ♦ I/O p o rt (36 pins) • In p u t 2 ports , System co ntroller 2.8 In te rru p t C ontroller 2.9 Reset Circuit PERIPHERAL HARDWARE FUNCTION 3.1 , branch instruction o r a subroutine instruction has been executed or an in te rru p t has been accepted , saved; w hen an in te rru p t is accepted, th e contents o f th e program counter and flags are saved


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PDF TMP47C200B/400B TMP47C200BN, TMP47C400BN TMP47C200BF, TMP47C400BF 47C200B/400B TLCS-47 47C200A/400A.
OP12A

Abstract: No abstract text available
Text: ), 244 ¿ u $ (at 32.8 kHz) 105 basic instructions S u b ro u tin e nestin g: 15 levels max. 6 in te rru , te rru p t control is available. I/O p o rt (56 pins) · In p u t 2 ports 5 pins · O u tp u t 4 ports , ord (SPW) · Data Counter (DC) 2.5 ALU, Accum ulator 2.6 Flags 2.7 System C ontroller 2.8 In te rru p t , te rru p t has been acknow ledged, the specified valueslisted inTable2-1 are set to the PC. The PC is , fro m stack O th e rs In te rru p t acceptance RESET 0 0 0 In c re m e n te d by th e n u m b e


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PDF TMP47C1260/1660 TMP47C1260N, TMP47C1660N TMP47C1260F TMP47C1660F 47C1260/1660 47C660/860 TLCS-470 TMP47C1260N TMP47C1260F OP12A
68A21

Abstract: MC6821 PIA mc6821 mc68b21p MC6821P
Text: n trol /in te rru p t lines may be program m ed fo r one o f several con tro l m odes This allo w s , Data D irection Registers Four Individ u a lly -C o n tro lle d In te rru p t In p u t Lines; T w o , Program C o ntrolled In te rru p t and In te rru p t Disable C apability CM O S D rive C apability on Side , , tw o in te rru p t request lines, a re a d /w rite line, an enable line and a reset line. To ensu re , IRQB) - T he a ctive lo w In* te rru p t R equest lines (IR Q A and IRQB) a c t to in te rru p t the M


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PDF MC6821 68A21 MC6821 PIA mc68b21p MC6821P
Not Available

Abstract: No abstract text available
Text: p /s u b ro u tin e -c a ll (Short relative ju m p /V e c to r call) ♦ 14 in te rru p t sources , rru p t control is available. • 4 edge-selectable external in te rru p ts w ith noise reject â , (In te rru p t frequency: ♦ Divider o u tp u t fu n ctio n (frequency: 1 Hz to 16 kHz) 1kHz to 8 kHz) ♦ W a tc h d o g Timer • In te rru p t source / reset o u tp u t (program m able , rru p t in p u t 2 or T im e r/C o u n te r 1 in p u t inputs. P12 (INT2/TC1) P11 (INT1) p


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PDF TMP87CM45 TMP87CM45N 87CM45 P-SDIP64-600-1 TMP87PS39N TLCS-870 MX-38T 87CM45-120
m83c154

Abstract: m80c154 OKI EM-318 83C154 instruction MSM80C154 msm80c154v
Text: -source 2 -p rio rity level in te rru p t and m ulti-level in te rru p t available b y program m ing IP and , the external in te rru p t 0 , and as cou nt-u p co n tro l pin fo r the tim e r/c o u n te r 0. · P 3.3 ITn T I ) Used as in p u t pin fo r the external in te rru p t 1, and as cou nt-u p c o n tro l , stopped when ID LE mode is set, b u t X T A L1 -2, tim e r/cou nters 0, 1, and 2, the in te rru p t , rru p t is generated. PD mode set when this b it is set to " 1 " , CPU operations and X T A L 1 -2 are


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PDF 154/M 83C154 16-bit b724240 m83c154 m80c154 OKI EM-318 83C154 instruction MSM80C154 msm80c154v
diode E8

Abstract: No abstract text available
Text: -bit data operations · 1-byte jum p/subroutine-call (Short relative ju m p /V e c to r call) 10 in te rru p , te rru p t control is available. · 3 edge-selectable external in te rru p ts w ith noise reject · , , External trig g e r tim er, W in d o w modes T im e Base Tim er (In te rru p t frequency: 1 Hz to 15625 Hz) Divider o u tp u t fu n ctio n (frequency: 1 kHz to 8 kHz) W a tc h d o g Timer · In te rru p t source , clock co ntrolle r, an in te rru p t co ntrolle r, and a w atchdog tim er. This section provides a


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PDF C444/844 TMP87C444N, TMP87C844N 87C444/844 TMP87C444N TMP87C844N P-SDIP42-600-1 TMP87P844N TLCS-870 diode E8
16 pin 7-segment display

Abstract: TMP47C200BF
Text: u b ro u tin e nesting : 15 levels max. 6 in te rru p t sources (External: 2, Internal: 4) A ll sources have independent latches each, and m ultip le in te rru p t control is available. I/O p o rt (36 , ord (SPW) · Data C ounter (DC) 2.5 ALU, Accum ulator 2.6 Flags 2.7 System controller 2.8 In te rru p t , been executed or an in te rru p t has been accepted, the specified values listed in Table 2-1 are set , ; w hen an in te rru p t is accepted, the contents o f the program counter and flags are saved. W hen


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PDF TMP47C200B/400B TMP47C200BN, TMP47C400BN TMP47C200BF, TMP47C400BF 47C200B/400B TLCS-47 47C200A/400A. 16 pin 7-segment display TMP47C200BF
Not Available

Abstract: No abstract text available
Text: u tin e -c a ll (Short relative ju m p /V e c to rc a ll) ♦ 14 in te rru p t sources (External : 5, Internal : 9) • A ll sources have independent latches each, and nested in te rru p t control , rru p t frequency : 1 Hz to 16384 Hz ♦ W a tc h d o g Timer ♦ S e ria l bus Interface • l 2C , I E J j RESETTEST- System C ontroller In te rru p t C ontroller Program Mem ory (ROM , Function I/O (In p u t Input) p o rt.a n in te rru p t inp u t o r STOP mode release signal input


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PDF TMPA8700CH/C TMPA8700CHN/F, TMPA8700CKN/F, TMPA8700CMN/F, TMPA8700CPN/F, TMPA8700CSN/F A8700CH/CK/CM/CP/CS SDIP42-P-600-1 TMPA8700CHN/F TMPA8700PSN/F
47C416

Abstract: No abstract text available
Text: · 5-bit to 8 -b it data conversion instruction S u b ro u tin e nesting: 15 levels max. 6 in te rru , te rru p t control is available. I/O p o rt (38 pins) · Input 1 ports 4 pins · O u tp u t 3 ports 12 , port w ith latch. W h en used as th e in p u t p o rt, e x te rn a l in te rru p t in p u t p in, o r , ) system clock co ntro lle r and in te rru p t function. PERIPHERAL HARDWARE FUNCTION © In p u t/O u tp u , (1) In te rru p t C ontroller There are 6 in te rru p t sources (1 external and 5 internal). The


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PDF TMP47C216/416 TMP47C216F TMP47C416F 47C216/416 TLCS-470 TMP47C416F QFP44-P-1414D TMP47P416VF 768kHz 47C416
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