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2009 - rgmii specification

Abstract: RGMII delay RGMII RGMII version 2.0 specification
Text: KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support Revision 1.2 General Description , twisted pair (UTP) cable. The KSZ9021RL provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at , Information). • Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet Transceiver • RGMII interface compliant to RGMII Version 1.3 • RGMII I/Os with 3.3V/2.5V tolerant and programmable timings


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PDF KSZ9021RL/RN KSZ9021RL 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps rgmii specification RGMII delay RGMII RGMII version 2.0 specification
2003 - 88E1111 RGMII

Abstract: Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
Text: ] RGMII_TXD [3:0] GMII_TX_EN RGMII_TX_CTL GMII_TX_ER RGMII_TX_CLK GMII_TX_CLK PHY RGMII_RXD [3:0] GMII_RXD[7:0] RGMII_RX_CTL GMII_RX_DV RGMII_RX_CLK GMII_RX_ER GMII_RX_CLK GMII , ] D1[7:0] D2[7:0] D3[7:0] D4[7:0] RGMII_TX_CLK RGMII_TX_CTL D0[3:0] RGMII_TXD [3:0 , ] D3[7:0] RGMII_RX_CLK RGMII_RX_CTL RGMII_RXD [3:0] D0[3:0] D0[7:4] D1[3:0] D1[7:4 , RGMII_TXD [3:0] D1 Q CE C RGMII_TX_CLK C0 C1 FD D GMII_TX_EN RGMII_TX_CLK Q C


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PDF XAPP692 DS200, 1000BASE-X) 88E1111 RGMII Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
2010 - RGMII constraints

Abstract: RGMII delay rgmii timing RGMII phy fpga rgmii RGMII altddio_in rgmii specification altddio_out
Text: AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs © January 2010 AN-477-2.0 This application note describes how to design a reduced gigabit media independent interface ( RGMII ) with Stratix® , Arria® , and Cyclone® FPGAs and HardCopy® ASICs. RGMII is an alternative to the IEEE , with RGMII , Synopsys design constraints (SDC), and the TimeQuest Timing Analyzer before you read this application note. System-Level Diagram Figure 1 shows a block diagram of RGMII implementation. An RGMII


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PDF AN-477-2 RGMII constraints RGMII delay rgmii timing RGMII phy fpga rgmii RGMII altddio_in rgmii specification altddio_out
RGMII

Abstract: GMII fpga rgmii RGMII constraints 0809 timing diagram isplever LFXP10 RGMII to RGMII
Text: Testbench rgmii2gmii_tb.v · Scripts rgmii2gmii_fsim.tcl rgmii2gmii_tsim.tcl rgmii2gmii_syn.tcl rgmii2gmii_par.tcl wave.do · Constraints rgmii2gmii.lpf Technical Support Assistance Hotline: 1-800 , ec.v · Testbench rgmii2gmii_tb.v · Scripts rgmii2gmii_fsim.tcl rgmii2gmii_tsim.tcl rgmii2gmii_syn.tcl rgmii2gmii_par.tcl wave.do · Constraints rgmii2gmii.lpf The files provided in this LatticeXP , . tx_ctl O HSTL Control signal for transferring other Tx signals to the RGMII. The signal tx_en is


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PDF RD1022 125MHz 1-800-LATTICE RGMII GMII fpga rgmii RGMII constraints 0809 timing diagram isplever LFXP10 RGMII to RGMII
2008 - RGMII Layout Guide

Abstract: 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
Text: specification found at the following link: http://www.hp.com/rnd/pdfs/ RGMIIv2_0_final_hp.pdf. The electrical , . The TCI6486/C6472 device implements an internal delay (referred to as RGMII-ID in the RGMII , RGMII-to-SGMII PHY Device #1 RGTXC RGTXCTL RGTD[3:0] RGCLK RGRXC RGRXCTL RGRD[3:0] 4 P0-GTX-CLK , . 21 Appendix A TCI6486/C6472 RGMII 1.5-V/1.8-V-to-2.5-V/3.3-V Translation , . RGMII PHY Connectivity Diagram


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PDF TMS320C6472/TMS320TCI6486 TMS320TCI6486/TMS320C6472 TCI6486/C6472 TMS320C6472/TMS320TCI6486 RGMII Layout Guide 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
2008 - hifn 8450

Abstract: 1.5V RGMII hsbga 324 HSBGA hifn encryption express sgmii sfp tcam ip cores hifn lzs AN0145 IBM PCI Express serdes architecture
Text: GMAC GMII/TBI Pin Descriptions (Host-side Only) . . . . . . . . . 37 39 Host GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . . . . 39 Host GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . . . . 40 Host GMAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . . . 42 43 Network GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . 43 Network GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . 44 Network MAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . 46 48 GMAC


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PDF DS-0131-06, DS-0131-06 hifn 8450 1.5V RGMII hsbga 324 HSBGA hifn encryption express sgmii sfp tcam ip cores hifn lzs AN0145 IBM PCI Express serdes architecture
2009 - rgmii specification

Abstract: marvell ethernet switch mii RGMII AN3811 RGMII delay MSC8144 MSC8144E MSC8144EC marvell ethernet switch
Text: ://www.hp.com/rnd/pdfs/ RGMIIv2_0_final_hp.pdf To maintain Gigabit speed while reducing the number of data , delay and skew as they are written in the standards for MII, RMII, SMII, and RGMII. As noted in the , DSP for the specific interface and processing configuration (MII, RMII, SMII, RGMII , or SGMII mode , the Reduced Gigabit Media Independent Interface ( RGMII ). The application note does not reproduce the , must research and develop a general understanding of the general principles of RGMII and the other


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PDF AN3811 MSC8144 rgmii specification marvell ethernet switch mii RGMII AN3811 RGMII delay MSC8144E MSC8144EC marvell ethernet switch
2009 - KSZ9021RN

Abstract: KSZ9021 ksz9021rl KSZ9021RNI RGMII rgmii specification TLA-7T101LF rgmii timing KSZ9021RLI fpga rgmii
Text: KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support General Description Features , pair (UTP) cable. The KSZ9021RL provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at 10/100 , /1000Mbps IEEE 802.3 compliant Ethernet Transceiver · RGMII interface compliant to RGMII Version 1.3 · RGMII I/Os with 3.3V/2.5V tolerant and programmable timings to adjust and correct delays on both Tx and


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PDF KSZ9021RL/RN KSZ9021RL 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps M9999-101309-1 KSZ9021RN KSZ9021 KSZ9021RNI RGMII rgmii specification TLA-7T101LF rgmii timing KSZ9021RLI fpga rgmii
2005 - VSC8641XKO-03

Abstract: VSC8641XKO VSC8641 hp laptop MOTHERBOARD pcb CIRCUIT diagram router board 433 circuit diagram for ethernet VSC8641KO marvell ethernet switch sgmii VSC8641XJF VSC8641XK RGMII
Text: VSC8641 10/100/1000BASE-T PHY with RGMII and GMII MAC Interface Datasheet VMDS , . 20 3.2.2 RGMII MAC Interface Mode , . 64 4.3.12 RGMII Skew Control , . 95 6.2.2 GMII/ RGMII MAC Interface , . 105 6.6.2 GMII/ RGMII MAC Interface


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PDF VSC8641 10/100/1000BASE-T VMDS-10211 88-pin, VSC8641XKO 100-pin, VSC8641XKO-03 VSC8641XJF VSC8641XKO-03 VSC8641XKO VSC8641 hp laptop MOTHERBOARD pcb CIRCUIT diagram router board 433 circuit diagram for ethernet VSC8641KO marvell ethernet switch sgmii VSC8641XJF VSC8641XK RGMII
2009 - ML605 UCF FILE

Abstract: iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
Text: attributes based on user options Provides user-configurable Ethernet MAC physical interfaces · Supports RGMII v1.3, RGMII v2.0, SGMII, and 1000BASE-X PCS/PMA interfaces, as well as GMII/MII at 2.5V only , RGMII SGMII PCS PMA 1000BASE-X PMD Figure 1: Typical Ethernet Architecture Figure 1 displays , (UG368). RGMII The Reduced-GMII ( RGMII ) is an alternative to GMII/MII. RGMII achieves a 50-percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII


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PDF DS710 ML605 UCF FILE iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
2012 - RGMII version 2.0 specification

Abstract: No abstract text available
Text: KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Revision 2.0 General Description , twisted pair (UTP) cable. The KSZ9031RNX provides the reduced Gigabit media independent interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at , €¢ Single-chip 10/100/1000Mbps IEEE 802.3-compliant Ethernet transceiver • RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making


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PDF KSZ9031RNX KSZ9031RNX 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps. RGMII version 2.0 specification
2012 - ksz9031

Abstract: KSZ9031RNXIA KSZ9031RNX 73d15 KSZ9021RN KSZ9031RN KSZ9031RNXCA JK0-0136NL KSZ9031RNXCC TG1G-S001NZ
Text: KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Data Sheet Rev. 1.0 General , ) cable. The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps , IEEE 802.3 compliant Ethernet transceiver · RGMII timing supports on-chip delay according to RGMII , RX timing paths · RGMII with 3.3V/2.5V/1.8V tolerant I/Os · Auto-negotiation to automatically select


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PDF KSZ9031RNX KSZ9031RNX 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps. KSZ90. M9999-103112-1 ksz9031 KSZ9031RNXIA 73d15 KSZ9021RN KSZ9031RN KSZ9031RNXCA JK0-0136NL KSZ9031RNXCC TG1G-S001NZ
2004 - RGMII

Abstract: HSTL RGMII switch RGMII 2-channel switch SM 933 RGMII switch rgmii hstl TO lvcmos PM8373 PM8363 PM8364 24xFE
Text: ] CTC_EN RGMII_RTBIB TDO TCK TDI TMS TRSTB G_DIGLB TCLKSEL Control/Status JTAG , 1.5 V and 1.8 V RGMII /RTBI interface. · 1.8 V and 2.5 V LVCMOS interoperable for all other digital I , Rate Interface compliant with RGMII /RTBI v2.0 standard. · Receive channel output clocks eliminate the need for PLLs in interface ASICs. · 1.5 V and 1.8 V HSTL interoperable on RGMII /RTBI digital I , PCS RTBI Mode RXDy[3:0] Receive RGMII W/O CTC PCS _SM RxCTLy RxFIFO RXCKy RGMII &


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PDF PM8364 8B/10B PMC-2040187 RGMII HSTL RGMII switch RGMII 2-channel switch SM 933 RGMII switch rgmii hstl TO lvcmos PM8373 PM8363 PM8364 24xFE
2013 - rgmii specification ieee

Abstract: LAN8820i
Text: information. RGMII ID Mode Enable Configuration Strap RGMII_ID_MODE IS (PD) This configuration , 10_LED/REFCLK_SEL 100_LED/HPD_MODE 1000_LED/ RGMII_ID_MODE VDD12CORE TXC 42 41 40 , TR3P 14 RXCTRL 28 TXCTRL 42 ETHRBIAS 56 VDD12A RGMII_ID_MODE EXPOSED PAD , LAN8820/LAN8820i RGMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT , specification at 10/100/1000 Mbps operation Miniature 56-pin QFN lead-free RoHS compliant package with RGMII


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PDF LAN8820/LAN8820i 1000BASE-T) 802-3/IEEE 10BASE-T) 56-pin rgmii specification ieee LAN8820i
2010 - AR8033

Abstract: AR8031 AR8035 AR-8031 atheros ethernet switch AR8030 Atheros ar8035 RGMII to SGMII ATHEROS AR80 AR8031-11-29-10
Text: AR8031 Ultra low-power 10/100/1000 RGMII /SGMII Gigabit Ethernet Transceiver Technology Overview , consumers and businesses. Solution Highlights AR8031 Product Overview · SGMII and RGMII MAC , PHY. It supports both RGMII and SGMII interfaces to the MAC. The AR8031 provides a low-power, low BOM , RGMII / SGMII RGMII / SGMII TRD[0:3] Hybrid Circuit PGA AGC PMA The AR8031 also supports , on both the MAC interfaces ( RGMII /SGMII) and the line side. ADC Trellis Decoder Timing and


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PDF AR8031 AR8031-11-29-10 AR8033 AR8031 AR8035 AR-8031 atheros ethernet switch AR8030 Atheros ar8035 RGMII to SGMII ATHEROS AR80 AR8031-11-29-10
CNS3420

Abstract: CNS3410 RGMII to PCIe USB2.0 video controller BT656 ARM11 PCIe PHY ARM11 mpcore PCIe BT.656 sata phy block diagram of floating point dsp processors
Text: ( RGMII / GMII/ MII supported) · Dual SATA, PCIe and USB2.0 with integrated PHYs · TDM/PCM, I2S, SPI, I2C , / MMU 300 ­ 700 MHz 32K I Cache RGMII RGMII PSE R/GMII 5xGE Non-Blocking 64 , PCIe 16/32 bit RGMII WLAN 802.11n OR Femto Radio ECONA CNS3XXX WLAN Module , .0 SATA RGMII /GMII GMII/ RGMII WLAN Module SATA HDD MoCA/ HPNA HDD Flash Radio / MAC Ethernet Switch PCIe RGMII WLAN 802.11n WAN+LAN USB2.0 GbE Switch


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PDF ARM11 HSBGA-484 CNS3420 CNS3410 RGMII to PCIe USB2.0 video controller BT656 PCIe PHY ARM11 mpcore PCIe BT.656 sata phy block diagram of floating point dsp processors
2008 - RGMII Layout Guide

Abstract: No abstract text available
Text: RGMII /RTBI Interface Usage . . . . . . . . . . . . . . . . . . 41 6.2.2.1 Host GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . . . . 41 6.2.2.2 Host GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . . . . 42 6.2.2.3 Host GMAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . . . 44 6.2.3 Network GMAC RGMII /RTBI Interface Usage . . . . . . . . . . . . . . . 46 6.2.3.1 Network GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . 46 6.2.3.2


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PDF DS-0142-C, DS-0142-C RGMII Layout Guide
2012 - MAX24287

Abstract: RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
Text: 125MHz transmit clock. RGMII Modes: GTXCLK is the 125MHz ( RGMII-1000 ), 25MHz ( RGMII-100 ) or 2.5MHz ( RGMII-10 , 10Mbps MII 0 1 100Mbps MII 1 0 1000Mbps GMII 1 1 1000Mbps TBI DDR=1 RGMII-10 RGMII-100 RGMII-1000 RTBI , : RXCLK is the 125MHz receive clock. RGMII Modes: RXCLK is the 125MHz ( RGMII-1000 ), 25MHz ( RGMII-100 ) or , the rising edge of RXCLK. MII, RGMII-10 and RGMII-100 Modes: receive_data[3:0] is output on RXD[3:0 , . 62 Table 9-12. RGMII-1000 and RTBI Receive AC Characteristics


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
2004 - RGMII

Abstract: 4-Port Gigabit Ethernet Transceiver SM 933 PM8373 HSTL RGMII HSTL RGMII switch RGMII switch
Text: MDIO MDIO I/F DVAD[4:3] CTC_EN G_DIGLB TCLKSEL TDO TDI TCK RGMII_RTBIB , Minimal external components required. · 1.5 V and 1.8 V RGMII /RTBI interface. · 1.8 V and 2.5 V LVCMOS , Rate Interface compliant with RGMII /RTBI v2.0 standard. · Receive channel output clocks eliminate the need for PLLs in interface ASICs. · 1.5 V and 1.8 V HSTL interoperable on RGMII /RTBI digital I , RTBI Mode RXDy[3:0] Receive RGMII W/O CTC PCS _SM RxCTLy RxFIFO RXCKy RGMII & CTC


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PDF PM8373 8B/10B PMC-2030005 RGMII 4-Port Gigabit Ethernet Transceiver SM 933 PM8373 HSTL RGMII HSTL RGMII switch RGMII switch
2005 - bcm5488

Abstract: rgmii specification rgmii specification ieee sgmii specification ieee sgmii RGMII switch RGMII to MII RGMII SGMII
Text: FEATURES · Eight fully integrated 10BASE-T/100BASE-TX/1000BASE-T Gigabit Ethernet transceivers · RGMII , SGMII, and SerDes MAC interface options · 1-Gbps lineside SerDes with RGMII MAC interface option · , power and cost · Supports copper or fiber in RGMII mode · Low power · <625 mW per port · Advanced , pin requirements with RGMII (over 50%), SGMII (over 75%), and SerDes (over 80%) · Clock timing can be adjusted to eliminate board trace delays required by the RGMII specification · Lowers MAC/switch


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PDF BCM5488 10/100/1000BASE-T 10BASE-T/100BASE-TX/1000BASE-T 13-micron BCM5488 5488-PB00-R rgmii specification rgmii specification ieee sgmii specification ieee sgmii RGMII switch RGMII to MII RGMII SGMII
2006 - Not Available

Abstract: No abstract text available
Text: for routing high density solutions. - Reduced I/O pin requirements with RGMII (over 50%), SGMII , required by the RGMII specification. - Lowers MAC/switch costs by reducing the number of pins required to interface to the PHY. Gigabit Ethernet transceivers • RGMII , SGMII, and SerDes MAC interface options • 1-Gbps line-side SerDes with RGMII MAC interface • Fully compliant with IEEE 802.3, 802.3u , RGMII mode • Provides compatibility with IEEE standard devices operating at 10, 100, and 1000 Mbps


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PDF BCM5464R 10/100/1000BASE-T 10BASE-T/100BASE-TX/1000BASE-T BCM5464R 5464R-PB01-R
2007 - sgmii sfp virtex

Abstract: UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl DS307 1000BASE-X RGMII SGMII
Text: the EMAC0/EMAC1 tie-off pins based on user options - Supports MII, GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , , and as a result, GMII/MII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1 Gbps. RGMII The Reduced-GMII ( RGMII ) is an alternative to the GMII/MII. RGMII achieves a 45 percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII is preferred over GMII by


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PDF DS307 1000BASE-X sgmii sfp virtex UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl RGMII SGMII
2011 - MAX24287

Abstract: RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
Text: . RGMII Modes: GTXCLK is the 125MHz ( RGMII-1000 ), 25MHz ( RGMII-100 ) or 2.5MHz ( RGMII-10 ) transmit clock , clocks DDR=1 RGMII-10 RGMII-100 RGMII-1000 RTBI In 3-pin mode (COL=1 during reset, see Table , ), 25MHz ( RGMII-100 ) or 2.5MHz ( RGMII-10 ) receive clock (DDR). TBI Mode: In normal TBI mode , output on RXD[7:0] on the rising edge of RXCLK. MII, RGMII-10 and RGMII-100 Modes: receive_data[3:0] is , . 61 Table 9-12. RGMII-1000 and RTBI Receive AC Characteristics


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PDF MAX24287 MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
2006 - vhdl code for mac interface

Abstract: sfp design virtex-5 ETHERNET-MAC verilog code for ethernet FPGA Virtex 6 vhdl code for phy interface RGMII phy Xilinx gmii sfp fpga ethernet sgmii 1000BASE-X fpga rgmii
Text: , Scripts User Constraints File (.ucf) Example Designs - Supports MII, GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , , and as a result, GMII/MII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1 Gbps. RGMII The Reduced-GMII ( RGMII ) is an alternative to GMII/MII. RGMII achieves a 50-percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII is preferred over GMII by


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PDF DS550 Virtex-51 vhdl code for mac interface sfp design virtex-5 ETHERNET-MAC verilog code for ethernet FPGA Virtex 6 vhdl code for phy interface RGMII phy Xilinx gmii sfp fpga ethernet sgmii 1000BASE-X fpga rgmii
2004 - HSTL RGMII

Abstract: RGMII SM10B
Text: JTAG Control/Status ad ed RGMII_RTBIB DVAD[4:3] REFCLK RPRES RESET POEN , only device configuration. · Minimal external components required. · 1.5 V and 1.8 V RGMII /RTBI , -bit Dual Data Rate Interface compliant with RGMII /RTBI v2.0 standard. · Receive channel output clocks eliminate the need for PLLs in interface ASICs. · 1.5 V and 1.8 V HSTL interoperable on RGMII /RTBI digital I , RTBI Mode RXDy[3:0] RxCTLy RXCKy RGMII W/O CTC m of PCS _SM 8B/10B Encoder PCS Receive


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PDF PM8364 8B/10B 28xGE PMC-2040187 HSTL RGMII RGMII SM10B
Supplyframe Tracking Pixel