The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
ISL5629/2INZ Intersil Corporation Dual 8-bit, +3.3V, 130/210MSPS, CommLink™ High Speed D/A Converter; LQFP48; Temp Range: -40° to 85°C
ISL5927INZ Intersil Corporation Dual 14-Bit, +3.3V, 260MSPS, High Speed D/A Converter; LQFP48; Temp Range: -40° to 85°C
CA3338AMZ Intersil Corporation PARALLEL, 8 BITS INPUT LOADING, 0.02us SETTLING TIME, 8-BIT DAC, PDSO16, LEAD FREE, PLASTIC, MS-013-AA, SOIC-16
HI5660/6IAZ Intersil Corporation 8-Bit, 125/60MSPS, High Speed D/A Converter; SOIC28, TSSOP28; Temp Range: -40° to 85°C
HI5731BIB Intersil Corporation PARALLEL, WORD INPUT LOADING, 0.02us SETTLING TIME, 12-BIT DAC, PDSO28
HI5741BIBZ Intersil Corporation 14-Bit, 100 MSPS, High Speed D/A Converter; SOIC28; Temp Range: -40° to 85°C

RGMII to MII Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - 16X2 LCD vhdl CODE

Abstract: DE2-115 EP4CE115F29 philips DVD player with usb port circuit diagram vhdl code for lcd display for DE2 altera LCD display module 16x2 HD44780 zt3232 altera de2 altera de2 board sd card simple vhdl de2 audio codec interface
Text: . 115 3 Chapter 1 DE2-115 Package The DE2-115 package contains all components needed to use , contains some extender pins, which can be used to facilitate easier probing with testing equipment of the , controller 1.2 The DE2-115 Boar d Assembly To assemble the included stands for the DE2-115 board , -115 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the DE2-115 board


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PDF DE2-115 DE2-115 Table4-15 16X2 LCD vhdl CODE EP4CE115F29 philips DVD player with usb port circuit diagram vhdl code for lcd display for DE2 altera LCD display module 16x2 HD44780 zt3232 altera de2 altera de2 board sd card simple vhdl de2 audio codec interface
2008 - RGMII Layout Guide

Abstract: 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
Text: /C6472 device and the MDIO interface can be configured to use HSTL levels and be compatible with RGMII , are powered, the unused RGMII input pins should be pulled to ground. 4 TMS320C6472 , management interface to different devices. For example, if EMAC0 is configured for RGMII and EMAC1 is , None 0 0 0 1 0 1 MII RGMII 0 1 0 X X 0 GMII None 0 , be used to choose the best value for a specific board implementation. 9.1 GMII/ MII The GMII


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PDF TMS320C6472/TMS320TCI6486 TMS320TCI6486/TMS320C6472 TCI6486/C6472 TMS320C6472/TMS320TCI6486 RGMII Layout Guide 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
2009 - ML605 UCF FILE

Abstract: iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
Text: (UG368). RGMII The Reduced-GMII ( RGMII ) is an alternative to GMII/ MII . RGMII achieves a 50 , illustrated in Figure 1 and Figure 2, these can be connected using GMII/ MII , RGMII , or SGMII to provide a , v1.3, RGMII v2.0, SGMII, and 1000BASE-X PCS/PMA interfaces, as well as GMII/ MII at 2.5V only , to , any type of physical sublayer. GMII/ MII The Media Independent Interface ( MII ), defined in , extension of the MII used to connect a 1-Gb/s capable MAC to the physical sublayers. MII can be considered a


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PDF DS710 ML605 UCF FILE iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
2006 - vhdl code for mac interface

Abstract: sfp design virtex-5 ETHERNET-MAC verilog code for ethernet FPGA Virtex 6 vhdl code for phy interface RGMII phy Xilinx gmii sfp fpga ethernet sgmii 1000BASE-X fpga rgmii
Text: Reduced-GMII ( RGMII ) is an alternative to GMII/ MII . RGMII achieves a 50-percent reduction in the pin count , Figures 1 and 2, these can be connected using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet , , Scripts User Constraints File (.ucf) Example Designs - Supports MII , GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/ MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , used to connect a 1-Gbps capable MAC to the physical sublayers. MII can be considered a subset of GMII


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PDF DS550 Virtex-51 vhdl code for mac interface sfp design virtex-5 ETHERNET-MAC verilog code for ethernet FPGA Virtex 6 vhdl code for phy interface RGMII phy Xilinx gmii sfp fpga ethernet sgmii 1000BASE-X fpga rgmii
2012 - MAX24287

Abstract: RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
Text: Applications Any System with a Need to Interface a Component with a Parallel MII Interface (GMII, RGMII , TBI , . 32 GMII, RGMII and MII Serial to Parallel Conversion and Decoding . 35 GMII, RGMII and MII Parallel to Serial Conversion and Encoding , configured for GMII, RGMII , TBI, RTBI, or 10/100 MII , while the serial interface can be configured for , -, 6-, or 8-Pin) Parallel Interface Configurable as GMII, RGMII , TBI, RTBI, or 10/100 MII Serial


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
2011 - MAX24287

Abstract: RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
Text: Interface a Component with a Parallel MII Interface (GMII, RGMII , TBI RTBI, 10/100 MII ) to a Component , . 35 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 GMII, RGMII and MII Serial to Parallel , configured for GMII, RGMII , TBI, RTBI, or 10/100 MII , while the serial interface can be configured for , GMII, RGMII , TBI, RTBI, or 10/100 MII Serial Interface Has Clock and Data Recovery Block (CDR , MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate


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PDF MAX24287 MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
2012 - RGMII to SGMII PHY

Abstract: MAX24287 switch SGMII MII GMII RGMII to SGMII sgmii sgmii mode sfp 1000BASE-X sfp sgmii 1000BASE-X fpga ethernet sgmii fpga rgmii
Text: Parallel MII Interface (GMII, RGMII , TBI RTBI, 10/100 MII ) to a Component with an SGMII or 1000BASE , be configured for GMII, RGMII , TBI, RTBI, or 10/100 MII , while the serial interface can be configured , Configurable as GMII, RGMII , TBI, RTBI, or 10/100 MII Serial Interface Has Clock and Data Recovery Block , MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate Configurable for 10/100 MII DTE or DCE Modes (i.e., Connects to PHY or MAC) Can Also Be Configured


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII to SGMII PHY switch SGMII MII GMII RGMII to SGMII sgmii sgmii mode sfp 1000BASE-X sfp sgmii fpga ethernet sgmii fpga rgmii
2007 - sgmii sfp virtex

Abstract: UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl DS307 1000BASE-X RGMII SGMII
Text: Reduced-GMII ( RGMII ) is an alternative to the GMII/ MII . RGMII achieves a 45 percent reduction in the pin count , Figures 1 and 2, these can be connected using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet , the EMAC0/EMAC1 tie-off pins based on user options - Supports MII , GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/ MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , used to connect a 1-Gbps capable MAC to the physical sublayers. MII can be considered a subset of GMII


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PDF DS307 1000BASE-X sgmii sfp virtex UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl RGMII SGMII
2006 - IP1001-DS-R02

Abstract: A 1712 IP1001 IP1001-DS-R01 giga media converter IC Plus
Text: works in MII or GMII mode. VDDO is connected to 2.5v if IP1001 works at RGMII mode. 24 AVDDH , RGMII / GMII/ MII to interface a MAC device. Registers in the IP1001 can be accessed via the SMI (MDC , auto-negotiation Support timing programmable MII / GMII/ RGMII (delay clock, and driving current etc.) Support 3 , -TX, and 10BASE-T applications. IP1001 supports MII , GMII and RGMII for different types of 10/100/1000Mb , quality to guarantee data transmission. Cable analysis function "SCA" is supported by programming MII


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PDF IP1001 1000BASE-T, 100BASE-TX, 10BASE-T 10M/100M 125MHz 25MHz 354BSC 344BSC 020BSC IP1001-DS-R02 A 1712 IP1001 IP1001-DS-R01 giga media converter IC Plus
2004 - application TEMAC

Abstract: RGMII constraints 1000BASE-X DS297 sgmii specification ieee switch SGMII MII GMII RGMII phy Xilinx spartan ucf file 6 sgmii xilinx EF-DI-TEMAC-PROJ
Text: using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet port. The 1000BASE-X architecture , FIFO-based loopback example design and adds IOB flip-flops to the external signals of the GMII/ MII (or RGMII , to provide an external GMII/ MII 3 - A shim to provide an external RGMII1 · Configured and monitored , Control pause frames · Optional MDIO interface to managed objects in PHY layers ( MII Management) · , v4.3 Ethernet Tri-Speed BASE-T Port ( MII /GMII or RGMII ) Figure 2 illustrates a typical


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PDF DS297 application TEMAC RGMII constraints 1000BASE-X sgmii specification ieee switch SGMII MII GMII RGMII phy Xilinx spartan ucf file 6 sgmii xilinx EF-DI-TEMAC-PROJ
2006 - sgmii sfp virtex

Abstract: xilinx virtex 5 mac 1.3 fpga rgmii RGMII to MII fpga ethernet sgmii iodelay Virtex-5 LXT Ethernet GTX 460 switch SGMII MII GMII GTP ethernet
Text: Mbps, 100 Mbps, and 1 Gbps. RGMII The Reduced-GMII ( RGMII ) is an alternative to GMII/ MII . RGMII , Supports MII , GMII, RGMII v1.3, RGMII v2.0, SGMII, and 1000BASE-X PCS/PMA interfaces Supported HDL , / MII RGMII SGMII (RocketIO) PMD PMA 1000BASE-X (RocketIO) Figure 1: Typical Ethernet , , and can connect to , any type of physical sublayer. GMII/ MII The Media Independent Interface ( MII , clause 35, is an extension of the MII used to connect a 1-Gbps capable MAC to the physical sublayers


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PDF DS550 sgmii sfp virtex xilinx virtex 5 mac 1.3 fpga rgmii RGMII to MII fpga ethernet sgmii iodelay Virtex-5 LXT Ethernet GTX 460 switch SGMII MII GMII GTP ethernet
2007 - RTL8212G

Abstract: RTL8212 rtl8211 RTL8212-GR RTL821 rtl836 RTL8369 QFN-76 QFN76 RTL8212N-GR
Text: .52 9.2. MII /GMII/ RGMII SIGNAL LAYOUT GUIDELINES , modules. Each of the two independent transceivers features an industrial standard MII , GMII, and RGMII , duplex, CRS is also asserted during transmission. CRS is asynchronous to TXC and RXC. MII /GMII , duplex mode, this out is forced low. COL is asynchronous to TXC, and RXC. MII /GMII Receive Error. When , asserted with RXDV deasserted) is not valid. RXDV is synchronous to RXC. MII /GMII Receive Data Bus. The


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PDF RTL8212-GR RTL8212N-GR RTL8211N-GR JATR-1076-21 RTL8212/RTL8212N/RTL8211N DHS-QFP-128 RTL8212G RTL8212 rtl8211 RTL8212-GR RTL821 rtl836 RTL8369 QFN-76 QFN76 RTL8212N-GR
2006 - RGMII constraints

Abstract: 1000base-x xilinx xilinx virtex 5 mac 1.3 V583 RGMII to SGMII fpga ethernet sgmii DS307 1000BASE-X Ethernet-MAC using vhdl ETHERNET-MAC
Text: Reduced-GMII ( RGMII ) is an alternative to the GMII/ MII . RGMII achieves a 45 percent reduction in the pin count , Figures 1 and 2, these can be connected using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet , the EMAC0/EMAC1 tie-off pins based on user options - Supports MII , GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/ MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , used to connect a 1-Gbps capable MAC to the physical sublayers. MII can be considered a subset of GMII


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PDF DS307 1000BASE-X RGMII constraints 1000base-x xilinx xilinx virtex 5 mac 1.3 V583 RGMII to SGMII fpga ethernet sgmii Ethernet-MAC using vhdl ETHERNET-MAC
2012 - RGMII-1000

Abstract: MAX24287 switch SGMII MII GMII sgmii specification ieee ENG-46158
Text: Parallel MII Interface (GMII, RGMII , TBI RTBI, 10/100 MII ) to a Component with an SGMII or 1000BASE , . 32 GMII, RGMII and MII Serial to Parallel Conversion and Decoding . 35 GMII, RGMII and MII Parallel to Serial Conversion and Encoding , for GMII, RGMII , TBI, RTBI, or 10/100 MII , while the serial interface can be configured for 1.25Gbps , Configurable as GMII, RGMII , TBI, RTBI, or 10/100 MII Serial Interface Has Clock and Data Recovery Block


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII sgmii specification ieee ENG-46158
2005 - RTL8212

Abstract: RTL8369 QFN-76
Text: .59 MII /GMII/ RGMII SIGNAL LAYOUT GUIDELINES , RGMII (Reduced Gigabit Media Independent Interface). To further reduce PCB trace complexity, the , / MII RGMII RTL8212 Dual-PHY (10/100/1000) RTL8208 Octa-PHY (10/100) RTL8208 Octa-PHY (10 , also asserted during transmission. CRS is asynchronous to TXC and RXC. GMII/ MII Collision. This , out is forced low. COL is asynchronous to TXC, and RXC. GMII/ MII Receive Error. When RXER and RXDV


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PDF RTL8212-GR RTL8212N-GR RTL8211N-GR JATR-1076-21 RTL8212/RTL8212N/RTL8211N kin8212N) QFP-128 RTL8212 RTL8369 QFN-76
2004 - xilinx tcp vhdl

Abstract: TEMAC 1000BASE-X application TEMAC DS297 fpga ethernet sgmii IMPLEMENTATION OF IEEE 802.3 MAC TRANSMITTER USING VHDL MDIO communication protocol UCF virtex4
Text: using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet port. The 1000BASE-X architecture , example design and adds IOB flip-flops to the external signals of the GMII/ MII (or RGMII ). All clock , ) that can be connected to - IOBs to provide an external GMII/ MII 4 - A shim to provide an external , Optional MDIO interface to managed objects in PHY layers ( MII Management) · Optional Address Filter with , Tri-Mode Ethernet MAC v4.2 Ethernet Tri-Speed BASE-T Port ( MII /GMII or RGMII ) Figure 2 illustrates a


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PDF DS297 xilinx tcp vhdl TEMAC 1000BASE-X application TEMAC fpga ethernet sgmii IMPLEMENTATION OF IEEE 802.3 MAC TRANSMITTER USING VHDL MDIO communication protocol UCF virtex4
2004 - vhdl code for ethernet mac spartan 3

Abstract: application TEMAC TEMAC verilog code for mdio protocol RGMII RGMII SGMII 1000BASE-X MDIO clause 22 clause 22 phy registers DS297
Text: , these can be connected using GMII/ MII , RGMII , or SGMII to provide a tri-speed Ethernet port. The , , OBUFs, and IOB flip-flops to the external signals of the GMII/ MII (or RGMII ). All clock management , Ethernet 1000BASE-X PCS/PMA or SGMII core or other custom logic - IOBs to provide an external GMII/ MII - A shim to provide an external RGMII · Configured and monitored through an optional independent , asymmetrically enabled · Optional MDIO interface to managed objects in PHY layers ( MII Management) · Optional


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PDF DS297 1000BASE-X vhdl code for ethernet mac spartan 3 application TEMAC TEMAC verilog code for mdio protocol RGMII RGMII SGMII MDIO clause 22 clause 22 phy registers
2008 - marvel phy 88e1111 reference design

Abstract: 88E6182 RGMII switch Marvell PHY 88E1111 alaska register map 88E1111 PHY registers map MSC8156ADS 88E1111 PHY registers map Triple-Speed Ethernet M 88E1111 register map 88E1111 config 88E1111 RGMII
Text: : Master and Slave - MII controller to program RGMII PHY - SPI controller - Boot Sequencer configures , to verify DDR2 module on the MSC8156 DDRC2 controller. The DSP RGMII (at ports GE1 and GE2) connects , ISP JTAG LED lsb CCSLLD LYNX1/LYNX2 MI/ MII msb OnCE PC PCIe PHY POL PS, PSU RGMII RCW(L,H , RGMII (multiplexed with TDM ports) interface. Four TDM ports together support up to 1K time-slots for , connector and on PTMC connectors J3. TDM lines are multiplexed with RGMII . Two E1/T1 Framers link to four


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PDF MSC8156ADS MSC8156 MSC8256 MSC8156ADSRM EL516 marvel phy 88e1111 reference design 88E6182 RGMII switch Marvell PHY 88E1111 alaska register map 88E1111 PHY registers map 88E1111 PHY registers map Triple-Speed Ethernet M 88E1111 register map 88E1111 config 88E1111 RGMII
2004 - 741 IC data sheet

Abstract: uA 741 IC data sheet vsc8244 vsc8244hg orcad schematic symbol for rj45 vsc8224hg VSC8234hg RGMII V1.3 vsc8234 1.5V RGMII
Text: VSC8244 Data Sheet Quad 10/100/1000BASE-T PHY with RGMII and RTBI MAC Interfaces 1 General , 640mW per port, supporting 1000BASE-T with respect to all worst case impairments (NEXT, FEXT, Echo , pin-efficient RGMII and RTBI compliant MAC interfaces. On-chip RGMII /RTBI series termination resistors , integrates, for the first time in the industry, all copper media side line termination resistors. To enable maximum network management feedback to the host system and the user, the VeriPHY® Link Management


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PDF VSC8244 10/100/1000BASE-T VSC8244 10BASE-T, 100BASE-TX, 1000BASE-T) 260-pin 640mW 1000BASE-T 741 IC data sheet uA 741 IC data sheet vsc8244hg orcad schematic symbol for rj45 vsc8224hg VSC8234hg RGMII V1.3 vsc8234 1.5V RGMII
ieee format for w16 engine

Abstract: ASIX ELECTRONICS CORPORATION AX88655 AX88655AB gmii phy
Text: . And synchronous to rising edge of TX_CLK0 in 10/100BASE-T mode., For RGMII , only TXD0[3:0] MII , 1. Add RGMII timing diagram 2. TRUNKING register correction 3. modify all GMII/ MII to RGMII /GMII , with RGMII /GMII/ MII interface RGMII support REV 1.3 with 3.3V IO Full Duplex 1000 Mbit/s. Full and , /1000 Mbps Ethernet switch with, GMII/ RGMII or MII Interface. The switch controller provides network , .7 2.1 RGMII /GMII/ MII INTERFACE


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PDF AX88655 10/100/1000BASE-T AX88655AB ieee format for w16 engine ASIX ELECTRONICS CORPORATION gmii phy
RGMII phy

Abstract: RGMII L10M VSC8201 rgmii specification RGMII to MII 1.5V RGMII rgmii timing GMII switch
Text: ETHERNET PRODUCTS VSC8201 Single Port 10/100/1000BASE-T PHY with GMII, MII , TBI, RGMII / RTBI , Migration to 1000BASE-T by Minimizing Common Interoperability Problems Choice of Standard GMII/ MII or TBI , PB-VSC8201-002 VSC8201 Single Port 10/100/1000BASE-T PHY with GMII, MII , TBI, RGMII / RTBI MAC , require a GMII/ MII , RGMII , TBI, or RTBI MAC / Switch interface. The VSC8201's integrated switching , Enables Widespread, Low Cost, 1000BASE-T Deployment in Desktop NICs and Switches Compliant with RGMII


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PDF VSC8201 10/100/1000BASE-T 1000BASE-T RGMII phy RGMII L10M VSC8201 rgmii specification RGMII to MII 1.5V RGMII rgmii timing GMII switch
2006 - IP1001LF

Abstract: giga Ethernet PHY RGMII IC PLUS IP1001 1000BASE IP1001 IP1001-DS-R13 CSB453 giga media converter IP1001-DS-R01
Text: /slave resolution. This device also supports RGMII / GMII/ MII to interface a MAC device. Registers in , timing programmable MII / GMII/ RGMII (delay clock, and driving current etc.) Support 3 power saving , -T applications. IP1001 supports MII , GMII and RGMII for different types of 10/100/1000Mb Media Access , IEEE802.3, and APS (auto power saving). Physical Layer Device RGMII / GMII/ MII IP1001 IP1001 , . 16 3.2 MAC Interface ( RGMII / GMII/ MII


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PDF IP1001 1000BASE-T, 100BASE-TX, 10BASE-T 10M/100M 125MHz CSB05 CSB57 CSB00 FER02 IP1001LF giga Ethernet PHY RGMII IC PLUS IP1001 1000BASE IP1001-DS-R13 CSB453 giga media converter IP1001-DS-R01
CICADA SEMICONDUCTOR

Abstract: PAM-5 1.5V RGMII Cicada Cis8204 CIS8204 Ethernet-MAC ic 10BASE DIGITAL ECHO pcb RGMII to MII pc partner
Text: CIS8204 PRODUCT BRIEF QUAD LOW POWER, TRIPLE SPEED PHY WITH GMII / MII , RGMII & TBI / RTBI , standard GMII / MII , an optional TBI, or pin saving RGMII / RTBI, 4D -PAM5 encoder/decoder, scrambler , Ethernet MAC GMII / MII 10/100/1000 Ethernet MAC Quad Transformer RJ-45 RGMII Quad , to any MAC or switch controller ASIC 100BASE -TX, and 1000BASE -T), low power Ethernet , CIS8204 physical layer "PHY" IC leverages Cicada's proprietary MicroPHY TM DSP Technology, key to enabling


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PDF CIS8204 48-port 1000BASE-T 10BASE 125MHz /-100ppm CICADA SEMICONDUCTOR PAM-5 1.5V RGMII Cicada Cis8204 CIS8204 Ethernet-MAC ic DIGITAL ECHO pcb RGMII to MII pc partner
2006 - Speed-10

Abstract: IP1001-DS-R01 IP1001 1000BASE RW101 giga Ethernet PHY RGMII RGMII delay IP1001LF
Text: upon power-on reset to define the RGMII /GMII interface mode. 0: RGMII mode (default) 1: GMII/ MII , works in MII or GMII mode. VDDO is connected to 2.5v if IP1001 works at RGMII mode. 3.3v/ 2.5v analog , / half) mode and master/slave resolution. This device also supports RGMII / GMII/ MII to interface a MAC , -T applications. IP1001 supports MII , GMII and RGMII for different types of 10/100/1000Mb Media Access , Support timing programmable MII / GMII/ RGMII (delay clock, and driving current etc.) Support 3 power


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PDF IP1001 1000BASE-T, 100BASE-TX, 10BASE-T 10/100/1000Mb Speed-10 IP1001-DS-R01 1000BASE RW101 giga Ethernet PHY RGMII RGMII delay IP1001LF
2004 - GMII switch

Abstract: 1000base RJ45 LED Gigabit Ethernet PHY TBI 1000BASE-T 1000baseT VSC8204
Text: ETHERNET PRODUCTS VSC8204 Quad Port 10/100/1000BASE-T PHY with GMII, MII , TBI, RGMII / RTBI MAC , MAC GMII / MII RGMII TBI RTBI 388 HS-PBGA (35mm x 35mm or 27mm x 27mm) Quad Transformer Quad , /MDI-X Crossover Function Choice of Standard GMII/ MII or TBI, or Pin Saving RGMII /RTBI Interfaces , -002 VSC8204 Quad Port 10/100/1000BASE-T PHY with GMII, MII , TBI, RGMII / RTBI MAC Interfaces GENERAL , Ethernet Switch applications that require a GMII/ MII , RGMII , TBI, or RTBI MAC / Switch interface. Vitesse


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PDF VSC8204 10/100/1000BASE-T RJ-45 RJ-45 10/100/1000BASE-T) 388Pin 1000BASE-T GMII switch 1000base RJ45 LED Gigabit Ethernet PHY TBI 1000baseT VSC8204
Supplyframe Tracking Pixel