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2004 - RGMII 3COM

Abstract: mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
Text: - 0 - 1 -GMII mode - 1 - 0 - RGMII mode (HP original) - 1 - 1 - RGMII mode ( 3COM ) If RGMII is to be used, 3COM mode is recommended. See "Note on Recommended PCB Layer , " All RGMII signals in 3COM mode must have the same trace length between PHY and MAC (including serial termination resistor). Tolerance +/- 0.5" Refer to DP83865DVH datasheet for layout instructions on RGMII HP , require this interface to be configured as RGMII . Follow these instructions to change design to RGMII


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PDF DP83865DVH: LINK100 25MHz DP83865 RGMII 3COM mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
2015 - BCM89810

Abstract: BROADCOM BCM89810 ad2410 schematic usb to rj45 cable extender AT/BCM89810 INA3221
Text: operate in RGMII-3COM mode. The PHY supports 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols. On the board, EMAC0 is also connected to a Broadcom BCM89810 PHY. It is configured to operate in RGMII , /100 Mbps (interfacing through RMII) or 1 Gbps (interfacing through RGMII ). It supports IEEE 1588 and , UART0 USB to UART FTDI232RQ EMAC0 RGMII interface enabled EMAC0 RMII interface enabled


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PDF ADSP-SC584 445-4060-2-ND SRN8040-6R8Y CDBC540-G 641-1126-2-ND 565-3197-2-ND DO214AB BCM89810 BROADCOM BCM89810 ad2410 schematic usb to rj45 cable extender AT/BCM89810 INA3221
2004 - Not Available

Abstract: No abstract text available
Text: , S, PD 39 0 = RGMII - HP 1 1 = RGMII - 3COM COLLISION DETECT: Asserted high to , Gigabit Media Independent Interface (GMII), or Reduced GMII ( RGMII ). The DP83865 is a fourth generation , s IEEE 802.3z GMII s RGMII version 1.3 s User programmable GMII pin ordering s IEEE 802.3u , -T RJ-45 DP83820 MAGNETICS MII GMII RGMII STATUS LEDs PHYTER® is a registered , / GMII / RGMII INTERFACE GTX_CLK TX_ER TX_EN TXD[7:0] TX_CLK RX_CLK COL CRS RX_ER RX_DV RXD


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PDF DP83865 DP83865 SNLS165B 10BASE-T, 100BASE-TX 1000BASE-T DP83861
2004 - LF9203

Abstract: NCH089B3 DP83865DVH TG1G RGMII RGMII 3COM PAM-5 ACSHL-25 auto tran 600 DP83820
Text: - HP 1 1 = RGMII - 3COM COLLISION DETECT: Asserted high to indicate detection of a , IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII ( RGMII ). The DP83865 is a , : IEEE 802.3u MII IEEE 802.3z GMII RGMII version 1.3 User programmable GMII pin ordering IEEE , -45 DP83820 MAGNETICS MII GMII RGMII STATUS LEDs PHYTER® is a registered trademark of National , ® V 10/100/1000 Ethernet Physical Layer October 2004 COMBINED MII / GMII / RGMII INTERFACE


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PDF DP83865 10BASE-T, 100BASE-TX 1000BASE-T DP83861 DP83891. LF9203 NCH089B3 DP83865DVH TG1G RGMII RGMII 3COM PAM-5 ACSHL-25 auto tran 600 DP83820
2004 - RGMII 3COM

Abstract: TG1G LF9203 duplex-led DP83865DVH CSP-9-111C2 BCM 100BASE full duplex ACSHL-25 1000BASE-T-FD 0x1213
Text: 1 COL/CLK_MAC_FREQ O_Z, S, PD 39 0 1 0 1 MAC Interface = GMII = GMII = RGMII - HP = RGMII - 3COM , (GMII), or Reduced GMII ( RGMII ). The DP83865 is a fourth generation Gigabit PHY with field proven , X3.T12 3.3 V or 2.5 V MAC interfaces: IEEE 802.3u MII IEEE 802.3z GMII RGMII version 1.3 User , SYSTEM DIAGRAM MII GMII RGMII 10BASE-T 100BASE-TX 1000BASE-T RJ-45 DP83820 10/100/1000 Mb/s ETHERNET , MII / GMII / RGMII INTERFACE µC MGMT & PHY CNTRL MII 100BASE-TX Block MII 100BASE-TX PCS


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PDF DP83865 DP83865 SNLS165B 10BASE-T, 100BASE-TX 1000BASE-T RGMII 3COM TG1G LF9203 duplex-led DP83865DVH CSP-9-111C2 BCM 100BASE full duplex ACSHL-25 1000BASE-T-FD 0x1213
2015 - TJA1145

Abstract: INA3221
Text: Texas Instruments DP83865 PHY. It is configured to operate in RGMII-3COM mode. The PHY supports 10BASE , /100 Mbps (interfacing through RMII) or 1 Gbps (interfacing through RGMII ). It supports IEEE 1588 and , to UART FTDI232RQ EMAC0 RGMII interface enabled EMAC1 RMII interface enabled SPI Flash


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PDF ADSP-SC589 ERJ-2RKF8661X 1/10W ERJ-2RKF5101X ERJ-2RKF4301X TJA1145 INA3221
2009 - rgmii specification

Abstract: RGMII delay RGMII RGMII version 2.0 specification
Text: KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support Revision 1.2 General Description , twisted pair (UTP) cable. The KSZ9021RL provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at , Information). • Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet Transceiver • RGMII interface compliant to RGMII Version 1.3 • RGMII I/Os with 3.3V/2.5V tolerant and programmable timings


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PDF KSZ9021RL/RN KSZ9021RL 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps rgmii specification RGMII delay RGMII RGMII version 2.0 specification
2003 - 88E1111 RGMII

Abstract: Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
Text: Application Note: Virtex-II, Virtex-II Pro Using the RGMII to Interface with the Gigabit , Gigabit Media Independent Interface ( RGMII ) is an alternative to the Gigabit Media Independent Interface (GMII). In this application note, an RGMII adaptation module is used to reduce the number of pins required to connect the Gigabit Ethernet MAC to a Gigabit PHY from 24 to 12. The RGMII achieves this 50 , This application note shows how to combine an RGMII adaptation module with the GMII configuration of


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PDF XAPP692 DS200, 1000BASE-X) 88E1111 RGMII Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
2010 - RGMII constraints

Abstract: RGMII delay rgmii timing RGMII phy fpga rgmii RGMII altddio_in rgmii specification altddio_out
Text: AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs © January 2010 AN-477-2.0 This application note describes how to design a reduced gigabit media independent interface ( RGMII ) with Stratix® , Arria® , and Cyclone® FPGAs and HardCopy® ASICs. RGMII is an alternative to the IEEE , with RGMII , Synopsys design constraints (SDC), and the TimeQuest Timing Analyzer before you read this application note. System-Level Diagram Figure 1 shows a block diagram of RGMII implementation. An RGMII


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PDF AN-477-2 RGMII constraints RGMII delay rgmii timing RGMII phy fpga rgmii RGMII altddio_in rgmii specification altddio_out
2008 - RGMII Layout Guide

Abstract: 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
Text: . 21 Appendix A TCI6486/C6472 RGMII 1.5-V/1.8-V-to-2.5-V/3.3-V Translation , . RGMII PHY Connectivity Diagram . RGMII Switch Connectivity Diagram , . RGMII Voltage Level Translation Circuit , . TCI6486/C6472 RGMII Port Signals


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PDF TMS320C6472/TMS320TCI6486 TMS320TCI6486/TMS320C6472 TCI6486/C6472 TMS320C6472/TMS320TCI6486 RGMII Layout Guide 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
RGMII

Abstract: GMII fpga rgmii RGMII constraints 0809 timing diagram isplever LFXP10 RGMII to RGMII
Text: RGMII to GMII Bridge April 2005 Reference Design RD1022 Introduction GMII (Gigabit Media Independent Interface) is an Ethernet interface standard, and RGMII (Reduced Gigabit Media Independent Interface) is intended to be an alternative to GMII. The principle objective of RGMII is to reduce the , design provides a bi-directional bridge function for transferring data between RGMII and GMII. Features · Data bridging from GMII to RGMII · Data bridging from RGMII to GMII · Works at >125MHz with


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PDF RD1022 125MHz 1-800-LATTICE RGMII GMII fpga rgmii RGMII constraints 0809 timing diagram isplever LFXP10 RGMII to RGMII
2008 - hifn 8450

Abstract: 1.5V RGMII hsbga 324 HSBGA hifn encryption express sgmii sfp tcam ip cores hifn lzs AN0145 IBM PCI Express serdes architecture
Text: GMAC GMII/TBI Pin Descriptions (Host-side Only) . . . . . . . . . 37 39 Host GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . . . . 39 Host GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . . . . 40 Host GMAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . . . 42 43 Network GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . 43 Network GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . 44 Network MAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . 46 48 GMAC


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PDF DS-0131-06, DS-0131-06 hifn 8450 1.5V RGMII hsbga 324 HSBGA hifn encryption express sgmii sfp tcam ip cores hifn lzs AN0145 IBM PCI Express serdes architecture
2009 - rgmii specification

Abstract: marvell ethernet switch mii RGMII AN3811 RGMII delay MSC8144 MSC8144E MSC8144EC marvell ethernet switch
Text: DSP for the specific interface and processing configuration (MII, RMII, SMII, RGMII , or SGMII mode , the Reduced Gigabit Media Independent Interface ( RGMII ). The application note does not reproduce the , must research and develop a general understanding of the general principles of RGMII and the other , . Contents Ethernet Timing Related Specifications . . . . . . . . . . . 2 RGMII . . . . . . . . . . . . . . , delay and skew as they are written in the standards for MII, RMII, SMII, and RGMII . As noted in the


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PDF AN3811 MSC8144 rgmii specification marvell ethernet switch mii RGMII AN3811 RGMII delay MSC8144E MSC8144EC marvell ethernet switch
2009 - ML605 UCF FILE

Abstract: iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
Text: attributes based on user options Provides user-configurable Ethernet MAC physical interfaces · Supports RGMII v1.3, RGMII v2.0, SGMII, and 1000BASE-X PCS/PMA interfaces, as well as GMII/MII at 2.5V only , RGMII SGMII PCS PMA 1000BASE-X PMD Figure 1: Typical Ethernet Architecture Figure 1 displays , (UG368). RGMII The Reduced-GMII ( RGMII ) is an alternative to GMII/MII. RGMII achieves a 50-percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII


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PDF DS710 ML605 UCF FILE iodelay virtex-6 ML605 user guide switch SGMII MII GMII RAMB36s example ml605 ethernet fpga rgmii 1000base-x xilinx 1000BASE-X sfp sgmii RGMII to SGMII
2005 - VSC8641XKO-03

Abstract: VSC8641XKO VSC8641 hp laptop MOTHERBOARD pcb CIRCUIT diagram router board 433 circuit diagram for ethernet VSC8641KO marvell ethernet switch sgmii VSC8641XJF VSC8641XK RGMII
Text: VSC8641 10/100/1000BASE-T PHY with RGMII and GMII MAC Interface Datasheet VMDS , . 20 3.2.2 RGMII MAC Interface Mode , . 64 4.3.12 RGMII Skew Control , . 95 6.2.2 GMII/ RGMII MAC Interface , . 105 6.6.2 GMII/ RGMII MAC Interface


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PDF VSC8641 10/100/1000BASE-T VMDS-10211 88-pin, VSC8641XKO 100-pin, VSC8641XKO-03 VSC8641XJF VSC8641XKO-03 VSC8641XKO VSC8641 hp laptop MOTHERBOARD pcb CIRCUIT diagram router board 433 circuit diagram for ethernet VSC8641KO marvell ethernet switch sgmii VSC8641XJF VSC8641XK RGMII
2009 - KSZ9021RN

Abstract: KSZ9021 ksz9021rl KSZ9021RNI RGMII rgmii specification TLA-7T101LF rgmii timing KSZ9021RLI fpga rgmii
Text: KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support General Description Features , pair (UTP) cable. The KSZ9021RL provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at 10/100 , /1000Mbps IEEE 802.3 compliant Ethernet Transceiver · RGMII interface compliant to RGMII Version 1.3 · RGMII I/Os with 3.3V/2.5V tolerant and programmable timings to adjust and correct delays on both Tx and


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PDF KSZ9021RL/RN KSZ9021RL 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps M9999-101309-1 KSZ9021RN KSZ9021 KSZ9021RNI RGMII rgmii specification TLA-7T101LF rgmii timing KSZ9021RLI fpga rgmii
2012 - RGMII version 2.0 specification

Abstract: No abstract text available
Text: KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Revision 2.0 General Description , twisted pair (UTP) cable. The KSZ9031RNX provides the reduced Gigabit media independent interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at , €¢ Single-chip 10/100/1000Mbps IEEE 802.3-compliant Ethernet transceiver • RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making


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PDF KSZ9031RNX KSZ9031RNX 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps. RGMII version 2.0 specification
2012 - ksz9031

Abstract: KSZ9031RNXIA KSZ9031RNX 73d15 KSZ9021RN KSZ9031RN KSZ9031RNXCA JK0-0136NL KSZ9031RNXCC TG1G-S001NZ
Text: KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Data Sheet Rev. 1.0 General , ) cable. The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface ( RGMII ) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps , IEEE 802.3 compliant Ethernet transceiver · RGMII timing supports on-chip delay according to RGMII , RX timing paths · RGMII with 3.3V/2.5V/1.8V tolerant I/Os · Auto-negotiation to automatically select


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PDF KSZ9031RNX KSZ9031RNX 10Base-T/100Base-TX/1000Base-T) 10/100/1000Mbps. KSZ90. M9999-103112-1 ksz9031 KSZ9031RNXIA 73d15 KSZ9021RN KSZ9031RN KSZ9031RNXCA JK0-0136NL KSZ9031RNXCC TG1G-S001NZ
2013 - rgmii specification ieee

Abstract: LAN8820i
Text: LAN8820/LAN8820i RGMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT , specification at 10/100/1000 Mbps operation Miniature 56-pin QFN lead-free RoHS compliant package with RGMII , detection Vendor specific register functions Supports reduced pin count RGMII interface – Controlled impedance outputs – Supports RGMII ID mode Four status LED outputs and configurable LED modes with support for tricolor operation Compliant with IEEE 802.3-2005 standards – RGMII pins tolerant to 3.6V


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PDF LAN8820/LAN8820i 1000BASE-T) 802-3/IEEE 10BASE-T) 56-pin rgmii specification ieee LAN8820i
2012 - MAX24287

Abstract: RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
Text: configured for GMII, RGMII , TBI, RTBI, or 10/100 MII, while the serial interface can be configured for , -, 6-, or 8-Pin) Parallel Interface Configurable as GMII, RGMII , TBI, RTBI, or 10/100 MII Serial , and Duplex Mode Negotiation Between MDIO and SGMII PCS Supports 10/100 MII or RGMII , Applications Any System with a Need to Interface a Component with a Parallel MII Interface (GMII, RGMII , TBI , . 23 PARALLEL INTERFACE ­ GMII, RGMII , TBI, RTBI, MII


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
2008 - RGMII Layout Guide

Abstract: No abstract text available
Text: RGMII /RTBI Interface Usage . . . . . . . . . . . . . . . . . . 41 6.2.2.1 Host GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . . . . 41 6.2.2.2 Host GMAC RGMII /RTBI Connection Diagrams . . . . . . . . . . . . 42 6.2.2.3 Host GMAC RGMII /RTBI Pin Descriptions . . . . . . . . . . . . . . . . 44 6.2.3 Network GMAC RGMII /RTBI Interface Usage . . . . . . . . . . . . . . . 46 6.2.3.1 Network GMAC RGMII /RTBI Pin Mappings . . . . . . . . . . . . . . . 46 6.2.3.2


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PDF DS-0142-C, DS-0142-C RGMII Layout Guide
2004 - RGMII

Abstract: HSTL RGMII switch RGMII 2-channel switch SM 933 RGMII switch rgmii hstl TO lvcmos PM8373 PM8363 PM8364 24xFE
Text: 1.5 V and 1.8 V RGMII /RTBI interface. · 1.8 V and 2.5 V LVCMOS interoperable for all other digital I , Rate Interface compliant with RGMII /RTBI v2.0 standard. · Receive channel output clocks eliminate the need for PLLs in interface ASICs. · 1.5 V and 1.8 V HSTL interoperable on RGMII /RTBI digital I , PCS RTBI Mode RXDy[3:0] Receive RGMII W/O CTC PCS _SM RxCTLy RxFIFO RXCKy RGMII & , RGMII RGMII 6 Backplane PM8364 DualPHY 1GR Optics Optics Connector 24xFE + 1GE


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PDF PM8364 8B/10B PMC-2040187 RGMII HSTL RGMII switch RGMII 2-channel switch SM 933 RGMII switch rgmii hstl TO lvcmos PM8373 PM8363 PM8364 24xFE
2010 - AR8033

Abstract: AR8031 AR8035 AR-8031 atheros ethernet switch AR8030 Atheros ar8035 RGMII to SGMII ATHEROS AR80 AR8031-11-29-10
Text: AR8031 Ultra low-power 10/100/1000 RGMII /SGMII Gigabit Ethernet Transceiver Technology Overview , consumers and businesses. Solution Highlights AR8031 Product Overview · SGMII and RGMII MAC , PHY. It supports both RGMII and SGMII interfaces to the MAC. The AR8031 provides a low-power, low BOM , RGMII / SGMII RGMII / SGMII TRD[0:3] Hybrid Circuit PGA AGC PMA The AR8031 also supports , on both the MAC interfaces ( RGMII /SGMII) and the line side. ADC Trellis Decoder Timing and


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PDF AR8031 AR8031-11-29-10 AR8033 AR8031 AR8035 AR-8031 atheros ethernet switch AR8030 Atheros ar8035 RGMII to SGMII ATHEROS AR80 AR8031-11-29-10
2007 - sgmii sfp virtex

Abstract: UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl DS307 1000BASE-X RGMII SGMII
Text: the EMAC0/EMAC1 tie-off pins based on user options - Supports MII, GMII, RGMII v1.3, RGMII v2 , FIFO I/F Ethernet MAC PCS GMII/MII RGMII SGMII (RocketIO) PMD PMA 1000BASE , , and as a result, GMII/MII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1 Gbps. RGMII The Reduced-GMII ( RGMII ) is an alternative to the GMII/MII. RGMII achieves a 45 percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII is preferred over GMII by


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PDF DS307 1000BASE-X sgmii sfp virtex UCF virtex-4 1000base-x xilinx 1000BASE-X sfp sgmii sgmii mode sfp fpga ethernet sgmii xilinx tcp vhdl RGMII SGMII
2011 - MAX24287

Abstract: RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
Text: configured for GMII, RGMII , TBI, RTBI, or 10/100 MII, while the serial interface can be configured for , Interface a Component with a Parallel MII Interface (GMII, RGMII , TBI RTBI, 10/100 MII) to a Component , GMII, RGMII , TBI, RTBI, or 10/100 MII Serial Interface Has Clock and Data Recovery Block (CDR , MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate , . 23 PARALLEL INTERFACE ­ GMII, RGMII , TBI, RTBI, MII


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PDF MAX24287 MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
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