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Part Manufacturer Description Datasheet Download Buy Part
ISL26132AVZ Intersil Corporation Low-Noise 24-bit Delta Sigma ADC; TSSOP24; Temp Range: -40° to 105°C
ISL26132AVZ-T Intersil Corporation Low-Noise 24-bit Delta Sigma ADC; TSSOP24; Temp Range: -40° to 105°C
ISL6132IRZA Intersil Corporation Multiple Voltage Supervisory ICs; QFN24; Temp Range: -40° to 85°C
ISL6132IRZA-T Intersil Corporation Multiple Voltage Supervisory ICs; QFN24; Temp Range: -40° to 85°C
ISL6132IR Intersil Corporation 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, PLASTIC, MO-220VGGD-2, QFN-24
ISL6132IR-T Intersil Corporation 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, PLASTIC, MO-220VGGD-2, QFN-24

RDA 6132 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - ethernet hub

Abstract: NIDAQ SCXI-1000 SCXI-1100
Text: With RDA , you can acquire data over a network using a National Instruments DAQ board installed in a remote computer. Because the underlying network protocol used by RDA is TCP/IP, you can use the Internet if it is available to both computers. RDA can also be used on any existing local area network (LAN , administrator to properly install all computers on your network. RDA is implemented at the NI-DAQ driver level. With RDA , you can run applications on your computer (the RDA Client) that uses National Instruments


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1998 - NIDAQ

Abstract: SCXI-1000 SCXI-1100
Text: existing programming investment to install a remote data acquisition system. RDA works on every product controlled by NI-DAQ for Windows. The term RDA Client refers to the computer in front of you. This computer , not need to have any DAQ hardware installed. The term RDA Server refers to the computer elsewhere on , need any application software installed. What Can I Do with RDA ? Basically, you can do anything with a DAQ board installed in an RDA Server elsewhere on your network that you can do with it


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2007 - SST89E58RDA-40-C-PIE

Abstract: f310 T1440
Text: FlashFlex MCU SST89E54RD2A/ RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A/ RDA Data Sheet , DESCRIPTION The SST89E5xRD2A/ RDA and SST89V5xRD2A/ RDA are members of the FlashFlex family of 8 , change without notice. FlashFlex MCU SST89E54RD2A/ RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A/ RDA Data Sheet TABLE OF CONTENTS FEATURES: . . . . . . . . . . . . . . . . . . . . . . . . . , -01-000 2 1/07 FlashFlex MCU SST89E54RD2A/ RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A


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PDF SST89E54RD2A/RDA SST89E58RD2A/RDA SST89V54RD2A/RDA SST89V58RD2A/RDA 8051-Compatible SST89E5xRD2A SST89V5xRD2A 128-Byte 40-contact S71339-01-000 SST89E58RDA-40-C-PIE f310 T1440
TC59LM818DMG-33

Abstract: P-BGA60-0917-1
Text: CL = 6 IRC 200 CL = 4 ns IRCD RDA /WRA ­ LAL () IRAS LAL ­ RDA /WRA () IRBD () IRWD RDA LAL ­ WRA () IWRD WRA LAL ­ RDA () IRSC IPD PD , cycle IREFC ICKD REF ­ () ILOCK DLL ( RDA ) Rev 1.4 2005-10-19 9/57 , Command DESL RDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code , DS/QS mode tCH tCL tCK CLK CLK tIS tIH LAL (after RDA ) Input (control & addresses


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PDF TC59LM818DMG-33 TC59LM818DMG 300MHz 15MIN TC59LM818DMB 333MHz P-BGA60-0917-1
TC59LM818DMB

Abstract: TC59LM818DMB-33
Text: CL = 6 IRC 200 CL = 4 ns IRCD RDA /WRA ­ LAL () IRAS LAL ­ RDA /WRA () IRBD () IRWD RDA LAL ­ WRA () IWRD WRA LAL ­ RDA () IRSC IPD PD , cycle IREFC ICKD REF ­ () ILOCK DLL ( RDA ) Rev 1.4 2005-10-19 9/57 , Command DESL RDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code , DS/QS mode tCH tCL tCK CLK CLK tIS tIH LAL (after RDA ) Input (control & addresses


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PDF TC59LM818DMB-33 TC59LM818DMB 300MHz 333MHz 666Mbps TC59LM818DMB
2006 - Not Available

Abstract: No abstract text available
Text: FlashFlex51 MCU SST89E54RD2A/ RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A/ RDA SST89E , (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST89E5xRD2A/ RDA and SST89V5xRD2A/ RDA are , / RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A/ RDA Data Sheet TABLE OF CONTENTS FEATURES , ©2006 Silicon Storage Technology, Inc. S71339-00-000 12/06 2 FlashFlex51 MCU SST89E54RD2A/ RDA / SST89E58RD2A/ RDA SST89V54RD2A/ RDA / SST89V58RD2A/ RDA Data Sheet 9.2 SoftLock . . . . . . . . . . . . . . . . .


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PDF FlashFlex51 SST89E54RD2A/RDA SST89E58RD2A/RDA SST89V54RD2A/RDA SST89V58RD2A/RDA SST89E/V58 52RD2/RD 8051-Compatible SST89E5xRD2A
MB81116420

Abstract: No abstract text available
Text: With Auto Precharge 6 RDA H X L H L H X H V Write 6 WR H , , and RDA commands should only be issued after the corresponding bank has been activated (ACTV command). , X BA, CA, A10 BA, CA, A10 BA, RA Symbol DESL NOP RD/ RDA WR/WRA ACTV Function NOP NOP llleagal , PRE/PALL REFR/SREN MRS/MRR TEST DESL NOP RD/ RDA WR/WRA ACTV PRE/PALL REFR/SREN MRS/MRR TEST DESL NOP RD/ RDA WR/WRA ACTV PRE/PALL REFR/SREN MRS Function NOP Auto Refresh or Self Refresh Mode Register


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PDF 152-WORDS MB81116420 JV0082-947J4
2005 - Not Available

Abstract: No abstract text available
Text: Read/Write Cycle Time (applicable to same bank) RDA /WRA to LAL Command Input Delay (applicable to same bank) LAL to RDA /WRA Command Input Delay (applicable to same bank) Random Bank Access Delay (applicable to other bank) LAL following RDA to WRA Delay (applicable to other bank) LAL following WRA to RDA , Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (applicable to RDA command) Rev , lREFC lREFC Command DESL RDA MRS DESL RDA MRS DESL WRA REF DESL WRA REF DESL


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PDF TC59LM913AMB-50 512Mbits 304-WORDS 16-BITS TC59LM913AMB
2005 - TC59LM913AMB-50

Abstract: BGA64 TC59LM913AMB
Text: RDA /WRA to LAL Command Input Delay (applicable to same bank) 1 1 IRAS LAL to RDA /WRA , to other bank) 2 LAL following RDA to WRA Delay (applicable to other bank) BL = 2 2 IRWD BL = 4 3 ns 3 3 5 µs cycle IWRD LAL following WRA to RDA Delay , (applicable to RDA command) 200 Rev 1.1 2005-11-08 9/46 TC59LM913AMB-50 AC TEST CONDITIONS , PD lPDA Command 200clock cycle(min) DESL RDA MRS DESL op-code RDA MRS DESL WRA


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PDF TC59LM913AMB-50 512Mbits 304-WORDS 16-BITS TC59LM913AMB TC59LM913AMB-50 BGA64
1990 - TC59LM836DKB

Abstract: TC59LM836DKB-33
Text: IRCD RDA /WRA ­ LAL () 1 1 1 1 CL = 4 4 4 IRAS LAL ­ RDA /WRA () CL = 5 5 5 CL = 6 6 6 IRBD () 2 2 RDA LAL ­ , 7 7 CL = 5 7 7 CL = 6 7 7 IWRD WRA LAL ­ RDA , DLL ( RDA ) Rev 1.4 2005-11-08 10/65 TC59LM836DKB-33,-40 AC , lREFC lREFC lLOCK = 200clock cycle(min) lPDA Command DESL RDA MRS DESL op-code RDA


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PDF TC59LM836DKB-33 TC59LM836DKB 36bit TC59LM836DKB 36DKB-33 TC59LM836DMB 333MHz
LA2 DT2

Abstract: BA2A1 LAL 2.25 BGA64 TC59LM906AMG TC59LM906AMG-37 Off Chip Driver
Text: tPAUSE 200 IRC /() 6 IRCD RDA /WRA-LAL () 1 LAL-RDA/WRA () 5 () 2 2 3 5 () µs RDA LAL-WRA BL = 2 3 IRBD 3 1 IRAS ns , ILOCK DLL ( RDA ) 200 cycle Rev 1.1 2005-11-08 9/47 TC59LM906AMG-37 AC , DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code Address EMRS MRS , TC59LM906AMG-37 (Burst Length = 4) tCH tCL tCK CLK CLK tIS tIH LAL (after RDA ) Input


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PDF TC59LM906AMG-37 TC59LM906AMG TC59LM906-37 P-BGA64-1317-1 030519TBA LA2 DT2 BA2A1 LAL 2.25 BGA64 TC59LM906AMG TC59LM906AMG-37 Off Chip Driver
2005 - toshiba cnc

Abstract: TC59LM836DKG-30
Text: 7 7 7 IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank , 7 5 2 µs CL = 6 3 IRAS 3 1 LAL to RDA /WRA Command Input , ) IRWD LAL following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA , Lock-on Time (applicable to RDA command) 200 200 200 cycle Rev 1.3 2005-03-07 , lREFC lLOCK = 200clock cycle(min) lPDA Command DESL RDA MRS DESL op-code RDA MRS DESL


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PDF TC59LM836DKG-30 288Mbits 152-WORDS 36-BITS TC59LM836DKG toshiba cnc
2003 - LAL 2.25

Abstract: K4C89183AF 19Cycles
Text: - CL = 6 7 - 7 - 7 - IRC 3 5 us IRCD RDA /WRA to LAL Command Input Delay (Applicable to Same Bank) IRAS LAL to RDA /WRA Command Input Delay (Applicable to Same Bank) IRBD Random Bank Access Delay (Applicable to Other Bank) IRWD LAL following RDA to WRA Delay (Applicable to Other Bank) IWRD LAL following WRA to RDA Delay (Applicable to Other Bank) IRSC 3 , DLL Lock-on Time (Applicable to RDA command) - 11 - REV. 0.3 Nov. 2003 Target K4C89183AF


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PDF K4C89183AF 288Mb 800Mbps 400Mhz) 8K/32ms 667Mbps/pin 333MHz, 600Mbps 300MHz, LAL 2.25 K4C89183AF 19Cycles
2003 - Not Available

Abstract: No abstract text available
Text: Ž¯ IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) IRAS LAL to RDA /WRA Command , ) IRWD LAL following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA , Command to Clock Input Disable at Self-Refresh Entry ILOCK DLL Lock-on Time (applicable to RDA , lRSC lRSC lREFC lREFC PD lLOCK = 200clock cycle(min) Command DESL RDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code Address EMRS MRS DQ


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PDF TC59LM818DMBI-37 304-WORDS 18-BITS TC59LM818DMBI
2011 - SST89E58RDA

Abstract: 89V58RD2
Text: . FlashFlex MCU A Microchip Technology Company SST89E54RD2A/ RDA / SST89E58RD2A/ RDA Not Recommended for New Designs The SST89E54RD2A/ RDA and SST89E58RD2A/ RDA are members of the FlashFlex family of 8 , . www.microchip.com DS25114A 12/11 FlashFlex MCU A Microchip Technology Company SST89E54RD2A/ RDA / SST89E58RD2A/ RDA Not Recommended for New Designs Product Description The SST89E54RD2A/ RDA and SST89E58RD2A/ RDA are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured


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PDF SST89E54RD2A/RDA SST89E58RD2A/RDA SST89E58RD2A/RDA 8051-Compatible DS25114A SST89E58RDA 89V58RD2
2005 - TC59LM836DKB

Abstract: TC59LM836DKB-33
Text: 7 7 IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) 1 1 , 5 2 µs CL = 6 3 IRAS 3 1 LAL to RDA /WRA Command Input Delay , following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA Delay , Time (applicable to RDA command) 200 200 cycle Rev 1.4 2005-11-08 10/65 , lREFC lLOCK = 200clock cycle(min) lPDA Command DESL RDA MRS DESL op-code RDA MRS DESL


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PDF TC59LM836DKB-33 288Mbits 152-WORDS 36-BITS TC59LM836DKB
2003 - Not Available

Abstract: No abstract text available
Text: RDA /WRA to LAL Command Input Delay (Applicable to Same Bank) IRAS LAL to RDA /WRA Command Input , (Applicable to Other Bank) LAL following RDA to WRA Delay (Applicable to Other Bank) LAL following WRA to RDA , Time (Applicable to RDA command) IREFC 200 - IREFC 200 - IREFC 200 - IREFC 200 , PD 200 clock cycle(min) Command DESL RDA MRS DESL RDA MRS DESL , LAL (after RDA ) DESL CAS latency = 4 LQS/UQS (Output) Low tCKQS DQ (Output) High-Z Q0 tAC


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PDF K4C89363AF 800Mbps 8K/32ms 800Mbps/pin 400MHz, 667Mbps/pin 333MHz, 533Mbps 266MHz,
2005 - TC59LM818DMG-33

Abstract: No abstract text available
Text: CL = 6 7 7 IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) IRAS LAL to RDA /WRA Command Input Delay (applicable to same bank) IRBD IRWD IWRD IRSC Random Bank Access Delay (applicable to other bank) LAL following RDA to BL = 2 WRA Delay (applicable to other BL = 4 bank) LAL following WRA to RDA Delay (applicable to other bank) Mode Register , Command to Clock Input Disable at Self-Refresh Entry ILOCK DLL Lock-on Time (applicable to RDA


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PDF TC59LM818DMG-33 288Mbits 304-WORDS 18-BITS TC59LM818DMG
2004 - TC59LM818DMB

Abstract: TC59LM818DMB-30
Text: IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 4 LAL to RDA /WRA Command Input Delay CL = 5 (applicable to same bank) CL = 6 4 4 , Access Delay (applicable to other bank) IRWD LAL following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA Delay (applicable to other bank) IRSC Mode Register , Self-Refresh Entry IREFC IREFC IREFC ILOCK DLL Lock-on Time (applicable to RDA


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PDF TC59LM818DMB-30 288Mbits 304-WORDS 18-BITS TC59LM818DMB
2002 - Not Available

Abstract: No abstract text available
Text: 4 3 1 CL = 4 7 CL = 5 7 3 5 tREFI ns IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) IRAS LAL to RDA /WRA Command Input , LAL following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA Delay , Self-Refresh Entry ILOCK DLL Lock-on Time (applicable to RDA command) 2002-05-30 8/54 , ) Command DESL RDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code


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PDF TC59LM818DMGI-40 304-WORDS 18-BITS TC59LM818DMGI
2002 - TC59LM818DMG-30

Abstract: TC59LM8
Text: 7 7 7 IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 4 LAL to RDA /WRA Command Input Delay CL = 5 (applicable to , Random Bank Access Delay (applicable to other bank) IRWD LAL following RDA to B = 2 L WRA Delay (applicable to other BL = 4 bank) IWRD LAL following WRA to RDA Delay (applicable to other bank , (applicable to RDA command) 200 200 200 2002-05-15 8/54 TC59LM818DMG-30,-33


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PDF TC59LM818DMG-30 304-WORDS 18-BITS TC59LM818DMG TC59LM818DMG TC59LM8
2002 - Not Available

Abstract: No abstract text available
Text: Notes 3, 6, 8 3, 7, 8 3 3 5 us 1 2 Cycle IR C IRCD RDA /WRA to LAL Command Input Delay (Applicable to Same Bank) IRAS LAL to RDA /WRA Command Input Delay (Applicable to Same Bank) Random Bank Access Delay (Applicable to Other Bank) LAL following RDA to WRA Delay (Applicable to Other Bank) LAL following WRA to RDA Delay (Applicable to Other Bank) CL = 5 CL = 6 IRBD IRWD IWRD IRSC Mode , Input Disable at Self-Refresh Entry DLL Lock-on Time (Applicable to RDA command) I REFC 200 I


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PDF K4C89183AF 304-WORDS 18-BITS K4C89183AF 8K/32ms
2004 - Not Available

Abstract: No abstract text available
Text: 0.4 200 5 6 7 1 4 5 6 2 ns 3 1 1.95 µs 5 IRC IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) LAL to RDA /WRA Command Input Delay (applicable to same bank) Random Bank Access Delay (applicable to other bank) LAL following RDA to WRA Delay (applicable to other bank) BL = 2 , following WRA to RDA Delay (applicable to other bank) CL = 4 CL = 5 CL = 6 cycle IRSC Mode Register , Time (applicable to RDA command) Rev 1.0 2004-02-25 9/54 TC59LM818DMBI-37 AC TEST CONDITIONS


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PDF TC59LM818DMBI-37 288Mbits 304-WORDS 18-BITS TC59LM818DMBI
MB81116820-010

Abstract: MB81116420
Text: RDA H X L H L H X H V Write 6,10 WR H X L H L L , . 5. NOP and DESL commands have the same effect on the part. 6. WR, WRA, RD, and RDA commands should , X H H H L X H L L H X H H L H Addr X X BA, CA, A10 BA, CA, A10 BA, RA Symbol DESL NOP RD/ RDA , /PALL REFR/SREN MRS/MRR TEST DESL NOP RD/ RDA WR/WRA ACTV PRE/PALL REFR/SREN MRS/MRR TEST DESL NOP - , L H L H L H L H L RD/ RDA WR/WRA ACTV PRE/PALL REFR/SREN MRS 6 MB81116820


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PDF MB81116820-010 576-WORDS MB81116820 MB81116420 JV0069-947J4
2004 - LA2 DT2

Abstract: BGA64 TC59LM906AMG TC59LM914AMG
Text: 6 IRCD RDA /WRA to LAL Command Input Delay (applicable to same bank) IRAS LAL to RDA , to other bank) IRWD LAL following RDA to WRA Delay (applicable to other bank) IWRD LAL following WRA to RDA Delay (applicable to other bank) IRSC Mode Register Set Cycle Time IPD PD , Self-Refresh Entry ILOCK DLL Lock-on Time (applicable to RDA command) Rev 1.0 2004-08-20 10/59 , lRSC lREFC lREFC PD 200clock cycle(min) Command DESL RDA MRS DESL op-code RDA


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PDF TC59LM914/06AMG-37 512Mbits 304-WORDS 16-BITS 608-WORDS TC59LM914/06AMG TC59LM914AMG TC59LM906AMG LA2 DT2 BGA64
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