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Part Manufacturer Description Datasheet Download Buy Part
LTC1597BCN#TR Linear Technology IC PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDIP28, 0.300 INCH, PLASTIC, DIP-28, Digital to Analog Converter
LTC1597AIN#TR Linear Technology IC PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDIP28, 0.300 INCH, PLASTIC, DIP-28, Digital to Analog Converter
LTC1591IN#TRPBF Linear Technology IC PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDIP28, LEAD FREE, PLASTIC, DIP-28, Digital to Analog Converter
LTC1591-1CN#TR Linear Technology IC PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDIP28, PLASTIC, DIP-28, Digital to Analog Converter
LTC1591CN#TR Linear Technology IC PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDIP28, PLASTIC, DIP-28, Digital to Analog Converter
LTC1450G24 Linear Technology IC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, PDSO24, SSOP-24, Digital to Analog Converter

RAM 2112 256 word Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2011 - LCMXO2-256 pinout

Abstract: No abstract text available
Text: -1200 256 640 640 1280 1280 2112 2112 4320 6864 Distributed RAM (Kbits) EBR SRAM , Programmable Function Units with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , devices with 256 to 6864 LUT4s and ï€ 19 to 335 I/Os  Ultra Low Power Devices • • • â , RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash


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PDF DS1035 DS1035 LCMXO2-256 pinout
2014 - Not Available

Abstract: No abstract text available
Text: Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , Selection Guide XO2- 256 XO2-640 XO2-640U1 256 640 640 1280 1280 2112 2112 , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , and MachXO2-640/U are similar to , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to


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PDF DS1035 DS1035 XO2-2000 LCMXO2-2000ZE-1UWG49CTR LCMXO2-2000ZE-1UWG49ITR
2014 - Not Available

Abstract: No abstract text available
Text: Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , Selection Guide XO2- 256 XO2-640 XO2-640U1 256 640 640 1280 1280 2112 2112 , with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , and MachXO2-640/U , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to


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PDF DS1035 DS1035 XO2-2000 LCMXO2-2000ZE-1UWG49CTR LCMXO2-2000ZE-1UWG49ITR
2013 - Not Available

Abstract: No abstract text available
Text: Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , . The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 MachXO2-4000HE
2013 - Not Available

Abstract: No abstract text available
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 0A-13.
2014 - Not Available

Abstract: No abstract text available
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , and MachXO2-640/U are similar to , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to


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PDF DS1035 DS1035 LCMXO2-2000ZE-1UWG49ITR UWG49 LCMXO2-2000ZE-1UWG49CTR
2013 - Not Available

Abstract: No abstract text available
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 MachXO2-4000HE
2012 - LCMXO2-4000

Abstract: LCMX02 LCMX02 1200 LCMXO2 640HC MACHXO2 7000 pinout file LCMXO2-4000HC MachXO2 LCMXO2-7000HC LCMXO2-1200HC-4TG100C LCMXO2-1200HC-4TG100
Text: multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up to 256 Kbits of User Flash Memory · 100,000 write cycles · Accessible through WISHBONE, SPI, I2C and


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PDF DS1035 DS1035 TN1200. LCMXO2-1200ZE1UWG25ITR50. LCMXO2-1200ZE-1UWG25ITR. LCMXO2-4000 LCMX02 LCMX02 1200 LCMXO2 640HC MACHXO2 7000 pinout file LCMXO2-4000HC MachXO2 LCMXO2-7000HC LCMXO2-1200HC-4TG100C LCMXO2-1200HC-4TG100
2013 - LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 MachXO2-4000HE LCMXO2-256 pinout LCMXO2-2000 pinout
2011 - LCMX02

Abstract: LCMX02 1200 LCMXO2-1200HC-4TG144C LCMXO2-4000HC LCMXO2-1200HC-4MG132C lcmxo2-1200 LCMXO2-7000HC LCMXO2-640HC-4TG100C TQFP-144 footprint LCMX02-2000
Text: -7000 256 640 640 1280 1280 2112 2112 4320 6864 Distributed RAM (Kbits) EBR SRAM , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , and MachXO2-640/U are similar to , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , frequency range (10 MHz to 400 MHz) Flexible Logic Architecture · Six devices with 256 to 6864 , Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM ·


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PDF DS1035 DS1035 MachXO2-2000 MachXO2-1200-R1 LCMX02-2000UHE4FG484I, LCMX02-2000UHE-5FG484I, LCMX02-2000UHE-6FG484I. AN8086, LCMX02 LCMX02 1200 LCMXO2-1200HC-4TG144C LCMXO2-4000HC LCMXO2-1200HC-4MG132C lcmxo2-1200 LCMXO2-7000HC LCMXO2-640HC-4TG100C TQFP-144 footprint LCMX02-2000
2013 - MACHXO2 7000 pinout

Abstract: MachXO2-4000
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 0A-13. MACHXO2 7000 pinout MachXO2-4000
2011 - Not Available

Abstract: No abstract text available
Text: -1200U1 XO2-2000 XO2-2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 , with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2- 256 , and MachXO2-640/U , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , devices with 256 to 6864 LUT4s and ï€ 19 to 335 I/Os  Ultra Low Power Devices • • • â , RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash


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PDF DS1035 DS1035 MachXO2-2000 MachXO2-1200-R1 LCMX02-2000UHE4FG484I, LCMX02-2000UHE-5FG484I, LCMX02-2000UHE-6FG484I. AN8086,
2013 - Not Available

Abstract: No abstract text available
Text:  Embedded and Distributed Memory • Up to 240 Kbits sysMEM™ Embedded Block RAM • Up to 54 Kbits Distributed RAM • Dedicated FIFO control logic  On-Chip User Flash Memory • Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï€ 400 MHz)  Flexible Logic Architecture • Six devices with 256 to 6864


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PDF DS1035 DS1035 MachXO2-4000HE
2001 - RAM 2112 256 word

Abstract: intel 2112 Static RAM HDSP-2XXX HDSP-21XX HDSP-2111 HDSP-2110 HDSP-2112
Text: Memory Section of Memory Flash RAM UDC Address Register UDC RAM Control Word Register Character RAM CLOCK , UDC RAM , a UDC Address Register, a Control Word Register, and refresh circuitry necessary to , ) User-Defined Character Address Register (UDC Address Register) Control Word Register This RAM stores either , Load ""F'' into the UDC RAM . When the attribute is enabled through bit 3 of the Control Word and a , Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display


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PDF HDSP-210x HDSP-211x HDSP-250x HDSP-21xx) HDSP-250x) HDSP-210x/-211x/-250x HDSP-210x/211x/250x I-060: HDSP-21XX, -25XX RAM 2112 256 word intel 2112 Static RAM HDSP-2XXX HDSP-21XX HDSP-2111 HDSP-2110 HDSP-2112
2012 - LCMX02 1200

Abstract: LCMX02 LCMX02 256 LCMX02 640 MACHXO2 1200 pinout file LCMXO2-1200HC-4MG132C MACHXO2-1200ZE MACHXO2 7000 pinout file LCMXO2-256HC-4SG32I LCMXO2-7000
Text: RAM (PFUs) Note: MachXO2- 256 , and MachXO2-640/U are similar to MachXO2-1200. MachXO2- 256 has a , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up


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PDF DS1035 DS1035 49-ball LCMX02 1200 LCMX02 LCMX02 256 LCMX02 640 MACHXO2 1200 pinout file LCMXO2-1200HC-4MG132C MACHXO2-1200ZE MACHXO2 7000 pinout file LCMXO2-256HC-4SG32I LCMXO2-7000
2012 - LCMXO2-4000HC

Abstract: LCMX02 LCMX02 1200 Lattice XO2 LCMXO2-4000 LCMX02-2000 HE 021 LCMXO2-2000HC-6FTG256C CABGA 17 x 17 thermal resistance lcmxo2 7000he pcb layout
Text: RAM (PFUs) Note: MachXO2- 256 , and MachXO2-640/U are similar to MachXO2-1200. MachXO2- 256 has a , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up


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PDF DS1035 DS1035 49-ball MachXO2-256, MachXO2-4000 332caBGA. LCMXO2-4000HC LCMX02 LCMX02 1200 Lattice XO2 LCMXO2-4000 LCMX02-2000 HE 021 LCMXO2-2000HC-6FTG256C CABGA 17 x 17 thermal resistance lcmxo2 7000he pcb layout
2010 - lcmxo2-1200

Abstract: LCMXO2-2000 LCMXO2-256 LCMXO2-4000 LCMXO2-640 LCMXO2-256HC-4TG100I LCMXO2-7000 MACHXO2 7000 pinout file MachXO2-1200 LCMXO2-2000HC-4BG256C
Text: 1280 2112 4320 6864 Distributed RAM (Kbits) 2 5 10 16 34 54 EBR SRAM , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , MHz to 400 MHz) Flexible Logic Architecture · Six devices with 256 to 6864 LUT4s and 18 to , Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up to 256 Kbits of User Flash Memory · 100,000 write cycles · Accessible


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PDF DS1035 DS1035 lcmxo2-1200 LCMXO2-2000 LCMXO2-256 LCMXO2-4000 LCMXO2-640 LCMXO2-256HC-4TG100I LCMXO2-7000 MACHXO2 7000 pinout file MachXO2-1200 LCMXO2-2000HC-4BG256C
RAM 2112 256 word

Abstract: 2650 cpu 8T31 8T26 256X4 KT9000 ba7t 239 2112 ADR11 256x4 static ram
Text: requirements should become evident from these examples. PARTS DESCRIPTIONS 2112 : The 2112 is a static 1024-bit Random Access Memory organized as 256 words by 4 Bits/ Word . It is fabricated with N-Channel, Silicon Gate , 7 [T 2112 Til vcc Til a4 TT] r/W TT] ce TT] I/O 4 TT| 1/0 3 Tol "0 2 Vss(GND) [T ~9~| I/O 1 PARTS LIST PART NO. QTY DESCRIPTION REFERENCE DATA SHEET 2650 1 CPU — 2112 4 256X4 RAM MOS , use of RAM for program debugging. The second figure represents a possible final system configuration


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PDF KT9000 1024-bit 256X4 82S115I 512X8 8T31I 8T26B 2650BM1000 N7411 RAM 2112 256 word 2650 cpu 8T31 8T26 ba7t 239 2112 ADR11 256x4 static ram
HDSP2122

Abstract: HDSP-2111 HDSP-2121 HDSP-2122 HDSP-2113 equivalent hdsp-2500 HDSP-250X HDSP-211X HDSP-2113 HDSP-2112
Text: Care UDC RAM 1 0 1 Row Address Control Word Register 1 1 0 Don't Care Character RAM 1 1 1 Character , character ASCII (Katakana) decoder, a 16 character UDC RAM , a UDC Address Register, a Control Word Register , the UDC RAM when the user is writing or reading a custom character. Control Word Register This , of the Control Word and a "1" is stored in the Flash RAM , the corresponding character will flash at , FLASH RAM ADDRESS control word address Dj Dc Dg D4 D3 O7 D6 Db D4 D3 D2 D, REMOVE FLASH AT SPECIFIED


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PDF HDSP-211X HDSP-212X HDSP-250X HDSP-211X/ -212X) HDSP-250X) HDSP-211X/-212X/-250X HDSP2122 HDSP-2111 HDSP-2121 HDSP-2122 HDSP-2113 equivalent hdsp-2500 HDSP-2113 HDSP-2112
9112C

Abstract: AM9112 91L12A AM91L12A P2112A maxim 2112
Text: 2112 256 x 4 Static RAM B. PACKAGE TYPE P - 16-Pin Plastic DIP (PD 016) C = 16-Pin Ceramic DIP , . SPEED OPTION A " 500 ns B - 400 ns C - 300 ns A. DEVICE NUMBER/DESCRIPTION Am9112 256 X 4 Static RAM , Am9112 2 5 6 x 4 Static RAM ZL16UIV DISTINCTIVE CHARACTERISTICS Low operating power , es guaranteed for sim pler timing Direct plug-in replacem ent for 2112 type devices GENERAL , as fa st as 200 ns and as low as 100 mW typical. Each mem ory is implemented as 256 w ords by 4 bits


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PDF Am9112 ZL16UIV 9112/A 91L12 1024-bit, MIL-STD-883, 9112C AM9112 91L12A AM91L12A P2112A maxim 2112
Not Available

Abstract: No abstract text available
Text: kHz 50 kHz – 100 kHz MCLK/LRCK Ratio 256 , 384, 512, 768, 1024. 128, 192, 256 , 384, 512. In , / 256 ) 00010 MCLK/4 12 kHz (MCLK/1024) 00111 12 kHz (MCLK/1024) 00111 MCLK/4 16 , /6 48 kHz (MCLK/ 256 ) 00010 8 kHz (MCLK/1536) 01010 MCLK/4 48 kHz (MCLK/ 256 ) 00010 48 kHz (MCLK/ 256 ) 00010 MCLK/4 96 kHz (MCLK/128) 00000 96 kHz (MCLK/128 , 8.0182 kHz (MCLK/1408) 01001 44.1 kHz (MCLK/ 256 ) 00010 MCLK/4 11.025 kHz (MCLK/1024


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PDF 24-bit, -85dB -81dB 500mWatt 40mWatt 50BSC
2009 - bluetooth block diagram

Abstract: PA5750
Text: 50 kHz 50 kHz ­ 100 kHz MCLK/LRCK Ratio 256 , 384, 512, 768, 1024. 128, 192, 256 , 384, 512. In , . DAC Sample Rates (DLRCK) 8 kHz (MCLK/1536) 48 kHz (MCLK/ 256 ) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 8 kHz (MCLK/1536) 48 kHz (MCLK/ 256 ) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/ 256 ) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/ 256 ) 88.2 kHz (MCLK/128) 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 12 kHz (MCLK/1536) 16 kHz (MCLK


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PDF PA5750 24-bit, -85dB -81dB 500mWatt 40mWatt 16mWatt 256Fs, 384Fs, bluetooth block diagram PA5750
st-171

Abstract: HDSP-2122 st171 st171 cmos HDSP2121 HDSP-2113 HDSP2113 HDSP2122 H100-1440
Text: Address 1 0 0 UDC Address Register Don't Care 1 0 1 UDC RAM Row Address 1 1 0 Control Word Register Don't , RAM , a UDC Address Register, a Control Word Register and the refresh circuitry necessary to , bit 3 of the Control Word and a "1" is stored in the Flash RAM , the corresponding character will flash , frequency by 28,672. If the flash enable bit of the Control Word is a "0", the content of the Flash RAM is , seconds. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash


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PDF H100-1720 ND0220 HDSP-2113/-2123 H100-1440 HDSP-2112/-2122 H100-1670 r-1250 R6310 st-171 HDSP-2122 st171 st171 cmos HDSP2121 HDSP-2113 HDSP2113 HDSP2122
1999 - RAM 2112 256 word

Abstract: mst 720 ram 2112
Text: RAM . Row Decoder IA[t - 1] to Word Line Buffer Memory Cell Matrix Column Decoder , compiler. This section explains how to calculate actual available RAM size. (1) Adjustment of Word /Bit , voltage = 1.8V Parameter Unit Equation (ns) (ns) 0.000334 x W + 1.536 ( 256³Word >16) CYCLE TIME 0.000575 x W + 1.961 (1024³ Word >512) 0.000525 x W + 1.609 (512³ Word > 256 ) tCY (ns) 1.69 (1024³ Word >512) (ns) 1.32 (512³ Word > 256 ) (ns) 1.20 tCWH CLOCK PULSE WIDTH (H


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PDF CS81/CE81" GATI1062, CS81/CE81 GATI1062 RAM 2112 256 word mst 720 ram 2112
Not Available

Abstract: No abstract text available
Text: =+25 C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK= 256 . PARAMETER MIN TYP MAX UNIT Dynamic , =0V, Ambient temperature=+25 C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK= 256 . PARAMETER MIN TYP MAX , Speed Mode Sampling Frequency MCLK/LRCK Ratio Single Speed 8kHz – 50kHz 256 , 384, 512, 768, 1024 Double Speed 50kHz – 100kHz 128, 192, 256 , 384, 512 In master mode, LRCK and , / 256 ) 48 kHz (MCLK/ 256 ) 96 kHz (MCLK/128) 11.2896 MHz 22.5792MHz 8.0182 kHz (MCLK/1408) 8.0182


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PDF 24-Bit, PA5331
Supplyframe Tracking Pixel