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2002 - OC 74 germanium transistor

Abstract: No abstract text available
Text: Parameter Output HIGH voltage Q0-Q15 , QP, CLK16O Output LOW voltage Low Speed Outputs Output , Diagram tCLK16O TDIB TDIA CLK16O Q0-Q15 Q0-Q15 Q0-Q15 Figure 1: Timing Diagram , 65, 64 LOL 2 LOS 3 NUP, NDN 5, 6 NCLK16O CLK16O 11, 12 Data Output Q0-Q15 and , directly to GND. Type CLK160 Supply Supply for data output ( Q0-Q15 ) termination resistors. For , for data outputs ( Q0-Q15 ). For LVDS: Connect each to ground through ferrite bead. For CML: Connect


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PDF VSC1234 100-pin VMDS-10094 1-800-VITESSE OC 74 germanium transistor
em 6695

Abstract: 16 BIT SHIFT REGISTER cd14510s 1021j 74F673A N74F673D N74F673N Q0-Q15
Text: overrides all other inputs and forces the Q0-Q15 outputs Low. The storage register is in the Hold mode , -0.5 to + Vcc V 'out Current applied to output in Low output state Sl/O 48 mA Q0-Q15 40 mA Ta , clamp current -18 mA lOH High-level output current Sl/O -3.0 mA Q0-Q15 -1.0 mA IO- Low-level input current Sl/O 24 mA Q0-Q15 20 mA TA Operating free-air temperature 0 70 °C June 1987 , Min Typ2 Max VOH High-level output voltage Q0-Q15 Vcc = MIN VIL = MAX Vih = MIN Ioh -1mA Â


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PDF 74F673A 16-Bit 300mil-wide 24-Pin F673A em 6695 16 BIT SHIFT REGISTER cd14510s 1021j 74F673A N74F673D N74F673N Q0-Q15
1998 - M27W322

Abstract: Q0-Q15
Text: 1 FDIP42W (F) Logic Diagram VCC 21 16 A0-A20 E Q0-Q15 M27W322 GVPP , Names A0-A20 Address Inputs Q0-Q15 Data Outputs E Chip Enable GVPP Output Enable


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PDF M27W322 100ns 120ns 100sec. 0020h 0034h M27W322 AI02070 A0-A20 Q0-Q15 Q0-Q15
1998 - M27C516

Abstract: PLCC44 Q0-Q15
Text: VPP 15 16 A0-A14 Signal Names P A0-A14 Address Inputs Q0-Q15 Chip Enable , M27C516 Data Outputs E Q0-Q15 Ground E G B27C516/809 Complete data available on


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PDF M27C516 0020h 000Fh M27C516 PLCC44 TSOP40 PLCC44 A0-A14s Q0-Q15
1998 - M27W102

Abstract: PLCC44 Q0-Q15
Text: VPP 16 16 A0-A15 P Q0-Q15 M27W102 E G VSS AI01922 B27W102/804 Complete , Inputs Q0-Q15 Data Outputs E Chip Enable G Output Enable P Program VPP


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PDF M27W102 0020h 008Ch FDIP40W PLCC44 TSOP40 M27W102 organi102 PLCC44 Q0-Q15
1998 - M27C322

Abstract: Q0-Q15
Text: programming procedure. 42 1 FDIP42W (F) Logic Diagram VCC 21 16 A0-A20 E Q0-Q15 , AI02157 Signal Names A0-A20 Address Inputs Q0-Q15 Data Outputs E Chip Enable GVPP


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PDF M27C322 100sec. 0020h 0034h M27C322 FDIP42W AI02157 A0-A20 Q0-Q15 Q0-Q15
1999 - M27C322

Abstract: PDIP42 Q0-Q15 32-Mbit
Text: A0-A20 E Q0-Q15 M27C322 GVPP VSS AI02156 B27C322/9901 Complete data available on , A13 A14 A15 A16 A20 VSS Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Address Inputs Q0-Q15


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PDF M27C322 PDIP42 FDIP42W 0020h 0034h M27C322 Q0-Q15 AI02157 PDIP42 Q0-Q15 32-Mbit
MTC5585D

Abstract: MTC5585 1 to 16 demultiplexer MTC5615 MTC558 MTC56 MTC4110 multilink cdr MTC1210
Text: Range High Speed Data Inputs (DIN, NDIN) Output Voltage Swing Low Speed Data Outputs ( Q0-Q15 , CLK16O TDIA TDIB Q0-Q15 Q0-Q15 Q0-Q15 Figure 3: Timing Diagram Page 4 MIXED SIGNAL


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PDF 16-Bit MTC1210 OC-192 STM-64 MTC1210 OC-192, STM-64, 10-04-00L MTC5585D MTC5585 1 to 16 demultiplexer MTC5615 MTC558 MTC56 MTC4110 multilink cdr
1998 - presto

Abstract: M27C202 PLCC44 Q0-Q15
Text: A0-A16 Signal Names P A0-A16 Address Inputs Q0-Q15 Chip Enable G Output Enable , E Q0-Q15 Ground E G VSS AI01815 B27C202/803 Complete data available on


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PDF M27C202 128Kb 0020h 001Ch PLCC44 TSOP40 M27C202 presto PLCC44 Q0-Q15
Q0-Q15

Abstract: M27C322 FDIP42W
Text: programming procedure. 42 1 FDIP42W (F) Logic Diagram VCC 21 16 A0-A20 E Q0-Q15 , AI02157 Signal Names A0-A20 Address Inputs Q0-Q15 Data Outputs E Chip Enable GVPP


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PDF M27C322 0020h 0034h M27C322 FDIP42W AI02157 A0-A20 Q0-Q15 100ns 120ns Q0-Q15 FDIP42W
1998 - M27W102

Abstract: PLCC44 Q0-Q15
Text: VPP 16 16 A0-A15 P Q0-Q15 M27W102 E G VSS AI01922 B27W102/803 Complete , Inputs Q0-Q15 Data Outputs E Chip Enable G Output Enable P Program VPP


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PDF M27W102 0020h 008Ch FDIP40W PLCC44 TSOP40 M27W102 PLCC44 Q0-Q15
1998 - presto

Abstract: TSOP40 M27C1024 PDIP40 PLCC44 Q0-Q15
Text: ) PLCC44 (C) TSOP40 (N) 10 x 14mm Logic Diagram VCC VPP 16 16 A0-A15 P Q0-Q15 , Q9 Q8 VSS NC Q7 Q6 Q5 Q4 Address Inputs Q0-Q15 Q13 Q14 Q15 E VPP NC VCC P NC


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PDF M27C1024 0020h 008Ch M27C1024 FDIP40W PDIP40 PLCC44 TSOP40 100ns presto TSOP40 PDIP40 PLCC44 Q0-Q15
1998 - pdip40

Abstract: PLCC32 PLCC44 Q0-Q15 M27V102 M27W102
Text: Q0-Q15 M27V102 E G VSS AI01912 B27V102/805 Complete data available on DATA-on-DISC CD-ROM , Q0-Q15 Data Outputs E Chip Enable G Output Enable P Program VPP Program Supply


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PDF M27V102 0020h 008Ch M27W102 M27V102 FDIP40W PDIP40 PLCC44 pdip40 PLCC32 PLCC44 Q0-Q15
1999 - M27V256

Abstract: M27V402 PDIP40 PLCC44 Q0-Q15
Text: ) TSOP40 (N) 10 x 20 mm Figure 1. Logic Diagram VCC VPP 18 16 A0-A17 E Q0-Q15 , Figure 2A. DIP Pin Connections Address Inputs Q0-Q15 Data Outputs E Chip Enable G


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PDF M27V402 256Kb 120ns FDIP40W PDIP40 M27V402 Q0-Q15 M27V256 PDIP40 PLCC44 Q0-Q15
Not Available

Abstract: No abstract text available
Text: ) PLCC44 (K) TSOP40 (N) 10 x 20 mm Logic Diagram VCC VPP 18 16 A0-A17 E Q0-Q15 , Q0-Q15 Data Outputs E Chip Enable G Output Enable VPP Program Supply VCC


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PDF M27V402 256Kb 120ns M27V402 Q0-Q15 FDIP40W
MX* 64M-Bit eprom

Abstract: A0-A21 Q0-Q15
Text: Description Symbol A0-A22 Type input Q0-Q15 input/output ADV input CE input CLK , Gating/Sensing Q0-Q15 Device ID Block Lokc RCR Data Input Buffer ID Reg. Data Register , Generators Q0-Q15 Output Buffer I/O Logic A0-A21 ADV Address Input Buffer Address


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PDF MX28F640W30T/B 64M-BIT 32Kword 128-bit 64-bit DEC/09/2002 MX* 64M-Bit eprom A0-A21 Q0-Q15
1999 - M27V402

Abstract: PDIP40 PLCC44 Q0-Q15
Text: programming procedure. Table 1. Signal Names A0-A17 Address Inputs Q0-Q15 Program Supply VCC VPP 18 16 A0-A17 E Q0-Q15 M27V402 Supply Voltage VSS VCC Output Enable , . Table 3. Operating Modes E G A9 VPP Q0-Q15 Read VIL V IL X V CC or VSS , Q0-Q15 tGHQZ Hi-Z DATA OUT AI00731 6/15 M27V402 Table 9. Programming Mode DC , . Programming and Verify Modes AC Waveforms VALID A0-A17 tAVEL Q0-Q15 DATA OUT DATA IN tQVEL


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PDF M27V402 256Kb 120ns FDIP40W PDIP40 M27V402 PDIP40 PLCC44 Q0-Q15
M27C1024

Abstract: Q0-Q15
Text: VCC Vpp AO-A15 Address Inputs Q0-Q15 Data Outputs E Chip Enable G Output Enable P Program Vpp Program Supply Vcc Supply Voltage Vss Ground A0-A15 P Ë G 16 M27C1024 16 Q0-Q15 Vss ai00702b , than 20ns. Table 3. Operating Modes Mode Ë G P A9 Vpp Q0-Q15 Read V,L Vil Vih X Vcc or Vss Data , with or afterVpp 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A15 Q0-Q15 , A0-A15 Q0-Q15 Vpp Vcc VALID tAVPL DATA IN tQVPL ■-tVPHPL- tVCHPL- tELPL tPLPH S_i 4-» â


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PDF M27C1024 FDIP40W M27C1024 7T2T237 Q0-Q15
1998 - M27C516

Abstract: PLCC44 Q0-Q15
Text: Inputs Q0-Q15 Chip Enable G Output Enable P Program Enable VCC Supply Voltage VPP Program Supply VSS M27C516 Data Outputs E Q0-Q15 Ground E G B27C516


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PDF M27C516 0020h 000Fh PLCC44 TSOP40 M27C516 PLCC44 100ns Q0-Q15
TEST74

Abstract: mtc5525
Text: 666.5 Mb/s Data Outputs ( Q0-Q15 , NQ0-NQ15) Max. 10.66422857 Input Voltage Swing 10.664Gb/s , TDIB Q0-Q15 Q0-Q15 Q0-Q15 Figure 3: Timing Diagram Page 4 MIXED SIGNAL INTEGRATED


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PDF MTC1224B 16-Bit OC-192 STM-64 20mVpp MTC1224B OC-192, STM-64, 09-13-00L TEST74 mtc5525
mxic

Abstract: MX* 64M-Bit eprom 8088 microprocessor pin description A0-A21 Q0-Q15 64-mega
Text: Description Symbol A0-A22 Type input Q0-Q15 input/output ADV input CE input CLK , Gating/Sensing Q0-Q15 Device ID Block Lokc RCR Data Input Buffer ID Reg. Data Register , Generators Q0-Q15 Output Buffer I/O Logic A0-A21 ADV Address Input Buffer Address


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PDF MX28F640W18T/B 64M-BIT 32Kword 128-bit 64-bit DEC/09/ mxic MX* 64M-Bit eprom 8088 microprocessor pin description A0-A21 Q0-Q15 64-mega
16-Bit Parallel-out Serial-in Shift Register

Abstract: Q0-Q15 F673A
Text: U.L. definitions Pin Names Description 54F/74F(U.L.) HIGH/LOW CS SHCP STMR STCP R/W Sl/O Q0-Q15 Chip , asynchronous master reset (STMR) input that overrides all other inputs and forces the Q0-Q15 outputs LOW. The , - R/W- STCP STMR —> —oO> :=0 :=0 Do CP -O CP PE P0-P15 SHIFT REGISTER Q0-Q15 Ql5 â


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PDF 54F/74F673A 16-Bit F673A 16-Bit Parallel-out Serial-in Shift Register Q0-Q15
16-Blt

Abstract: Q0-Q15
Text: Data Output 25/12.5 Q0-Q15 Parallel Data Outputs 25/12.5 4-525 This Material Copyrighted By Its , Do CP Q15 Q0-Q15 -►so i> Please note that this diagram is provided only tor the


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PDF 54F/74F675 16-Bit 16-Blt Q0-Q15
1998 - JLCC44W

Abstract: M27C4002 PDIP40 PLCC44 Q0-Q15 tsop40
Text: VPP 18 16 A0-A17 E Q0-Q15 M27C4002 G VSS AI00727B B27C4002/809 Complete , . 2/3 Address Inputs Q0-Q15 Q13 Q14 Q15 E VPP NC VCC A17 A16 A15 A14 A0-A17


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PDF M27C4002 256Kb 10MHz 0020h 0044h FDIP40W PDIP40 JLCC44W M27C4002 JLCC44W PDIP40 PLCC44 Q0-Q15 tsop40
1998 - JLCC44W

Abstract: 256kb 16 bit eprom M27C4002 PLCC44 Q0-Q15 0044H
Text: ) PLCC44 (C) TSOP40 (N) 10 x 20 mm Logic Diagram VCC VPP 18 16 A0-A17 E Q0-Q15 , Q0-Q15 Q13 Q14 Q15 E VPP NC VCC A17 A16 A15 A14 A0-A17 Chip Enable G Output


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PDF M27C4002 256Kb 24sec. 0020h 0044h M27C4002 FDIP40W JLCC44W JLCC44W 256kb 16 bit eprom PLCC44 Q0-Q15 0044H
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