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2101549-1 TE Connectivity Ltd PLUG,40 POS,CIRCULAR HD,PCB,POL1
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(3)4POL. 180� RM 2,54 Chip One Exchange - -
(9)10POL. 180� Chip One Exchange - -
16POL. 180� Chip One Exchange - -
16POL. 180� BOX HEADER Chip One Exchange - -
16POL. 180� MIT VERRIEGELUNG Chip One Exchange - -
40POL 180� Chip One Exchange - -
40POL. 180� MIT VERRIEGELUNG Chip One Exchange - -
5POL. 180� RM2,54 Chip One Exchange - -
6POL. 180� 2,5MM Chip One Exchange - -
6POL. 180� RM2,54 Chip One Exchange - -
APOL12/16E 0.4 C1 Altech Corporation Allied Electronics & Automation 0 $39.66 $39.66
APOL12/16E 14 C1 Altech Corporation Allied Electronics & Automation 0 $42.90 $42.90
APOL12/16E 14 C3 Altech Corporation Allied Electronics & Automation 0 $42.90 $42.90
APOL12/16E 18 C3 Altech Corporation Allied Electronics & Automation 0 $49.77 $49.77
APOL12/16E 2.7 C1 Altech Corporation Allied Electronics & Automation 0 $39.66 $39.66
APOL12/16E 2.7 C3 Altech Corporation Allied Electronics & Automation 0 $39.66 $39.66
APOL12/16E 23 C3 Altech Corporation Allied Electronics & Automation 0 $51.40 $51.40
APOL12/16E 6 C1 Altech Corporation Allied Electronics & Automation 0 $39.66 $39.66
APOL12/16E 6 C3 Altech Corporation Allied Electronics & Automation 0 $39.66 $39.66
APOL12/16E 9 C1 Altech Corporation Allied Electronics & Automation 0 $41.30 $41.30
APOL12/16E 9 C3 Altech Corporation Allied Electronics & Automation 0 $41.30 $41.30
POL 102 / BL Schutzinger GmbH Allied Electronics & Automation 0 $24.59 $17.02
POL 102 / RT Schutzinger GmbH Allied Electronics & Automation 0 $24.10 $16.69
POL 102 / SW Schutzinger GmbH Allied Electronics & Automation 0 $24.59 $17.02
POL-15033 Premier Magnetics Bristol Electronics - -
POL100-15 MG Chemicals Allied Electronics & Automation 1 $15.95 $15.95
POL100-15 MG Chemicals Newark element14 20 $15.95 $15.95
POL100-15 MG Chemicals Chip1Stop 19 $22.20 $16.00
POL1000 Modelcraft Tools element14 Asia-Pacific 0 $5.38 $4.83
POL1000 Modelcraft Tools Farnell element14 24 £3.67 £3.30
POL1000 Modelcraft Tools Newark element14 12 $5.56 $3.64
POL1009 Modelcraft Tools element14 Asia-Pacific 0 $5.38 $4.83
POL1017/4 Modelcraft Tools element14 Asia-Pacific 6 $4.94 $4.31
POL1017/4 Modelcraft Tools Newark element14 1 $4.48 $2.93
POL1017/4 Modelcraft Tools Farnell element14 0 £5.48 £4.93
POL102/BL Schutzinger GmbH Schukat electronic 0 €14.80 €11.05
POL102/BL Schutzinger GmbH TME Electronic Components 9 $16.83 $15.31
POL102/GE Schutzinger GmbH Schukat electronic 0 €14.80 €11.05
POL102/GE Schutzinger GmbH TME Electronic Components 8 $16.83 $15.31
POL102/GN Schutzinger GmbH Schukat electronic 0 €14.80 €11.05
POL102/GN Schutzinger GmbH TME Electronic Components 1 $16.83 $15.31
POL102/RT Schutzinger GmbH Schukat electronic 0 €14.80 €11.05
POL102/RT Schutzinger GmbH TME Electronic Components 27 $16.83 $15.31
POL102/SW Schutzinger GmbH Schukat electronic 54 €14.80 €11.05
POL102/SW Schutzinger GmbH TME Electronic Components 33 $16.83 $15.31
POL1201 Modelcraft Tools element14 Asia-Pacific 0 $7.32 $6.59
POL1201 Modelcraft Tools Newark element14 13 $7.58 $4.96
POL1201 Modelcraft Tools Farnell element14 25 £5.00 £4.50
POL1202 Modelcraft Tools element14 Asia-Pacific 0 $7.32 $6.59
POL1994/SW Schutzinger GmbH TME Electronic Components 33 $3.83 $3.25
SUPERPOL 10 MISCELLANEOUS Bisco Industries - -

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Pol1 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
GL137

Abstract:
Text: is 255. The POL1-POLO-POL1 sequence is recognized when one or more POL1 interrupts are generated , . The period time of a POL1-POLO-POL1 sequence is available in the Ringer period register. It is preset , . Detection of a polarity change on the inputs POLO or POL1 , the reception of an FSK data byte, the detection , POL1 POLO LOWBAT CASIN FSKINFSKIN+ V DD I I 0 [T is ] FSK1N+ 5 6 I/O serial data , [F [IT T il LOWBAT T il POLO To] POL1 T] MBH930 I I I LX O U T [ T [IT AGND 13 14


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PDF PCD3316 GL137 2068 dd 3.58mg
ba607

Abstract:
Text: logic 0 to logic 1, a POL1 interrupt is generated. The period time of a POL1-POLO-POL1 sequence is , POL1-POLO-POL1 sequence is recognized when one or more POL1 interrupts are generated followed by one or more POLO , inputs POLO or POL1 , the reception of an FSK data byte, the detection of a CAS tone or a timebase , POL1 POLO LOWBAT CASIN FSKINFSKIN+ V dd T^vnn Ts| F S K IN + Û ] F S K IN C A S IN I/O serial , . The result of the two comparators can be read in bits 7 and 6 (POLO and POL1 ) of the Status register


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PDF I------100 PCD3316 GK729 MBH996 ba607 OM5843
2006 - twin lnb

Abstract:
Text: VVHIGH VVHIGH VVLOW 100 Vert 1/2 Outputs I VERT1 =I VERT2 =10mA, Voltage High V POL1 = V POL2 = 14V I VERT1 =I VERT2 =15mA, Voltage High V POL1 = V POL2 = 14V Voltage High I VERT1 =I VERT2 =10µA, V POL1 = V POL2 = 14V Voltage Low I VERT1 =I VERT2=-10mA, V POL1 = V POL2 = 15.0V VVHIGH , Low I HOR1 =I HOR2=10mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=15mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=10µA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=-10mA, V POL1 = V POL2 = 14V 76 µs


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PDF ZLNB100 ZLNB101 twin lnb HEMTFET lnb twins lnb ZNBG6000 ZLNB100X ZLNB100N8 ZLNB100 twin lnb diagram SO8 Wide Package LNB SUPPLY AND CONTROL VOLTAGE
2006 - twin lnb

Abstract:
Text: VVHIGH VVHIGH VVLOW 100 Vert 1/2 Outputs I VERT1 =I VERT2 =10mA, Voltage High V POL1 = V POL2 = 14V I VERT1 =I VERT2 =15mA, Voltage High V POL1 = V POL2 = 14V Voltage High I VERT1 =I VERT2 =10µA, V POL1 = V POL2 = 14V Voltage Low I VERT1 =I VERT2=-10mA, V POL1 = V POL2 = 15.0V VVHIGH , Low I HOR1 =I HOR2=10mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=15mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=10µA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=-10mA, V POL1 = V POL2 = 14V 76 78 µs


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PDF ZLNB101 ZLNB101 twin lnb HEMTFET lnb ZNBG6000 twin lnb diagram SO8 Wide Package mixer lnb ZLNB101N8 ZLNB101X8 ZNBG4000
3579545 crystal oscillator kss 7b

Abstract:
Text: logic 0 to logic 1, a POL1 interrupt is generated. The period time of a POL1-POLO-POL1 sequence is , register = 255. The period is given in multiples of V2048 s. The maximum value is 255. The POL1-POLO-POL1 , polarity change on the inputs POLO or POL1 , the reception of an FSK data byte, the detection of a CAS tone , LXOUT 7 o 32.768 kHz crystal oscillator output DGND 8 - digital ground AGND 9 - analog ground POL1 10 , ~ TTl fskin- scl |~4~ sdapt 3CD3316 TT| casin ~\z\ lowbat lxin [IT TT| polo lxout |~7~ To] POL1


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PDF
Xb2 276

Abstract:
Text: 414 413 412 411 410 409 408 407 406 ZA0 SPOI GNDL POL1 POL2 CK VCC V1 V2 V3 V4 , Shift clock input pin 420, 421 POL2, POL1 I Input data polarity exchange input pins 422 , 387 SPIO 407 SHIFT REGISTER 423 SPOI CK 419 POL1 421 1 2 XA0 436 401 XA5 441 406 , ¿Applicable pins¡ POL1 , POL2 GNDL Fig. 2 Input Circuit (2) 4 LH168A VCC VCC I To , output voltage values, refer to "Functional Operations" and "Output Voltage Value". POL1 POL2 TESTB


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PDF LH168A 384-output LH168A 444-PIN Xb2 276 LCD 6x2 444PIN FLS 441 V1-V10 XO128 yb4 42
1998 - 9398 393 40011 or I2C Peripherals Data Handbook IC12

Abstract:
Text: The POL1-POL0-POL1 sequence is recognized when one or more POL1 interrupts are generated followed by , be polled. 1998 May 14 INTERRUPT 1 The period time of a POL1-POL0-POL1 sequence is , oscillator can be enabled separately. Detection of a polarity change on the inputs POL0 or POL1 , the , 3 CONTROL 4 I2C-BUS INTERFACE POR LOWBAT POL0 POL1 12 5 SCL SDA 11 , 32.768 kHz crystal oscillator input LXOUT 7 O 8 - 9 - analog ground POL1 10


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PDF PCD3316 MHz31 SCA60 415102/1200/03/pp28 9398 393 40011 or I2C Peripherals Data Handbook IC12 FSK receiver philips PCD3316 PCD3316T
2001 - X1890

Abstract:
Text: V1 V0 GND1 TESTCLK CL2 CL1 M 41 42 43 44 45 46 47 48 49 50 POL1 POL2 D25 D24 , , D05 to D00 circuit Latch address selector 6 planes 480 latch circuits (1) POL1 POL2 VLCD , POL1 and POL2 signals to perform polarity inversion (at high levels) or non-inversion (at low levels , input. At least two CL2 clocks must be input during the high-level period of CL1. POL1 2 , . When POL1 /POL2 is high, display data is inverted in the driver. When POL1 /POL2 is low, display data


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PDF HD66339 64-level ADE-207-332 HD66339 HD66339s X1890 Y474 X3770 X5670 a 1v9 y472 x2420 X417 X2590
1998 - LPH7319

Abstract:
Text: POL1-POL0-POL1. which sets the ringer period register with the period time of the ringer signal by means of a , Detection by POL0 and POL1 4.4 Power Down state . . . . . . . . . . . . . . . . . . . 4.5 Low Battery , . . . POL0 and POL1 handling with a sinewave as input signal. . . . . . Signal path of ringer , . . . . . . . . POL0/ POL1 detection procedure . . . . . . . . . . . . . . . . . . . Polarity , via the I2C-bus serial interface. Detection of a polarity change on the inputs POL0 or POL1 , the


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PDF PCD3316 AN98071 PCD3316 LPH7319 lph7319-3 circuit diagram for micro controller based caller LPH7319-3 Display module dmo 465 BT 139 F applications note ,LPH7319 AN98071 caller id converter dtmf to fsk transistor BT 139 F applications note
dot led display large size with circuit diagram

Abstract:
Text: D07 9 D50 29 FSL 49 M 69 D06 10 D47 30 STPLS 50 POL1 70 D05 11 D46 31 ODD/EVN 51 POL2 71 D04 12 , to D20, D17 to D10, D07 to DOO POL1 POL2 Data inversion circuit V|_CD Vcc GND VO, V1, V2, V3 , controls internal timing signals. 2. Data inversion circuit Uses the POL1 and POL2 signals to perform , are for the 402-output LSIs.) POL1 , POL2 1 Input Data-polarity inversion signal to reduce power consumption of data bus lines in the interface. When POL1 or POL2 is high, display data is inverted in the


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PDF HD66350T 256-level ADE-207-297 HD66350T 384-output 402-output dot led display large size with circuit diagram EI02 hitachi lcd gate source drive J D371 R6 SXGA HITACHI
1998 - y399

Abstract:
Text: 56 57 58 59 60 V2 V1 V0 GND TEST2 TEST CL2 CL1 M POL1 POL2 D27 D26 D25 D24 D23 , Latch address selector Data inversion circuit 384/402 latch circuits (1) POL1 POL2 V0, V1 , , EIO1) and controls internal timing signals. 2. Data inversion circuit Uses the POL1 and POL2 signals , -output LSIs.) POL1 , POL2 1 Input Data-polarity inversion signal to reduce power consumption of data bus lines in the interface. When POL1 or POL2 is high, display data is inverted in the driver


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PDF HD66350T 256-level ADE-207-297 HD66350T 384-output 402-output y399 d388 Hitachi DSA00164 XGA HITACHI gate drive
1999 - V23 FSK Japan

Abstract:
Text: /2048 s. The maximum value is 255. The POL1-POL0-POL1 sequence is recognized when one or more POL1 , interrupt is generated. The period time of a POL1-POL0-POL1 sequence is available in the Ringer period , enabled separately. Detection of a polarity change on the inputs POL0 or POL1 , the reception of an FSK , DETECT TIMING st HXOUT ric POL0 10 3 4 I2C-BUS INTERFACE POR d POL1 , 11 POL0 LXOUT 7 10 POL1 DGND 8 9 AGND MBH980 Fig 2. Pin configuration. © Philips


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PDF PCD3316 PCD3316 V23 FSK Japan top mark smd Philips 9398 393 40011 or I2C Peripherals Data Handbook IC12 AN98071 PCD3316T
1999 - marking code C1E SMD ic

Abstract:
Text: , a POL1 interrupt is generated. The period time of a POL1-POL0-POL1 sequence is available in the , multiples of 1/2048 s. The maximum value is 255. The POL1-POL0-POL1 sequence is recognized when one or more , polarity change on the inputs POL0 or POL1 , the reception of an FSK data byte, the detection of a CAS tone , HXOUT LOWBAT POL0 POL1 12 11 10 16 PREPROCESSOR 3.58 MHz OSCILLATOR TIMING LEVEL DETECT , CASIN 12 LOWBAT 11 POL0 10 POL1 9 AGND MBH980 © Philips Electronics N.V. 1999. All rights reserved


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PDF PCD3316 PCD3316 PCD3316T/2D-T OT109 marking code C1E SMD ic smd code marking C1E 9398 393 40011 or I2C Peripherals Data Handbook IC12 smd c1e FSK receiver philips 7136 mark IC12 Peripherals data handbook
1998 - yn 1018

Abstract:
Text: POL2 41 42 43 44 45 46 47 48 49 50 POL1 D25 D24 D23 D22 D21 D20 D15 D14 D13 , circuit Latch address selector 6 planes 384 latch circuits (1) POL1 POL2 VLCD VCC GND V5 , POL1 and POL2 signals to perform polarity inversion (at high levels) or non-inversion (at low levels , input. At least two CL2 clocks must be input during the high-level period of CL1. POL1 2 , . When POL1 /POL2 is high, display data is inverted in the driver. When POL1 /POL2 is low, display data


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PDF HD66325A 64-level ADE-207-296 HD66325A HD66325As yn 1018 Hitachi DSA00164
d3827

Abstract:
Text: inversion unit Uses the POL1-POL2 signals to invert or not the 6 x 8-bit input data. 64 bits , · Display data inversion function ( POL1 , POL2) Page 2 of 19 EUREKA EK7411 1. INTERNAL , R/L CLK D0 0-D0 7, D10 -D17 D2 0-D2 7, D30 -D37 D4 0-D4 7, D50 -D57 POL1 POL2 Control , Copper Foil Surface · ·· GMA0 VSS1 NC NC CLK STB LPOL POL2 POL1 D2 7 ··· D2 0 D1 , POL1 , POL2 Input Right shift start pulse R/L = H : Becomes the start pulse input pin R/L = L


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PDF EK7411 384-Channel EK7411 256-bit d3827 D3831 D400 transistor transistor D400 circuit diagram application d382 p D3826 D383 D379 D385 transistor D400 pin diagram
1999 - rneg2

Abstract:
Text: 5 100pF 1 R7 4.7K C3 100nF POL1 POL2 IC SCEXT IC GND GND RxdatRxdat+ GND , 100nF PORB ENTX SLICE 1 PCBSW setb resel pol1 5 RPOS1 TCLK1 R4 100 K 4 , 5 6 7 8 9 100uF 25V 0 = ENABLE RECEPTION LASER: (dr4) (dr3)( pol1 ) (setb) (pol2


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PDF 100nF PCB405 ACS4050CS: ACS405 100uF rneg2 100n CB POL15 C1156 bookham laser ACS405A ACS4050 R1242 TMD2
smd diode code 33-16

Abstract:
Text: changes from logic 0 to logic 1, a POL1 interrupt is generated. The period tim e of a POL1-POLO-POL1 , . The POL1-POLO-POL1 sequence is recognized w hen one or more POL1 interrupts are generated follow ed by , DGND AGND POL1 POLO LOWBAT CAS IN FS K IN FSKIN+ V dd Pin d e s c rip tio n Pin 1 2 3 4 5 6 7 8 9 10 11 , by clearing bit 7 of M ode register 2. The tw o low pow er com parators (inputs POLO and POL1 ) and , the reference voltage V ref. If POLO < V ref or POL1 > V ref, POLO and POL1 (Status register, bit 7


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1999 - 100n CB

Abstract:
Text: VB 1 VA 8 VDD ENTX: GND SW1 4.7uH L1 L2 (resel) (pol2) ( pol1 ) (dr4) (dr3) (dr2) (dr1) (+) ZD1 (+) C CB 100uF 25V C1 100nF 100nF C2 100nF (GND) 1 = LASER DRIVE. 0 = LED DRIVE LASRX: 1 = RECEIVE on LAN and LAP TERMINALS PINRX: 1 = , 2 3 4 5 6 7 8 9 R4 100 K resel pol1 pol2 GND 21 TmD1 22 TmD2 54 SLICE , RNEG3 100pF 1 GND POL1 POL2 IC SCEXT IC GND GND RxdatRxdat+ GND_5 IREF VA+ XIN


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PDF 100uF 100nF ACS405 74HC241 100n CB rneg2 26way 74HC241 ACS4050 ACS9010 rneg4 TMD2
2015 - L8312

Abstract:
Text: 11 12 13 14 15 16 PIN NAME S2A S2B S2C S2D VCC CENB2 FIN2 POL2 POL1 FIN1 CENB1 , 1k CENB1 10n 10n FIN2 1k POL2 FIN1 1k 1k POL1 0.1u(Note 3) 0.1u(Note , provides maximum input voltage protection for the POL1 , 2 pins. The low pass filter of tone detection


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PDF L8312 L8312 QW-R123-016
2013 - Not Available

Abstract:
Text: PIN NAME S2A S2B S2C S2D VCC CENB2 FIN2 POL2 POL1 FIN1 CENB1 GND S1D S1C S1B S1A , 10n FIN2 1k POL2 FIN1 1k 1k POL1 0.1u(Note 3) 0.1u(Note 3) VPOL& Tone 4X1 , provides maximum input voltage protection for the POL1 , 2 pins. The low pass filter of tone detection


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PDF L8312 L8312 QW-R123-016
1998 - x6750

Abstract:
Text: 41 42 43 44 45 46 47 48 49 50 POL2 POL1 D25 D24 D23 D22 D21 D20 D15 D14 51 , Latch address selector 6 planes 384 latch circuits (1) POL1 POL2 VLCD VCC GND V5 to V9 , , EIO2) and controls internal timing signals. 2. Data inversion circuit Uses the POL1 and POL2 signals , this clock. CL2 1 Input Display data is stored at the falling edge of this clock. POL1 , interface. When POL1 /POL2 is high, display data is inverted in the driver. When POL1 /POL2 is low, display


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PDF HD66323 64-level ADE-207-294 HD66323 HD66323s x6750 d388 2SC3117S cl1100 D3837 D387 Hitachi DSA00164 x1300 X7250
2010 - 2 channel tone receiver circuit

Abstract:
Text: CENB2 FIN2 POL2 POL1 FIN1 CENB1 GND S1D S1C S1B S1A DESCRIPTION Channel 2 Switch Output A Channel 2 , S2B S2C S2D S1A S1B S1C S1D GND CENB1 10n FIN1 POL1 1k 1k VCC VCC CENB2 1k 1k 10n FIN2 POL2 , be adjusted. The resistor also provides maximum input voltage protection for the POL1 , 2 pins. The


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PDF L8312 L8312 QW-R123-016 2 channel tone receiver circuit
2013 - Not Available

Abstract:
Text: POL1 FIN1 CENB1 GND S1D S1C S1B S1A DESCRIPTION Channel 2 Switch Output A Channel 2 Switch , 1k CENB1 10n 10n FIN2 1k POL2 FIN1 1k 1k POL1 0.1u(Note 3) 0.1u(Note , provides maximum input voltage protection for the POL1 , 2 pins. The low pass filter of tone detection


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PDF L8312 L8312 QW-R123-016
1999 - cdi circuit diagram

Abstract:
Text: CDI POL1 POL0 TE S T B AU D C K X1 6 TD O R TS O · RJ-009 supports async character length , POL0-1. Table 4. Polarity Control POL1 POL2 0 0 0 1 1 TDO, RTSO TDI, RTSI RTSI , Enable/Disable Autobaud Circuit S D TE SYNC , POL1 , POL0, LENG TH1, LEN GTH0 , SHSTO P R TS I , POL1 I 20 CDI I 21 RCLK 22 RDI I S 23 TCLK I S 24 VCC


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PDF RJ-009 24-pin, RJ-009 cdi circuit diagram RJ009 dc dc for CDI Circuit MS-001-AF
2001 - CXA2153S

Abstract:
Text: . Clamp 12 OSD_BLK 9 Rch GAMMA1/GAMMA2/GM OFF POL1 /POL2 G_BKG 20 OSD GAIN R_BKG 21 , 01h BIT 2 B_DRV 0Ah 0Bh POL1 0Ch SHP WIDTH GAMMA1 POL2 SHP , SHP OFF is assumed to be 0dB. Sub Address 1011 POL1 (1) Controls the polarity of the correction , (100 [IRE] = 0.7Vp-p) to the RGB inputs, and measure the output amplitude. GAM1: GAMMA1 = 3/ POL1 = 1, Vin = 0.105Vp-p GAM2: GAMMA1 = 3/ POL1 = 0, Vin = 0.105Vp-p GAM3: GAMMA2 = F/POL2 = 1, Vin = 0.42Vp


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PDF CXA2153S CXA2153S 180MHz@ 30PIN SDIP-30P-01 P-SDIP30-8 TF12 TF22 TR12 TR22
Supplyframe Tracking Pixel