The Datasheet Archive

PSB126-2iR datasheet (2)

Part ECAD Model Manufacturer Description Type PDF
PSB126-2iR PSB126-2iR ECAD Model Power-One IC CONV DC-DC STEP DOWN 15 TO 40VIN Original PDF
PSB126-2iRG PSB126-2iRG ECAD Model Power-One IC CONV DC-DC STEP DOWN 15 TO 40VIN Original PDF

PSB126-2iR Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2011 - PSB125-7iR

Abstract: PSB245-7iR
Text: No file text available


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PDF BCD20026-G 18-May-2011 PSB125-7iR PSB245-7iR
PSB245-7iR

Abstract: No abstract text available
Text: No file text available


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PDF BCD20026-G 18-May-2011 PSB245-7iR
1992 - B129

Abstract: B248 B249 B256 B257 SN74ACT2226 SN74ACT2228
Text: 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and SN74ACT2228 are dual FIFOs , per FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or 2HF), and , input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the low-to-high , to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , 1AF/AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE 2OR 2Q FIFO 256 × 1 SN74ACT2228


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PDF SN74ACT2226, SN74ACT2228 SCAS219A SN74ACT2226 24-Pin B129 B248 B249 B256 B257 SN74ACT2226 SN74ACT2228
1992 - B129

Abstract: B248 B249 B256 B257 SN74ACT2226 SN74ACT2228
Text: 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and , . Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF , ) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , ALMOST FULL/EMPTY RDCLK OUT RDY 1HF 1AF/AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE


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PDF SN74ACT2226, SN74ACT2228 SCAS219C SN74ACT2226 24-Pin B129 B248 B249 B256 B257 SN74ACT2226 SN74ACT2228
B129

Abstract: B249 SN74ACT2227 SN74ACT2229
Text: signals and status flags for independent operation. Output flags per FIFO include input ready (1IR or 2IR , ) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both , input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK , jlor ] 1q_ ]2reset ]vcc ]vCc j 2d ] 2ir ] 2wrten ] 2wrtclk ] 2af/ae ] 2hf PRODUCTION DATA , 15 16 11 10 11R 1HF 1AF/AE 10R 1Q 2IR 2HF 2AF/AE 20R 2Q 1RESET 1 WRTCLK 1 WRTEN 1RDCLK 10E


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PDF 28-Pin SN74ACT2227 SN74ACT2229 SN74ACT2227) SN74ACT2229) SN74ACT2227 SN74ACT2229 flThl723 65s303 B129 B249
62d18

Abstract: fifo ttl B129 B249 SN74ACT2226 SN74ACT2228
Text: 1D[ 6 19 ]vcc GND [ 7 18 ]2D 1 RESET [ 8 17 ] 2IR 2Q [ g 16 ] 2WRTEN 20R [ 10 15 Î2WRTCLK 2RDEN , input ready (1IR or 2IR ), output ready (10R or 20R), half full (1HF or 2HF), and almost full/almost , (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the low-to-high transition of the , . Each input-ready flag (1IR or 2IR ) Is synchronized by two flip-flop stages to its write clock (1WRTCLK , symbolst 1IR 1HF 1AF/AE 10R 1Q 2IR 2HF 2AF/AE 20R 2 Q 1RESET 1WRTCLK 1WRTEN 1RDCLK 1RDEN 1D 2RESET


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PDF SN74ACT2226, SN74ACT2228 256x1 SCAS219A SN74ACT2226 24-Pin SN74ACT2226 SN74ACT2228 62d18 fifo ttl B129 B249
1992 - B129

Abstract: B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description , for independent operation. Output flags per FIFO include input ready (1IR or 2IR ), output ready (1OR , write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is , high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , 2IR 2HF 2AF/AE 2OR RDEN 10 RESET 2Q FIFO 256 × 1 SN74ACT2229 IN RDY WRTCLK


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PDF SN74ACT2227, SN74ACT2229 SCAS220B SN74ACT2227 28-Pin B129 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
1992 - A 1HF

Abstract: B129 B248 B249 B256 B257 SN74ACT2226 SN74ACT2228 Texas Instruments TTL handbook
Text: 17 9 16 10 15 11 14 12 13 1RDCLK 1RDEN 1OR 1Q 2RESET VCC 2D 2IR , (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE , (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR , input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK , /AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE 2OR 2Q FIFO 256 × 1 SN74ACT2228 RESET


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PDF SN74ACT2226, SN74ACT2228 SCAS219B SN74ACT2226 24-Pin A 1HF B129 B248 B249 B256 B257 SN74ACT2226 SN74ACT2228 Texas Instruments TTL handbook
1992 - SCAA006

Abstract: B129 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description , for independent operation. Output flags for each FIFO include input ready (1IR or 2IR ), output ready , write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is , high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , /EMPTY EN2 15 16 11 OUT RDY 2IR 2HF 2AF/AE 2OR RDEN 10 RESET 2Q FIFO 256


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PDF SN74ACT2227, SN74ACT2229 SCAS220C SN74ACT2227 28-Pin SCAA006 B129 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
1992 - B129

Abstract: ON B34 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description , for independent operation. Output flags per FIFO include input ready (1IR or 2IR ), output ready (1OR , write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is , high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , 2IR 2HF 2AF/AE 2OR RDEN 10 RESET 2Q FIFO 256 × 1 SN74ACT2229 IN RDY WRTCLK


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PDF SN74ACT2227, SN74ACT2229 SCAS220B SN74ACT2227 28-Pin B129 ON B34 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
PSB-4836D

Abstract: transformer 230V to 12V 500mA PSB-1036 12012 transformer 122d PSB-161 Transformer 115V 24V 4836d PSB-1206 PSB-1036D
Text: No file text available


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PDF 115/230V 50/60Hz 2500Vrms -25OC PSB-101 PSB-102 PSB-106 PSB-1012 PSB-1020 PSB-1036 PSB-4836D transformer 230V to 12V 500mA PSB-1036 12012 transformer 122d PSB-161 Transformer 115V 24V 4836d PSB-1206 PSB-1036D
2007 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF E244637 115/230V 50/60Hz 2500Vrms -25OC PSB-101 PSB-102 PSB-106 PSB-1012 PSB-1020
1992 - B129

Abstract: B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description , for independent operation. Output flags for each FIFO include input ready (1IR or 2IR ), output ready , write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is , high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , /EMPTY EN2 15 16 11 OUT RDY 2IR 2HF 2AF/AE 2OR RDEN 10 RESET 2Q FIFO 256


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PDF SN74ACT2227, SN74ACT2229 SCAS220C SN74ACT2227 28-Pin B129 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Texas Instruments TTL handbook

Abstract: B129 B249 B257 SN74ACT2226 SN74ACT2228 memory 256x1 62d18
Text: 1WRTEN [ 4 21 ]1Q 11R [ 5 20 3 2RESET idE 6 19 ]vcc GND E 7 18 ]2D 1RESET E 8 17 j 2IR 2Q E 9 16 , operation. Output flags per FIFO include input ready (1IR or 2IR ), output ready (10R or 20R), half full (1HF , ) input and input-ready flag (1 IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1 IR or 2IR ) is synchronized by two flip-flop stages to , /AE 10R 1Q 2IR 2HF 2AF/AE 20R 2Q ^ Texas Instruments POST OFFICE BOX 655303 • DALLAS. TEXAS


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PDF SN74ACT2226, SN74ACT2228 256x1 SCAS219B SN74ACT2226 SN74ACT2228 24-Pin Texas Instruments TTL handbook B129 B249 B257 memory 256x1 62d18
1992 - Texas Instruments TTL handbook

Abstract: B249 ON B34 B129 B248 B256 B257 SN74ACT2226 SN74ACT2228
Text: 17 9 16 10 15 11 14 12 13 1RDCLK 1RDEN 1OR 1Q 2RESET VCC 2D 2IR , (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE , (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR , input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK , /AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE 2OR 2Q FIFO 256 × 1 SN74ACT2228 RESET


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PDF SN74ACT2226, SN74ACT2228 SCAS219B SN74ACT2226 24-Pin Texas Instruments TTL handbook B249 ON B34 B129 B248 B256 B257 SN74ACT2226 SN74ACT2228
Photodiode vactec

Abstract: Photodiode-Array
Text: 5bE D BOBDbDT D001D7Ô 7Ô7 «VCT VTP Process Photodiodes E G & G VACTEC VTP6085/ 2IR T-41-51 PACKAGE DIMENSIONS inch (mm) .555 (14 10) .4«4 (12.29) (0 43) PRODUCT DESCRIPTION Dual channel, common cathode, large area planar silicon photodiode array mounted in a three lead TO-8 hermetic package. Package incorporates a visible rejection filter. Low junction capacitance permits fast response time , VTP6085/ 2IR UNITS Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. isc Short Circuit Current H =


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PDF D001D7Ã VTP6085/2IR T-41-51 1001c, Photodiode vactec Photodiode-Array
canon power supply circuit diagrams

Abstract: canon ir power supply circuit diagrams
Text: 20 ]ZD 19 ] 2IR 18 ] 2WRTEN 17 ]2WRTCLK 16 ]2AF/AE 15 ]2HF description The SN74ACT2227 and , . Output flags per FIFO include input ready (1IR or 2IR ), output ready (10R or 20R), half-full (1HF or 2HF , input ready flag (11R or 2IR ) output are both high. Serial data is read from a FIFO on the low-to-high , 2HF 1IR 2IR 10E 20E 10R 20R 10 20 NO. 2 16 6, 20 7,8 1 15 5 19 28 14 25 11 24 10 27 13 26 12 9 23 £ 3 , 1RESET, 2RESÉÌ low 1Q, 2Q HR, 2IR 10R, 20R 1AF/AE, 2AF/AE 1AF/AE, 2AF/AE 1HF, 2HF 1AF/AE, 2AF/AE 1HF.2HF


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PDF SN74ACT2227, SN74ACT2229 SN74ACT2227 SN74ACT2229 256X1 canon power supply circuit diagrams canon ir power supply circuit diagrams
B25G

Abstract: No abstract text available
Text: [ 2RDCLK[ 20E [ gnd 7 8 9 22 V CC 21 V CC 20 2D 19 18 17 16 15 10 1 1 12 13 14 2IR , or 2IR ), output ready (10R or 20R), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or , WRTCLKor 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1 IR or 2IR , input-ready flag (1 IR or 2IR ) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK , 1S HALF FULL 16 A L M O S T F U L L /E M P T Y 11 2IR 2HF 2AF/AE 20R OUT RDY 2D H I 4


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PDF SN74ACT2227, SN74ACT2229 B25G
1992 - Not Available

Abstract: No abstract text available
Text: 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and SN74ACT2228 , . Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or , ) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , RDY HALF FULL ALMOST FULL/EMPTY OUT RDY 17 13 14 10 2IR 2HF 2AF/AE 2OR 9 2Q 8 1RESET


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PDF SN74ACT2226, SN74ACT2228 SCAS219C SN74ACT2226 24-Pin
1992 - Not Available

Abstract: No abstract text available
Text: 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and SN74ACT2228 , . Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or , ) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , RDY HALF FULL ALMOST FULL/EMPTY OUT RDY 17 13 14 10 2IR 2HF 2AF/AE 2OR 9 2Q 8 1RESET


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PDF SN74ACT2226, SN74ACT2228 SCAS219C SN74ACT2226 24-Pin
1995 - assembly bresenham algorithms

Abstract: 256KB static RAM 019S NS32032 bit slice processors heidelberg circuit C1995 AN-524 AN-522 NS32CG
Text: now define Ai as Ai e (M a N 2B) a (iQ a iR B) Ai e M a iQ a (N a 2iR ) 2B Therefore substituting Ai , b 1 Hi a 1 e M a (i a 1)Q a lower (N a 2(i a 1)R) 2B b M a iQ a lower (N a 2iR ) 2B b 1 Hi a 1 e Q a lower (N a 2iR ) 2B a 2R 2B b lower (N a 2iR ) 2B b 1 Hi a 1 e Q b 1 a lower (Ti a 2R) 2B , becomes 0 This is due to the definition of residue and modulo The term Ti is defined as (N a 2iR ) b 2B(lower (N a 2iR ) 2B ) which means that 0 s Ti k 2B The same is true for R R e A b B(lower A B ) so


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PDF NS32CG16 assembly bresenham algorithms 256KB static RAM 019S NS32032 bit slice processors heidelberg circuit C1995 AN-524 AN-522 NS32CG
1992 - BLOCK DIAGRAM OF ZIGBEE

Abstract: B256 B257 SN74ACT2226 SN74ACT2228 B129 B248 B249
Text: 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and , . Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF , ) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , ALMOST FULL/EMPTY RDCLK OUT RDY 1HF 1AF/AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE


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PDF SN74ACT2226, SN74ACT2228 SCAS219C SN74ACT2226 24-Pin BLOCK DIAGRAM OF ZIGBEE B256 B257 SN74ACT2226 SN74ACT2228 B129 B248 B249
1992 - B129

Abstract: B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description , for independent operation. Output flags for each FIFO include input ready (1IR or 2IR ), output ready , write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is , high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , /EMPTY EN2 15 16 11 OUT RDY 2IR 2HF 2AF/AE 2OR RDEN 10 RESET 2Q FIFO 256


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PDF SN74ACT2227, SN74ACT2229 SCAS220C SN74ACT2227 28-Pin B129 B248 B249 B256 B257 SN74ACT2227 SN74ACT2229
1992 - Not Available

Abstract: No abstract text available
Text: 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and SN74ACT2228 , . Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR), half full (1HF or , ) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from a FIFO on the , asynchronous to one another. Each input-ready flag (1IR or 2IR ) is synchronized by two flip-flop stages to its , RDY HALF FULL ALMOST FULL/EMPTY OUT RDY 17 13 14 10 2IR 2HF 2AF/AE 2OR 9 2Q 8 1RESET


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PDF SN74ACT2226, SN74ACT2228 SCAS219C SN74ACT2226 24-Pin
1992 - b257

Abstract: No abstract text available
Text: 1OE 1RDCLK 1RDEN 1OR 1Q 2RESET VCC VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The , independent operation. Output flags for each FIFO include input ready (1IR or 2IR ), output ready (1OR or 2OR , (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR ) output are both high. Serial data is read from , state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR ) is , ALMOST FULL/EMPTY OUT RDY 15 16 11 2IR 2HF 2AF/AE 2OR 9 1RESET 1WRTCLK 1WRTEN 1RDCLK 1OE 1RDEN 1D 3 4


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PDF SN74ACT2227, SN74ACT2229 SCAS220C SN74ACT2227 28-Pin b257
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