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PLL-11-Y2-2.5 Panduit Corp Avnet - -
PLL-11-Y2-2.5 Panduit Corp Sager - -
SPLL-1198 RF Micro Devices Inc Bristol Electronics - -

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PLL11 datasheet (2)

Part Manufacturer Description Type PDF
PLL1100A Z-Communications PHASE LOCKED LOOP Original PDF
PLL-11-Y2-2.5 Panduit Labels, Labeling, Computers, Office - Components, Accessories, LABEL LSR POLY WHITE 1 X.75" Original PDF

PLL11 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2013 - AK8140A

Abstract:
Text: frequency Output State PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 20h CLK2 Output State CLK3 Output State , ] 0 MDIVP1 [0] 0 PLL1_1 MDIV1 Setting PLL1_1 NDIV1 Integral Part Setting PLL1_1 NDIV1 Fractional Part , . Please set PLL parameter according to . PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and , frequency of PLL is chosen from two setups PLL1_0 and PLL1_1 . FS1_x 0 1 PLL1 Frequency PLL1_0 Predefined by


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PDF AK8140A AK8140A 230MHz. 24-pin 16M-60MHz 4M-100MHz draft-E-06 CLK30 PLL11
2006 - 13M-pixel

Abstract:
Text: bit clock. MODES (1,2,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some , ( PLL1=1 , PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge Rate Mode: SLOW MODE 1 (S1=1, S0 , =1 100 PLL1=1 , PLL0=0 50 PLL1=1 , PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH


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PDF FIN212AC 12-Bit FIN212AC 13M-pixel AN-5058 AN-5061 FIN212ACGFX FIN212ACMLX MO-195 MO-220
2006 - FIN212AC

Abstract:
Text: bit clock. MODES (1,2,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some , : MODE 1 (S1=0, S0=1) CKREF=26MHz STROBE Frequency = 10 MHz PLL Divide Mode: Divide-by 2 ( PLL1=1 , PLL0 , fSTRB PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 50 PLL1=1 , PLL0=1 fSTRB 100 33 /3 %


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PDF FIN212AC 12-Bit FIN212AC MO-195 FIN212ACMLX FIN212ACGFX FIN212ACBFX 337 BGA footprint DP10 AN-5061 AN-5058 5M cmos camera
2006 - Not Available

Abstract:
Text: ,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some microcontroller applications , PLL Divide Mode: Divide-by 2 ( PLL1=1 , PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1


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PDF FIN212AC 12-Bit FIN212AC
2006 - 35x45mm

Abstract:
Text: ,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some microcontroller applications , Frequency = 10 MHz PLL Divide Mode: Divide-by 2 ( PLL1=1 , PLL0=0) Multiplier x 3.5 Deserializer , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1


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PDF FIN212AC 12-Bit FIN212AC 35x45mm 6X6 mlp
2006 - Not Available

Abstract:
Text: ,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some microcontroller applications , =1) CKREF=26MHz STROBE Frequency = 10 MHz PLL Divide Mode: Divide-by 2 ( PLL1=1 , PLL0=0) Multiplier x 3.5 , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1


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PDF FIN212AC 12-Bit FIN212AC 32-Lead, 42-Ball,
2006 - FIN212AC

Abstract:
Text: ,3); PLL1=1 ,PLL0=0 (Divide-by-2) or PLL1=1 ,PLL0=1 (Divide-by-3) For some microcontroller applications , PLL Divide Mode: Divide-by 2 ( PLL1=1 , PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge , fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1 , PLL0=1 tCPWH tCPWL tCLKT tSPWH/L tSTC tHTC CKREF DC


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PDF FIN212AC 12-Bit FIN212AC 42-Ball, 36-Ball,
2006 - FIN212AC

Abstract:
Text: STROBE CLKCKREF 10MHzCLK70MHz 140Mbps (1,2,3) PLL1=1PLL0=02 PLL1=1PLL0=13 STROBE 2 , (S1=0, S0=1) CKREF=26MHz STROBE =10 MHz PLL 2 ( PLL1=1 , PLL0=0) x 3.5 MODE 1 (S1=1, S0=0) 13 , =1 fCKREF 18 10 28 MHz PLL1=0, PLL0=0 CKREF tCPWH tSPWH/L tSTC tHTC PLL1=1 , tCLKT 100 T=1/fCKREF CKREF DC tCPWL fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0


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PDF FIN212AC AN-5058 AN-5061 FIN212ACMLX 32MLPJEDEC MO-2205 FIN212ACGFX MO1953 FIN212ACBFX FIN212AC 337 BGA footprint AN-5058 AN-5061 DP10 FIN212ACBFX FIN212ACGFX FIN212ACMLX MO-220
PHKI

Abstract:
Text: PEÍ1E nPOME}KyTOHHblEflByxn03HL4l40HHblE PR-&: Pfl-9, Pll-11 , PF1-12 O Bilí M E CßEflEHHil Peíií npgnfleÄLy-rc'HHbie flgyxnciJHmiPHHUç Tunçp Pfl-S. PII-II npçflH^SHâ-HÇHbi flna BKmoHSHUp p ueniíi nooTOHHHoro TOtía pene TtinciB PrVá¡ pn-12- e nenn nepewEHHnrci rana yacroTpw 50 n.nn GCH~u e ^ewecTee BcnownrgTenbHorn pene h cxeiwa* 3(3iuMTbi sMeprnc^CT&i'i Psne nweKji nQBbiLueHHyio ytfoSNmoriïk u ^exaHHHecunw snsaeñctb m n m li he n swehnun no n pm^hlki Koi-rrairrOfl n pu chwt^h hi* l- n n mc-ibïihcieiiÃ


OCR Scan
PDF KyTOHHblEflByxn03HL4l40HHblE Pll-11, PF1-12 pn-12- PHKI
2007 - hand calculator

Abstract:
Text: Two PLL Outputs Source Register Source Clock CLK5 PLL11 Destination Register INBUF


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PDF PLL10 hand calculator calculator on chip HC210 HC220 HC230 HC240 uncertainty
2008 - FIN212AC

Abstract:
Text: =0) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) ~50% CKP PW,(PWS1=PWS0=0) CKREF=26MHz & STROBE , 28 PLL1=0, PLL0=0 Strobe Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 fCKREF fSTRB 100 50 PLL1=1 , PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH


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PDF FIN212AC 12-Bit 12-Bit 40MHz 32-Terminal 42-Ball FIN212ACMLX FIN212ACGFX FIN212AC mobile camera interface microcontroller FIN212ACMLX FIN212ACGFX DSO20 dsi LCD driver DP1211 5M cmos camera 30 pin flex cable lcd 202 ball bga
2009 - Not Available

Abstract:
Text: – 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) ~50% CKP , 30 PLL1=0, PLL0=0 Strobe Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 fCKREF ≠fSTRB 94.7 50 PLL1=1 , PLL0=1 fSTRB MHz 331/3 % of fCKREF


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PDF FIN210AC 10-Bit 48MHz 10-bit 32-Terminal 42-Ball FIN210ACMLX FIN210ACGFX
2007 - AE31

Abstract:
Text: VCCA_PLL11 VCCD_PLL11 VCC_PLL11_OUT IO CLK14p IO CLK14n IO CLK15p IO CLK15n IO PLL11_OUT0p IO PLL11_OUT0n IO PLL11_OUT1p IO PLL11_OUT1n IO PLL11_FBp /OUT2p IO PLL11_FBn /OUT2n IO IO IO IO , Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin should be connected to the voltage level of the target device which PLL11 in bank 11 is driving. Refer to the data sheet for absolute maximum voltage rating on


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PDF PT-EP1AGX90E-1 PLL12 EP1AGX90E AE31 pll-11
2007 - EP1AGX20CF484

Abstract:
Text: PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. Connection Guidelines This , PLL11 ). When these pins are not used, they may be left floating PLL11_OUT [1,0]n (Note 4, 6) Output Optional negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be , PLL11_OUT [1,0]p (Note 4, 6) Output Optional positive external clock outputs [1,0] from enhanced PLL


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PDF PCG-01002-1 EP1AGX20CF484 PLL11
2009 - EP1AGX20CF484

Abstract:
Text: PLL11 clock outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin , negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or , ° out-ofphase. Output Optional positive external clock outputs [1,0] from enhanced PLL11. These pins can be , ]p PLL6_OUT[1,0]n PLL11_OUT [1,0]p PLL11_OUT [1,0]n PLL12_OUT[1,0]p PLL12_OUT[1,0]n


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PDF PT-EP1AGX20C-1 RX28p RX28n TX28p TX28n RX27p RX27n TX27p TX27n RX26p EP1AGX20CF484
2009 - pll-11

Abstract:
Text: outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin should be , enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or 180° out-of-phase. Output Optional positive , external clock outputs [1,0] from enhanced PLL11. These pins can be differential (two output pin pairs) or , IO, Input Pin Name PLL5_OUT[1,0]n PLL6_OUT[1,0]p PLL6_OUT[1,0]n PLL11_OUT [1,0]p PLL11_OUT


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PDF PT-EP1AGX35C/D-1 RX28p RX28n TX28p TX28n RX27p RX27n TX27p TX27n RX26p pll-11
2009 - FIN210AC

Abstract:
Text: ­ 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) ~50% CKP , CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 fCKREF fSTRB 94.7 50 PLL1=1 , PLL0


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PDF FIN210AC 10-Bit 48MHz 10-bit 32-Terminal 42-Ball FIN210ACMLX FIN210ACGFX FIN210AC 13M-pixel FIN210ACMLX FIN210ACGFX FIN210 DSO20 Dp 104 ckp5e 577ns PWS1.1
2008 - DP1211

Abstract:
Text: is twice as fast STROBE ( PLL1=1 ; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2008 Fairchild , Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1 , PLL0=1 tCPWH tCPWL tCLKT tSPWH/L CKREF DC


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PDF FIN212AC 12-Bit 40MHz 48MHz 32-Terminal 42-Ball FIN212ACMLX DP1211 337 BGA footprint
2008 - 577ns

Abstract:
Text: Range (S1=0, S0=1) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz , Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1 , PLL0=0 PLL1=1 , PLL0=1 tCPWH tCPWL


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PDF FIN212AC 12-Bit 40MHz 32-Terminal 42-Ball FIN212ACMLX FIN212ACGFX 577ns
2009 - emi line filter 48MHz

Abstract:
Text: =1, S0=0) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) ~50% CKP PW,(PWS1=PWS0=0) CKREF=26MHz & , Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 fCKREF fSTRB 94.7 50 PLL1=1 , PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH CKREF DC T=1/fCKREF


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PDF FIN210AC 10-Bit 48MHz 10-bit 32-Terminal 42-Ball FIN210ACMLX FIN210ACGFX emi line filter 48MHz FIN210AC Dp 104 mobile camera interface microcontroller JESD22-A114 FIN210ACMLX FIN210ACGFX 30 pin flex cable lcd FIN210 DSO20
2013 - AK8140A

Abstract:
Text: two setups, PLL1_0 or PLL1_1 . Table 2. PLL1 Output Frequency Selection (Address: 20h) FS1_x PLL1 Frequency 0 PLL1_0 Predefined by address: 21h, 22h ~ 26h (Default) 1 PLL1_1 , [10] 0 FRAC1 [9] 0 FRAC1 [8] 0 PLL1_1 NDIV1 Fractional Part Setting 29h FRAC1 , ] INT1[0] 0 0 0 0 0 0 0 0 PLL1_1 NDIV1 Integral Part Setting MDIVC1 [3 , MDIVP1 [1] 0 MDIVP1 [0] 0 PLL1_1 MDIV1 Setting PLL1 Frequency Selection 20h 21h


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PDF AK8140A] AK8140A AK8140A 230MHz. 24-pin MS1441-E-02
2009 - Dp 104

Abstract:
Text: ­ 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE ( PLL1=1 ; PLL0=0) ~50% CKP , CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1 , PLL0=0 fCKREF fSTRB 94.7 50 PLL1=1 , PLL0


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PDF FIN210AC 10-Bit 48MHz 10-bit 32-Terminal 42-Ball FIN210ACMLX FIN210ACGFX Dp 104 30 pin flex cable lcd mobile camera interface microcontroller JESD22-A114 FIN210ACMLX FIN210ACGFX FIN210AC FIN210 DSO20 PWS1.1
2007 - B14 DIODE

Abstract:
Text: External clock output VCCIO power for PLL11 clock outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin should be connected to the voltage level of the target device , ] from enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p , are considered one pair) can be either in phase or 180 degrees out of phase. PLL11_OUT [1,0]p Output PLL11_OUT [1,0]n Output PLL12_OUT[1,0]p Output PLL12_OUT[1,0]n Output Optional


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PDF PT-EP1AGX20C-1 RX28p RX28n TX28p TX28n RX27p RX27n TX27p TX27n RX26p B14 DIODE EP1AGX20CF484
2007 - Stratix II GX

Abstract:
Text: External clock output VCCIO power for PLL11 clock outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin should be connected to the voltage level of the target device , floating. PLL11. If the clock outputs are single-ended, each pair of pins (i.e. PLL11_OUT0p and , Output PLL6_OUT[1,0]n Output PLL11_OUT [1,0]p (Note 4, 6) Output PLL11_OUT [1,0]n (Note 4, 6 , [1,0] from enhanced PLL11. When these pins are not used, they may be left floating. These pins can


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PDF PCG-01001-3 Stratix II GX PCG-01001
2007 - Not Available

Abstract:
Text: Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT [1.0]p, PLL11_OUT [1.0]n, PLL11_FBp /OUT2p, and PLL11_FBn /OUT2n. This pin should be connected to the voltage level of the target device , enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e. PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. Output Optional , clock outputs [1,0] from enhanced PLL11. These pins can be differential (two output pin pairs) or


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PDF PT-EP1AGX35C/D-1 RX28p RX28n TX28p TX28n RX27p RX27n TX27p TX27n RX26p
Supplyframe Tracking Pixel