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LTC6905MPS5#TR Linear Technology IC PLL FREQUENCY SYNTHESIZER, PDSO5, PLASTIC, SOT-23, 5 PIN, PLL or Frequency Synthesis Circuit
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LT1310EMSE Linear Technology LT1310 - 1.5A Boost DC/DC Converter with Phase-Locked Loop; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
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PLL-11-Y2-2.5 datasheet (1)

Part Manufacturer Description Type PDF
PLL-11-Y2-2.5 Panduit Labels, Labeling, Computers, Office - Components, Accessories, LABEL LSR POLY WHITE 1 X.75" Original PDF

PLL-11-Y2-2.5 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
PEL-11-Y1C-5

Abstract: PEL-25-Y2Y-10 pll 367 305 5VL PLL-38-Y3-1 PLL-13-Y3-1 PLL-16-Y2-2 PEL-16-Y1-0 marking y2s PEL-A4-Y1-25
Text: -10 PLL-8- Y2 -5 PLL-8- Y2 -10 PLL-9- Y2 -5 PLL-9- Y2 -10 PLL-10- Y2-2.5 PLL-11-Y2-2.5 PLL-12- Y2 -1 PLL-12- Y2-2.5 , x 279.4 mm) Part Number PLL-3-Y3-5 PLL-33-Y3-5 PLL-10-Y3- 2.5 PLL-10-Y3-5 PLL- 11-Y3-2.5 PLL , , OR for Orange, PR for Purple, RD for Red and Y for Yellow. i.e. PLL- 11-Y3B-2.5 has a Blue Print-On , surfaces 0.56 x 0.19 (14.3 x 4.8) PLL-24-Y3-5 only PLL-23-Y3-1 PLL-23-Y3-5 PLL-9-Y3C-5 PLL-10-Y3C- 2.5 PLL- 11-Y3C-2.5 , Format (8.5" x 11 " / 215.9 mm x 279.4 mm) Part Number PLL-30- Y2 -10 PLL-1- Y2 -10 PLL-2- Y2 -10 PLL-31- Y2


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1995 - Not Available

Abstract: No abstract text available
Text: C100X050YJJ replaces JL9C -10, JL9Y-10, PEL -10- Y2 -5, PEL -10-Y3M-5, PEL - 11-Y2 -5, PLL10-PO-5, PLL-10- Y2-2.5 , PLL-11-Y2-2.5 , PLL-6- Y2 -10, PLL-6- Y2 -5, PLL-9- Y2 -10, PLL-9Y2-5, PLL-9-Y3C-5 and PLL-8- Y2 -5 White


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PDF C100X050YJJ' C100X050YJJ PLL10-PO-5, PLL-10-Y2-2 PLL-11-Y2-2 PLL-6-Y2-10, PLL-9-Y2-10,
SIEMENS 3VF

Abstract: epson printer board pm 235 access 2 wash buffer II MSDS LS5-HS3 panasonic ER 203 charger circuit gmv 3010 NEC PINWRITER P7 siemens LS4 MANUAL psmb 325 alps head
Text: downtime · More than 25 font styles and sizes · Exact label registration See pages 6-11 for complete , TM LS3E Hand-Held Dot-Matrix Printer Pages 6 - 11 · Lightweight, versatile printer for high quality , heat shrink DURA-MARK TM PTR2 Thermal Transfer Printer Pages 20 - 25 · High quality, thermal , -6 LWS-8 LWS-7 LWS-4 LWS-5 LWS-1 LWS-9 LWS-2 LWS-3 LWS-10 LWS- 11 LWS-12 LWS-13 LWS-14 v Label Code , page 25 A A Standard Butt-Cut Part Number White LHSW-1 LHSW-2 LHSW-6 LHSW-7 LHSW-3 LHSW


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PDF TTSL8VC3-10 TTSL9VC3-10 TTSL10VC3-5 TTSL247VC3-10 TTSL250VC3-10 SIEMENS 3VF epson printer board pm 235 access 2 wash buffer II MSDS LS5-HS3 panasonic ER 203 charger circuit gmv 3010 NEC PINWRITER P7 siemens LS4 MANUAL psmb 325 alps head
Not Available

Abstract: No abstract text available
Text: VDDQ 3 4 25 GND Y1 CLK 5 24 FBOUT Y2 CLK AVDD 6 23 7 FBOUT , Y2 FBIN AVDD FBOUT 08-0298 1 11 18 VDDQ Y2 FBOUT FBIN 19 12 17 GND VDDQ Y3 13 16 Y3 Y2 Logic and Test Ciruit 20 10 Y1 Y4 9 Y1 Y4 14 15 GND PS8749B 11 /13/08 PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver , for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a


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PDF PI6CV855-02 MO-153F/AE 28-Pin, 173-Mil PI6CV855-02LE 28-pin PS8749B
2008 - PI6CV855-02

Abstract: PI6CV855-02LE
Text: (Pb-free & Green available): - 28-pin TSSOP (L28) The PI6CV855-02 PLL Clock Buffer is designed for 2.5 , 4 25 GND Y1 CLK 5 24 FBOUT CLK AVDD 6 23 FBOUT VDDQ AGND 8 21 FBIN GND Y0 Y0 CLK CLK PLL FBIN FBIN Y2 Y2 Y3 Y3 7 28-Pin 22 L 9 20 FBIN Y1 10 19 Y1 11 18 GND VDDQ FBOUT VDDQ 12 17 Y3 FBOUT Y2 13 16 Y3 Y2 14 15 GND Y4 Logic and Test Ciruit AVDD


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PDF PI6CV855-02 MO-153F/AE 28-Pin, 173-Mil PI6CV855-02LE 28-pin PS8749B PI6CV855-02 PI6CV855-02LE
2002 - Y6 11

Abstract: PI6CV850
Text: Y2 9 40 Y7 Y5 Y2 10 39 Y7 VDDQ 11 38 VDDQ SCLK 12 37 , 2.5 -V Phase Lock Loop Clock Driver with I2C Control Interface Features Description , Functional Control Three-State Outputs when I2C low-level control bit is written Operates from dual 2.5 , 5 6 10 9 23 46 47 44 43 39 40 29 30 14 FBIN FBIN 36 35 GND Y2 1 48 GND Y0 Y2 2 47 Y5 Y0 3 46 Y5 Y3 VDDQ 4 45 VDDQ Y3 Y1


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PDF PI6CV850 whe43210987654321 48-Pin PS8481B Y6 11 PI6CV850
2008 - PI6CV855

Abstract: PI6CV855LE
Text: Y1 11 18 GND VDDQ FBOUT VDDQ 12 17 Y3 FBOUT Y2 13 16 Y3 Y2 14 15 GND Y0 CLK CLK PLL FBIN Y2 Y2 FBIN Logic and Test Ciruit AVDD 08-0298 1 7 28-Pin L PS8545D 11 /12/08 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR , is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The , Y4 VDDQ VDDQ 4 25 GND Y1 CLK 5 24 FBOUT 23 22 FBOUT VDDQ Y3


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PDF PI6CV855 28-pin PI6CV855 MO-153F/AE 28-Pin, 173-Mil PI6CV855LE PS8545D PI6CV855LE
Not Available

Abstract: No abstract text available
Text: 11 18 GND VDDQ VDDQ Y2 12 17 Y3 13 16 Y3 Y2 14 15 GND Y0 CLK Y1 CLK PLL FBIN Y2 Y2 FBIN Logic and Test Ciruit AVDD FBOUT FBOUT 08-0298 1 7 28-Pin L PS8545D 11 /12/08 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR , Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels , VDDQ Y1 VDDQ CLK 4 25 GND 5 24 FBOUT 6 23 22 FBOUT VDDQ Y3


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PDF PI6CV855 28-pin PI6CV855 MO-153F/AE 28-Pin, 173-Mil PI6CV855LE PS8545D
2003 - Not Available

Abstract: No abstract text available
Text: 30 29 28 27 26 25 24 23 22 Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ VDDQ FBOUT FBOUT GND 21 10 11 12 , cription VDDQ AVDD AGND GND 4, 11 ,12,15,21,28,34,38,45 16 17 1,7,8,18,24, 25 ,31,41,42,48 Ground , Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels , Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT CLK CLK FBIN FBIN PLL , D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AG N D GND Y3 Y3 VD D Q Y4 Y4 GND 1 2


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PDF PI6CV857B PC2700 48-pin 40-pin PI6CV857BA PI6CV857BAI PI6CV857BZD PS8639A
2003 - Not Available

Abstract: No abstract text available
Text: 40 GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 , -6201/ 11 IDTCSPT857C 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM PWRDWN TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK CLK , DWN 6 Y5 Y5 Y6 Y6 GND GND NC NC GND GND C Y7 Y7 NC NC Y2 Y2 D FBIN VDDQ FBOUT , RANGES PIN CONFIGURATIONS VDDQ VDDQ GND Y6 Y6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


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PDF IDTCSPT857C 60MHz 220MHz 100ps PC1600 PC2700 PC3200
2006 - CSPT857D

Abstract: DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
Text: FBIN GND 8 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 AVDD 8 23 VDDQ 39 Y7 AGND 9 22 FBOUT VDDQ 11 38 , Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 PLL FBIN Y6 FBIN Y6 Y7 Y7 Y8 Y8 , GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ , 30 Y7 VDDQ 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28


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PDF IDTCSPT857D 60MHz 220MHz 100ps PC1600 PC2700 PC3200 CSPT857D DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
2003 - Not Available

Abstract: No abstract text available
Text: DAC in the DAC5686 has an 11 -bit offset adjustment and 12-bit gain adjustment, which compensate for , BIASJ A Offset FIR1 FIR2 FIR3 FIR4 FIR5 x sin(x) A Gain DEMUX DA[15:0] y2 y2 y2 y2 16-Bit DAC IOUTA1 IOUTA2 DB[15:0] y2 TxENABLE y2 y2 y2 x sin(x) 16 , 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 DA6 25 Top View 100 HTQFP DAC5686 64 63 62 61 60 59 58 57 56 55 54 53 52 50 51


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PDF DAC5686 SLWS147C 16-BIT, 500-MSPS, 72-MHz 44-MHz 16-MHz 05-dB 80-dB
2003 - Not Available

Abstract: No abstract text available
Text: 27 26 25 24 23 22 21 Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ 40 GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND , ] Pin Number 17 16 13, 14 35, 36 32, 33 1, 7, 8, 18, 24, 25 , 31, 41, 42, 48 37 4, 11 , 12, 15, 21, 28, 34 , Information for details. FUNCTIONAL BLOCK DIAGRAM PWRDWN TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK , GND GND NC NC GND GND C Y7 Y7 NC NC Y2 Y2 D FBIN VDDQ FBOUT Y8 Y8 Y9 Y9 5 VDDQ , Y6 Y6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40


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PDF IDTCSPT857C 60MHz 220MHz PC1600 DDR200) PC2100 DDR266) PC2700 DDR333)
2003 - us 857d

Abstract: No abstract text available
Text: 7 42 GND CLK 5 26 FBIN GND 8 41 GND CLK 6 25 FBIN Y2 , Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 PLL FBIN Y6 FBIN Y6 Y7 , NC VDDQ GND 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 A B C D E F J K H G , CONFIGURATIONS 3 46 Y5 GND 1 30 Y7 VDDQ 4 45 VDDQ Y2 2 29 Y7 Y1


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PDF IDTCSPT857D CSPT857D 20MHz, us 857d
2006 - CSPT857C

Abstract: DDR1-400 DDR200 IDTCSPT857C PC2100 PC2700 PC3200
Text: 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 , PWRDWN AVDD TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 , GND VDDQ NC NC NC NC VDDQ GND 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 A B C D , 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28 VDDQ Y1 6


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PDF IDTCSPT857C 60MHz 220MHz 100ps PC1600 PC2700 PC3200 CSPT857C DDR1-400 DDR200 IDTCSPT857C PC2100 PC2700 PC3200
2006 - CSPT857D

Abstract: DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
Text: FBIN GND 8 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 AVDD 8 23 VDDQ 39 Y7 AGND 9 22 FBOUT VDDQ 11 38 , TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM PWRDWN AVDD TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 , Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND , 30 Y7 VDDQ 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28


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PDF IDTCSPT857D 60MHz 220MHz 100ps PC1600 PC2700 PC3200 CSPT857D DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
silego

Abstract: Silego Technology 48-TVSOP SLGVF857C-14 CVF857 SLGVF857 40-VFQFN DDR400 SLGVF857C 48TVSOP
Text: SLGVF857C-14 2.5 2.5V Low Power PLL Clock Driver for DDR1 Features: · 1:10 SSTL2 diffrential , CLK . . GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD GND , . . . . Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SLGVF857C-14 . Pin , .50mA 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25


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PDF SLGVF857C-14 PC1600/2100/2700 PC3200 60MHz 220MHz CVF857 JESD82-1A silego Silego Technology 48-TVSOP SLGVF857C-14 CVF857 SLGVF857 40-VFQFN DDR400 SLGVF857C 48TVSOP
2006 - Not Available

Abstract: No abstract text available
Text: 40 GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 , RANGES FUNCTIONAL BLOCK DIAGRAM PWRDWN TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK CLK FBIN , DWN 6 Y5 Y5 Y6 Y6 GND GND NC NC GND GND C Y7 Y7 NC NC Y2 Y2 D FBIN VDDQ FBOUT , RANGES PIN CONFIGURATIONS VDDQ VDDQ GND Y6 Y6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y5


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PDF IDTCSPT857C 60MHz 220MHz 100ps PC1600 PC2700 PC3200
Not Available

Abstract: No abstract text available
Text: 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 , LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 PLL FBIN Y6 FBIN Y6 , NC NC NC NC VDDQ GND 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 A B C D E F , 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28 VDDQ Y1 6


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PDF IDTCSPT857C 60MHz 220MHz 100ps PC1600 PC2700 PC3200
CX857

Abstract: SILEGO Silego Technology 40-VFQFN CX-857 48-TVSOP 48TVSOP SLGVF857 PC3200 CVF857
Text: . . . Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SLGVF857H/L . CLK GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD GND GND Y3 Y3 VDDQ Y4 Y4 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 , 31 Y1 Y1 VDDQ Y0 Y0 Y5 Y5 VDDQ Y6 Y6 (Top View) 30 29 28 27 26 25 24 23 22


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PDF SLGVF857 PC1600/2100/2700/3200 PC1600/2100/2700 PC3200 60MHz 220MHz CVF857 CX857 JESD82-1A SILEGO Silego Technology 40-VFQFN CX-857 48-TVSOP 48TVSOP SLGVF857 PC3200 CVF857
2003 - T0002

Abstract: T0003 DAC5686 DAC5686IPZP IS-136 18v transformer
Text: in unwanted sideband and local oscillator feedthrough. Each DAC in the DAC5686 has an 11 -bit offset , CLK1 1.2 V Reference CLK1C CLK2C A Offset FIR1 y2 FIR2 y2 FIR3 y2 y2 y2 A Gain FIR5 FIR4 x sin(x) y2 16-Bit DAC x sin(x) y2 DB[15:0] y2 , 9 67 PLLVDD AVDD 10 66 LPF EXTIO 11 65 PLLGND AGND 12 64 , . I/O DESCRIPTION AGND 1, 4, 7, 9, 12, 17, 19, 22, 25 I Analog ground return AVDD


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PDF DAC5686 SLWS147B 16-BIT, 500-MSPS, 72-MHz 44-MHz 16-MHz 05-dB 80-dB T0002 T0003 DAC5686 DAC5686IPZP IS-136 18v transformer
TC9174F

Abstract: No abstract text available
Text: , 10,12.5, 25 , 50,100kHz) to Pulse swallow system and direct frequency division system are , stops automatically. Rf2 V DD X t O ' Ì - 11 1 1) When a device is reset (V d d = 0 , - 11 /53 TOSHIBA TC9309AF DESCRIPTION OF OPERATION O cpu The CPU consists of a , Operation of in Item 11 ) 10. List of instructions sets Total 61 instruction sets are available and they are , SLTI SGEI SEQI SNEI MVSR MVIM M-|, M 2 M, I 11 3 M, I M, I M, I M, I ORR r, M ANDR r, M AC ACS ACN


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PDF TC9309AF DTS-10) TC9309AF 80pin QFP80-P-1420-0 TC9174F
2006 - 74LVC1G125

Abstract: TLV320AIC33 SN74CBTLV1G125 PLL1705 PI6CX100-27W DM643x CDCE949 CDCE925 CDCE913 U1-212
Text: Vctr GND Y1 GND Vddout Y2 Vddout Y3 14 13 12 11 I2C or Control Pin I2C or , S2/SCL Vctr Y1 4 5 GND 6 GND Vddout Y2 Vddout Y3 7 14 13 12 11 , frequency. Besides the video and audio clocks, a 27-MHz and a 25 -MHz Ethernet clock signals are generated , CSEL AGND FS1 VCC FS2 VDD1 SR VDD2 VDD3 10 11 PI6CX100-27W XT1 MCKO1 , of the outputs (Y1 and Y2 ) are PLL bypassed and generate a 27-MHz video clock. Y3 outputs are PLL


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PDF SCAA083 DM643x PI6CX100-27W, PLL1705, 74LVC1G125 TLV320AIC33 SN74CBTLV1G125 PLL1705 PI6CX100-27W CDCE949 CDCE925 CDCE913 U1-212
2003 - CSPT857C

Abstract: DDR1-400 DDR200 IDTCSPT857C PC2100 PC2700 PC3200
Text: 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 , PWRDWN AVDD TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 , GND VDDQ NC NC NC NC VDDQ GND 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 A B C D , 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28 VDDQ Y1 6


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PDF IDTCSPT857C CSPT857C 20MHz, DDR1-400 DDR200 IDTCSPT857C PC2100 PC2700 PC3200
us 857d

Abstract: CSPT857D DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
Text: 42 GND CLK 5 26 FBIN GND 8 41 GND CLK 6 25 FBIN Y2 9 , TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM PWRDWN AVDD TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 PLL FBIN Y6 FBIN Y6 Y7 Y7 Y8 Y8 Y9 Y9 , Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ , 3 46 Y5 GND 1 30 Y7 VDDQ 4 45 VDDQ Y2 2 29 Y7 Y1 5


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PDF IDTCSPT857D CSPT857D 20MHz, us 857d DDR1-400 DDR200 IDTCSPT857D PC2100 PC2700 PC3200
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