The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC3733CUHF-1#TR Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC1706EMS-63#TRPBF Linear Technology LTC1706-63 - 5-Bit VID Voltage Programmer for Sun CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC3733CUHF-1#PBF Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC1706EMS-61#TR Linear Technology LTC1706-61 - 5-Bit VID Voltage Programmer for AMD Opteron CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC1706EMS-61 Linear Technology LTC1706-61 - 5-Bit VID Voltage Programmer for AMD Opteron CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC3733CUHF-1 Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C

PLB DDR2 with OPB Central DMA Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - PLB DDR2 with PLB Central DMA

Abstract: DDR2 SDRAM ECC and Application Note PLB DDR2 with OPB Central DMA DS472 ML410 XAPP935 plb 405
Text: System: PLB DDR2 with OPB Central DMA Author: James Lucero This reference system demonstrates the , following sections explain the configuration of the PLB DDR2 memory controller with ECC, the OPB Central , for OPB Central DMA operations to be performed on the PLB DDR2 memory controller on the PLB bus, a , utilize OPB Central DMA to test DMA operations inside the PLB DDR2 memory space. The reference system is , controller with ECC, the OPB Central DMA controller, and the OPB2PLB bridge for communication between the


Original
PDF XAPP935 DS472, ML410 PLB DDR2 with PLB Central DMA DDR2 SDRAM ECC and Application Note PLB DDR2 with OPB Central DMA DS472 XAPP935 plb 405
2008 - PPC460EX

Abstract: PPC440EPx-SUA667T SGMII PCIE bridge PPC460SX powerpc 464 embedded powerpc 440GX ppc460 1600DMIPS amcc 460EX kilauea
Text: Code Decompression UART 133MHz Processor Local Bus ( PLB ) 64-Bit OPB Bridge DMA Controller , Processor Local Bus ( PLB ) 64-Bit On-Chip Peripheral Bus ( OPB ) Memory and Bus Architecture UART , and Bus Architecture On-Chip Peripheral Bus ( OPB ) · 32-bit DDR1/2 SDRAM controller with ECC , interrupts · Up to 32 general purpose I/Os · DMA Controller with four independent channels · Two PCI Express , Architecture On-Chip Peripheral Bus ( OPB ) · 32-bit DDR1/2 SDRAM controller with ECC, supports both x16 or


Original
PDF 460SX 10/100/1G 32KI/32KD 256KB 440GX 64-bit 32-bit 440SP PPC460EX PPC440EPx-SUA667T SGMII PCIE bridge PPC460SX powerpc 464 embedded powerpc 440GX ppc460 1600DMIPS amcc 460EX kilauea
2008 - busview

Abstract: ML555 ML555 MEMORY ML410 XPS Central DMA XAPP999 XAPP998 XAPP964 PPC405 PLB DDR2 with OPB Central DMA
Text: directory provides tcl scripts used for DMA transactions. Introduction Xilinx offers OPB PCI, PLB PCI , operation with XMD commands, the XPS Central DMA control, source address, destination address, and length , . The Results section provides bus transfer rate and latency results for the OPB PCI, PLB PCI, and , example is a DMA transaction from ML410 BRAM to ML555 DDR2 . Generics are parameters that are used to , xps_central_dma is used. The location of the registers in XPS Central DMA for generating a DMA transaction are


Original
PDF XAPP998 ML410 ML555 busview ML555 MEMORY XPS Central DMA XAPP999 XAPP998 XAPP964 PPC405 PLB DDR2 with OPB Central DMA
2010 - PPC460GT-SUB1000T

Abstract: PPC460EX-SUB1000T PPC440EP-3JC533C PPC440EPX-NUA667T PPC460GT PPC440EPX-NUA400T embedded powerpc 460 PPC440GX-3RF533C PPC440GX-3NF667C PPC460
Text: Peripheral Bus ( OPB ) CPU MMU JTAG Trace 32K 32K D-Cache I-Cache with parity with parity 8KB SRAM DMA , parity with parity DMA Controller PowerPC 440 Core On-Chip Peripheral Bus ( OPB ) MAL UIC , Bridge IIC 100-133 MHz Processor Local Bus ( PLB ) 64-Bit On-Chip Peripheral Bus ( OPB , general purpose I/Os · DMA Controller with four independent channels High Speed and Inter-Chip , PCIe PCIe Int Handler DMA Controller 4 channels PLB4 OPB Bridge 100MHz Max. HSS x1


Original
PDF 405EP. 405EX. 405EXr. 405GPr. 440EP. 440EPx. 440GP. PPC460GT-SUB1000T PPC460EX-SUB1000T PPC440EP-3JC533C PPC440EPX-NUA667T PPC460GT PPC440EPX-NUA400T embedded powerpc 460 PPC440GX-3RF533C PPC440GX-3NF667C PPC460
2007 - ALi M1535D

Abstract: vhdl code for vending machine XC4VFX60 PLB DDR2 with OPB Central DMA XCF32PFSG48C PLB CONNECTOR m1535d manual ALi M1535D ALI usb PDC202
Text: diagram of the reference system. X-Ref Target - Figure 1 OPB INTC OPB UART 16550 OPB PLB PPC405 PLB CENTRAL DMA PLB BRAM PLB PCI PLB DDR X945_01_092107 Figure 1: ML410 PLB , PLB Central DMA plb_central_dma_0 0x50000000 0x5000007F PLB BRAM plb_bram_if_cntlr , licenses available and installed. A PLB PCI evaluation license is shipped with EDK. Xilinx ML410 , PCI Core MB BRAM BRAM X945_07_100107 Figure 7: Interfacing ML410 PLB PCI with ML555


Original
PDF ML410 XAPP945 PPC405) ML410 ALi M1535D vhdl code for vending machine XC4VFX60 PLB DDR2 with OPB Central DMA XCF32PFSG48C PLB CONNECTOR m1535d manual ALi M1535D ALI usb PDC202
2009 - powerpc 464

Abstract: PPC460SX ppc460 1G DDR2 128 x 8 circuit diagram for smartmedia adapter 460SX DDR800 IEEE1619 SHA-256 SHA-384
Text: on-chip SRAM · 32 KB on-chip SRAM · High-speed Processor Local Bus ( PLB ) with 2-way crossbar, supports , three PLB slave segments, supporting memory speeds up to DDR2 -800 · On-chip RAID 5 and RAID 6 , . The primary bus is a CoreConnect 128-bit processor local bus ( PLB ), with a two-way crossbar , generation and checking. This hardware, along with an internal high efficiency three-channel DMA engine , Cntl 3 Ch DMA RAID5/6 AES Assist (Bulk) DIF Hashing SDRAM 64-bit DDR2 -800 Master Arbiter


Original
PDF 460SX 460SX POWERPC460SX powerpc 464 PPC460SX ppc460 1G DDR2 128 x 8 circuit diagram for smartmedia adapter DDR800 IEEE1619 SHA-256 SHA-384
2007 - GCM-AES-128

Abstract: power pc 460ex PPC405EX-SSA667T 16750 UART DDR1 pcb layout powerpc 405 MACsec PPC405EX PPC405EX-NpAfffTx resistor AC03 philips
Text: engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include: · , faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA support , bus ( PLB ) operating up to 200MHz · On-chip 32-bit peripheral bus ( OPB ) operating up to 100 MHz · , Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . , On-chip Peripheral Bus ( OPB ) Arbiter 16KB D-Cache 16KB I-Cache OPB / PLB Bridges GPT PKA TRNG


Original
PDF 405EX 405EX 32-bit 333MHz 667MHz 128-bit 200MHz GCM-AES-128 power pc 460ex PPC405EX-SSA667T 16750 UART DDR1 pcb layout powerpc 405 MACsec PPC405EX PPC405EX-NpAfffTx resistor AC03 philips
2006 - PCI AHB DMA

Abstract: No abstract text available
Text: embedded marketplace has a In addition, with each Power Design Kit, DMA to PLB4 controller long , (PLB4) On-Chip Peripheral Bus ( OPB ) and I/O cores that interface with that used in Power , PLB4 GPIO to OPB controller core unpacking. The DMA is a master in The synthesizable PCIX to , the PLB . to PCI devices and PCI-X mode 1 I/Os with many different functions. devices. This , booting a PLB processor from PCIX The synthesizable EBC to OPB controller to 4 KB each, and supports


Original
PDF G224-7592-01 PCI AHB DMA
POWERPC405EX

Abstract: DTLs safenet PPC405 SHA-256 EIP-94
Text: PLB and OPB slave, and external bus. Development Tools Support PowerPC embedded processors are , well as an on-chip peripheral bus ( OPB ). High speed peripheral, such as PCI Express, DDR2 and the , · · · · · · · CPU: 533 MHz Maximum · PLB : 200 MHz Maximum · OPB : 100 MHz Maximum · , ) supports IPSec, SSL, DTLS and SRTP DMA Controller with four independent channels One 10/100/1000 Ethernet MAC with MAL DMA support 8/16/32-bit External Peripheral Bus Controller External Bus Master


Original
PDF 405EXr 533MHz 405EXr PPC405 POWERPC405EXr POWERPC405EX DTLs safenet SHA-256 EIP-94
EIP-94

Abstract: DTLs EIP94 POWERPC405EX AMCC ppc405 plb 405 powerpc 405 SHA-256 PPC405 405EX
Text: . Two UARTs (one with full hardware modem flow control), watchdog timer, and a 4channel DMA controller capable of transferring data to/from any PLB and OPB slave, and external bus. Development Tools , on-chip buses: a processor local bus ( PLB ) as well as an on-chip peripheral bus ( OPB ). High speed , . Frequency Features · 388-pin E-PBGA 27mm × 27mm ( with 1mm ball pitch) · CPU: 600 MHz Maximum · PLB , ) supports IPSec, SSL, DTLS and SRTP · DMA Controller with four independent channels · Two 10/100/1000


Original
PDF 405EX 400MHz 600MHz 8/16/32-bit 405EX PPC405 POWERPC405EX EIP-94 DTLs EIP94 AMCC ppc405 plb 405 powerpc 405 SHA-256
2007 - PPC405EXR

Abstract: POWERPC405EX EIP-94 AMCC ppc405 DTLs powerpc 405 SHA-256 PPC405EX 506 DMIPs PPC405
Text: -pin E-PBGA 27mm × 27mm ( with 1mm ball pitch) · CPU: 533 MHz Maximum · PLB : 200 MHz Maximum · OPB : 100 , transferring data to/from any PLB and OPB slave, and external bus. Development Tools Support PowerPC , well as an on-chip peripheral bus ( OPB ). High speed peripheral, such as PCI Express, DDR2 and the , IPSec, SSL, DTLS and SRTP · DMA Controller with four independent channels · One 10/100/1000 Ethernet MAC with MAL DMA support · 8/16/32-bit External Peripheral Bus Controller · External Bus Master


Original
PDF 405EXr 533MHz PPC405EXr PPC405 POWERPC405EXr POWERPC405EX EIP-94 AMCC ppc405 DTLs powerpc 405 SHA-256 PPC405EX 506 DMIPs
2008 - 405EX

Abstract: uart 16750 "ESP" PPC405EX-SSC600 epbg
Text: built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and , simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated Circuit (IIC , including 16KB I- and D-caches with parity checking · 128-bit processor local bus ( PLB ) operating up to , . . . . . . . . . . . . . . . 51 Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM . . , Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 15. DC Power


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz uart 16750 "ESP" PPC405EX-SSC600 epbg
2008 - PPC405EX-NSD600T

Abstract: EIP94 EPBGA PPC405EXR-NPD400T PPC405EXR PPC405EX-SSC600 PPC405EX-NSD400T
Text: communications link faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 15. Maximum DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 54 Table 17. DC Power Supply Loads with DDR2 SDRAM . . . . .


Original
PDF 405EXr 405EXr 32-bit 333MHz 533MHz 128-bit 200MHz PPC405EX-NSD600T EIP94 EPBGA PPC405EXR-NPD400T PPC405EXR PPC405EX-SSC600 PPC405EX-NSD400T
2008 - PPC405EX-SSC600T

Abstract: AMCC errata PPC405EX 405EX SPI NAND FLASH "ESP" PPC405EX-NSD600T AMCC PPC405EX
Text: built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and , simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated Circuit (IIC , including 16KB I- and D-caches with parity checking · 128-bit processor local bus ( PLB ) operating up to , . . . . . . . . . . . . . . . 51 Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM . . , Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 15. DC Power


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz PPC405EX-SSC600T AMCC errata PPC405EX SPI NAND FLASH "ESP" PPC405EX-NSD600T AMCC PPC405EX
2005 - XAPP809

Abstract: DS460 Gemac ml300 ucf
Text: PowerPCTM processor and PLB Gemac core, this system includes PLB DDR, PLB BRAM, OPB UARTLite with , software application is displayed in the HyperTerminal data screen. Running the OPB Central DMA Software , Local Bus ( PLB ) and On-Chip Peripheral Bus ( OPB ). The PLB 1-Gigabit Ethernet MAC solution (referred to , the address map of this system. OPB INTC OPB GPIO PLB DDR OPB PPC PROCESSOR PLB OPB , DMA . It is important to note that the when the PLB GEMAC core is configured to use the SerDes


Original
PDF XAPP809 DS460 XAPP809 DS460 Gemac ml300 ucf
2008 - PPC405EXR

Abstract: 11-G02 ppc405ex 16750 UART
Text: communications link faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 15. Maximum DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 54 Table 17. DC Power Supply Loads with DDR2 SDRAM . . . . .


Original
PDF 405EXr 405EXr 32-bit 333MHz 533MHz 128-bit 200MHz PPC405EXR 11-G02 ppc405ex 16750 UART
2008 - AMCC ppc405

Abstract: No abstract text available
Text: communications link faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , . . . . . . . . . . . . . . . . . . . . 52 Table 13. Typical DC Power Supply Requirements with DDR2 , 53 Table 15. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . , I-Cache OPB / PLB Bridges GPT PKA TRNG Arbiter Processor Local Bus (PLB4)-128 bits DDR1/2 SDRAM


Original
PDF 405EXr 405EXr 32-bit 333MHz 533MHz 128-bit 200MHz AMCC ppc405
2007 - PPC405EXR

Abstract: 405 t14 n03 macsec GCM-AES-128 EIP-94 AE09 0.9v bridge W04 epbga N25 replacement b20 p03
Text: attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include: · Federal , error simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , . . . . . . . . . . . . . . . . . . . . 52 Table 13. Typical DC Power Supply Requirements with DDR2 , 53 Table 15. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . .


Original
PDF 405EXr 405EXr 32-bit 333MHz 533MHz 128-bit 200MHz PPC405EXR 405 t14 n03 macsec GCM-AES-128 EIP-94 AE09 0.9v bridge W04 epbga N25 replacement b20 p03
2007 - power pc 460ex

Abstract: 405EX PPC405EX 460EX, lot resistor AC03 philips MACsec IBM PCI Express serdes architecture GCM modem M10 DDR1 pcb layout "ESP"
Text: function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers , , framing error simulation · OPB interface with optional DMA support IIC Bus Interface The , ( PLB ) operating up to 200MHz · On-chip 32-bit peripheral bus ( OPB ) operating up to 100 MHz · , . . . . . . . . . . 50 Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . , . DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz power pc 460ex PPC405EX 460EX, lot resistor AC03 philips MACsec IBM PCI Express serdes architecture GCM modem M10 DDR1 pcb layout "ESP"
2007 - SPI NAND FLASH

Abstract: PPC405EX
Text: cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include , error simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . , Arbiter On-chip Peripheral Bus ( OPB ) 16KB D-Cache 16KB I-Cache OPB / PLB Bridges GPT PKA/ TRNG


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz SPI NAND FLASH PPC405EX
2007 - SPI NAND FLASH

Abstract: PPC405EX
Text: cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include , error simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . , Arbiter On-chip Peripheral Bus ( OPB ) 16KB D-Cache 16KB I-Cache OPB / PLB Bridges GPT PKA/ TRNG


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz SPI NAND FLASH PPC405EX
2007 - DCR 804 SG 2121

Abstract: AMCC 405 DATE CODE MARKING PPC405EX Philips CDM3 104 esm SM 87719 philips CDM4 28548 marking PBEI 2322 157 11023 PHILIPS
Text: conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC , . 1.1.2.1 PLB , . 1.1.2.3 OPB , . 1.1.5 DMA Controller , . 1.1.7 DDR2 /1 SDRAM Controller


Original
PDF 405EX 405EX PPC405EX PPC405 DCR 804 SG 2121 AMCC 405 DATE CODE MARKING Philips CDM3 104 esm SM 87719 philips CDM4 28548 marking PBEI 2322 157 11023 PHILIPS
2007 - SPI NAND FLASH

Abstract: PPC405EX amcc 460EX EIP94 640KB
Text: cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include , error simulation · OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . , Arbiter On-chip Peripheral Bus ( OPB ) 16KB D-Cache 16KB I-Cache OPB / PLB Bridges GPT PKA/ TRNG


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz SPI NAND FLASH PPC405EX amcc 460EX EIP94 640KB
2008 - spi nand

Abstract: AMCC DTLs SPI NAND FLASH SHA-256 asic EIP94
Text: communications link faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA , - and D-caches with parity checking · On-chip 128-bit processor local bus ( PLB ) operating up to 200MHz · , Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . , Arbiter On-chip Peripheral Bus ( OPB ) 16KB D-Cache 16KB I-Cache OPB / PLB Bridges GPT PKA/ TRNG , the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the PLB


Original
PDF 405EX 405EX 32-bit 333MHz 600MHz 128-bit 200MHz spi nand AMCC DTLs SPI NAND FLASH SHA-256 asic EIP94
2008 - XPS Central DMA

Abstract: PLB DDR2 with PLB Central DMA MPLB LocalLink PLBV46 XAPP1121 PPC440MC UART16550 ML507 PPC440
Text: discussed. The XPS Central DMA master interface can be connected to the Processor Local Bus ( PLB ) v4.6 on either PLB Slave 0 (SPLB0) or PLB Slave 1 (SPLB1). Parameters for the XPS Central DMA are modified for , applications are included to demonstrate DMA transactions for XPS Central DMA and HDMA to DDR2 . In addition , XPS Central DMA instances are connected to the PLB v4.6 instance connected to the MPLB. In addition , Processor IBA XPS Central DMA plb_v46_1 Memory IF ILA XPS GPIO PPC440_MC PLB Mstr


Original
PDF XAPP1121 XPS Central DMA PLB DDR2 with PLB Central DMA MPLB LocalLink PLBV46 XAPP1121 PPC440MC UART16550 ML507 PPC440
Supplyframe Tracking Pixel