The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
UJ3D06508TS UJ3D06508TS ECAD Model UnitedSiC Rectifier Diode, Schottky, 1 Phase, 1 Element, 8A, 650V V(RRM), Silicon Carbide, TO-220AC
UJ3D06512TS UJ3D06512TS ECAD Model UnitedSiC Rectifier Diode, Schottky, 1 Phase, 1 Element, 12A, 650V V(RRM), Silicon Carbide, TO-220AC
UF3C065030K4S UF3C065030K4S ECAD Model UnitedSiC Power Field-Effect Transistor, 85A I(D), 650V, 0.035ohm, 1-Element, N-Channel, Silicon Carbide, Junction FET, TO-247
UJ3C065080T3S UJ3C065080T3S ECAD Model UnitedSiC Power Field-Effect Transistor
UJ3N120070K3S UJ3N120070K3S ECAD Model UnitedSiC Power Field-Effect Transistor, 33.5A I(D), 1200V, 0.09ohm, 1-Element, N-Channel, Silicon Carbide, Junction FET, TO-247
UF3C065080B7S UF3C065080B7S ECAD Model UnitedSiC 650V-80mΩ SiC FET D2PAK-7L

PIN DIAGRAM of ic 4028 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
IC 4028 D

Abstract: No abstract text available
Text: R IC R ATING S INPUT C U R R E N T OF 100 n A A T 18V A N D 25°C FOR HCC D EV IC E 100% TESTED , A R D No. 13A, "S T A N D A R D SP EC IFIC ATIO N S FOR DESCRIPTIO N OF " B " SERIES CMOS D E V IC , Plastic micropackage fo r HCF 4028 BM on , ¿9-57 FUNCTIONAL DIAGRAM CONNECTION DIAGRAM 3 , -5 5 to 125 -4 0 to 85 130 V V V °C °C HCC/HCF 4028 B LOGIC DIAGRAM AND TRUTH TABLE , capacitance D ynam ic power dissipation 131 HCyC/HCF 4028 B / ^< ^ > . STATIC


OCR Scan
PDF
PIN DIAGRAM of ic 4028

Abstract: functions of ic 4028 ws600 HVU316 VP15-00-3 ic 4028 4028 BE
Text: DESCRIPTION The µPC2734GR is a silicon monolithic IC designed for L band down-converter. This IC consists of , mark shows major revised points. © 1996, 2000 µPC2734GR INTERNAL BLOCK DIAGRAM AND PIN , Circuit 20 1 filter. 0.0 GND pin of mixer, IF amplifier, and regulator switch. OSC 3 MIX. 2.4 IN2 RF signal input pin . In case of single 4 3 input, 3 pin or 4 pin should , . ­­­­­­­ 7 8 VCC 5.0 Power supply pin of mixer, IF amplifier, and regulator switch. 9


Original
PDF PC2734GR PC2734GR 20-pin PIN DIAGRAM of ic 4028 functions of ic 4028 ws600 HVU316 VP15-00-3 ic 4028 4028 BE
4028

Abstract: 900 mhz oscillator RF mixer 433 Mhz PIN DIAGRAM of ic 4028
Text: BRO ADBAND FREQUENCY OPERATION RF = 0.9 - 2.1 GHz, LO = 1.1 - 2.5 GHz · · · · · HIGH DYNAM IC RANGE: P sat = +5 dBm Typical UPC2734GR INTERNAL BLOCK DIAGRAM MIX OUT LOW DISTORTION: IP3 = +11 , CONDITIONS Circuit Current (no signal) RF Frequency Range Conversion Gain fRF = 900 MHz, fiF = 402.8 MHz fRF = 900 MHz, flF = 479.5 MHz fRF = 2.1 GHz, fiF = 402.8 MHz fRF = 2.1 GHz, fiF = 479.5 MHz CG NF Noise Figure fRF = 900 MHz, fiF = 402.8 MHz fRF = 900 MHz, fiF = 479.5 MHz fRF = 2.1 GHz, fiF = 402.8


OCR Scan
PDF UPC2734GR SSOP20 UPC2734GR r734GR -C2734G UPC2734GR-E1 2500/Reel LHE75ES 4028 900 mhz oscillator RF mixer 433 Mhz PIN DIAGRAM of ic 4028
C10535E

Abstract: HVU316
Text: fluctuation of output impedance. Supply voltage : 5 V Packaged in 20- pin SSOP suitable for high-density , (5.72mm (225 mil) Embossed tape 12 mm wide. Pin 1 indicates pull-out direction of tape. Qty 2.5 kp , revised points. © 1996, 2000 µPC2734GR INTERNAL BLOCK DIAGRAM AND PIN CONFIGURATION (Top , IF band pass Equivalent Circuit 20 1 filter. GND 0.0 GND pin of mixer, IF , pin . In case of single input, 3 pin or 4 pin should be 4 MIX. 2.4 IN1 5 NC Non


Original
PDF
2002 - PIN DIAGRAM of ic 4028

Abstract: functions of ic 4028 KS0718 S6B0718 IC 4028 lcd cog dc-dc step-up
Text: written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move , light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip , control V0 voltage. HPMB I Power control pin of the power supplies circuit for LCD driver - HPMB , on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When , this document are subject to change without notice. No part of this document may be reproduced or


Original
PDF S6B0718 SEG103 SEG102 COM39 SEG102 SEG103 PIN DIAGRAM of ic 4028 functions of ic 4028 KS0718 S6B0718 IC 4028 lcd cog dc-dc step-up
4 bit gray code

Abstract: ITT nixie tube
Text: 5V, 10V, A N D 15V P A R A M E T R IC RA TIN G S INPUT C U R R E N T OF 100 nA A T 18V A N D 25°C FOR HCC D E V IC E 100% T E STE D FOR Q U IE SC EN T C U R R E N T M EET S A L L R E Q U IR E M E N T S OF , IPT IO N OF " B " S E R IE S CM O S D E V IC E S " The HCC 4028B (extended temperature range) and H , W P T » - - j m \ ' hcc /h c f 4028B _ 0 T - 4 > 7 'H ` £ / 1 I . . 4 ic 08711 , O PERATIO N : tPHL, tPL.H = 80 ns (TYP.) @ V DD= 10V S T A N D A R D IZ E D S Y M M E T R IC A L


OCR Scan
PDF 4028B D--07 4 bit gray code ITT nixie tube
PIN DIAGRAM of ic 4028

Abstract: 74hc4028 4028B 54HC 74HC M54HC4028 M74HC4028 d2539
Text: C 4028 PIN CONNECTIONS (top view) 'W Y2 Y0 High Speed t PD= 25 ns (Typ.) at V Cc = 5V Low , Cpo - pF (*) PF N ote (*) C po is defined as the va lue the IC ' s of internal equ iva , fabricated in silicon gate C 2MOS technology. It has the sam e high speed perform ance of LSTTL com bined , level at the selected one of the decim al decoded outputs. An illegal BCD code such as eleven to fifteen , discharge or transient excess voltage. FEATURES Y4 B1 P lastic Package F1 C eram ic P ackage Cl C


OCR Scan
PDF M54HC4028 M74HC4028 M54HC4028 M74HC4028 PIN DIAGRAM of ic 4028 74hc4028 4028B 54HC 74HC d2539
2000 - PIN DIAGRAM of ic 4028

Abstract: functions of ic 4028 configuration of decoder 4028 4028 BE KS0718 S6B0718
Text: mechanical, for any purpose, without the express written permission of LCD Driver IC Team. 104 SEG / 81 , resistive divider control V0 voltage. HPMB I Power control pin of the power supplies circuit for , clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal. I 9 , DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L" , VEV. The Ra and Rb are connected internally or externally by INTRS pin . And VEV called the voltage of


Original
PDF S6B0718 lhs98 S6B0718 85COM 100SEG SEG103 COM39 SEG102 PIN DIAGRAM of ic 4028 functions of ic 4028 configuration of decoder 4028 4028 BE KS0718
1999 - PIN DIAGRAM of ic 4028

Abstract: KS0718 configuration of decoder 4028 lcd cog
Text: , electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team , control V0 voltage. HPMB I Power control pin of the power supplies circuit for LCD driver - HPMB , : The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin , internally or externally by INTRS pin . And VEV called the voltage of electronic volume is determined by Eq , In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is


Original
PDF KS0718 KS0718 COM39 SEG102 SEG103 PIN DIAGRAM of ic 4028 configuration of decoder 4028 lcd cog
PIN DIAGRAM of ic 4028

Abstract: 4028 4028B 4028 BE 4029 truth table
Text: combination of inputs vmiit Dynamic power dissipation Xc Ii 1 16 2 15 3 u u 13 s 1? 6 ii 1 ic 8 9 -ggp 2V , PARAMETRIC RATINGS • INPUT CURRENT OF 100 nA AT 18V AND 25°C FOR HCC DEVICE • 100% TESTED FOR QUIESCENT CURRENT • MEETS ALL REQUIRËMENTS OF JEDËC TENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES" The HCC 4028B (extended temperature range) and HCF 4028B {intermediate , binary-to-octal decoders consisting of buffering on air4 inputs, decoding-logic gâtes, and 10 output buffers. A


OCR Scan
PDF 4028b PIN DIAGRAM of ic 4028 4028 4028 BE 4029 truth table
c2722

Abstract: No abstract text available
Text: ) PACKAG E STYLE Embossed tape 12 mm wide 2.5 k/REEL. Pin 1 indicates pull-out direction of tape. Embossed tape 12 mm wide 2.5 k/REEL. Pin 1 indicates roll-in direction of tape. Em bossed tape 8 mm wide 1 k/REEL. Pin 1 indicates pull-out direction of tape. For evaluation sample order, please contact your , DIAGRAM _ jjPC2721,uPC2722 PIN CONFIGURATION (Top View) EO 1. O SC base (bypass) 2 , pin for the IC . In ¿¿PC2721, IF am plifier is designed as single-end push-pull amplifier. ¿¿PC2721


OCR Scan
PDF uPC2721 uPC2722 iPC2721/2722 iPC2721 iPC2722: IR35-00-3 VP15-00-3 WS60-00-1 c2722
4028 BE

Abstract: 4028 4069B 4028BE ON 957 4028b 4028 cmos BCD to Decimal decoder nixie
Text: DIAGRAM FUNCTIONAL DIAGRAM 3-BIT BINARY INPUTS BUFFERED OCTAL DECODEO OUTPUTS < I OF 8 ) DECOOED , CURRENT OF 100 nA AT 18V AND 25°C FOR HCC DEVICE • 100% TESTED FOR QUIESCENT CURRENT • MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No 13A "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS , consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four inputs A to D results in a high level at the selected one of 10 decimal decoded outputs


OCR Scan
PDF 4028b 4028B 4028 BE 4028 4069B 4028BE ON 957 4028 cmos BCD to Decimal decoder nixie
GD4-01

Abstract: GD40175 GD40175B GD4017
Text: the LOW*to*HIGH Transition of the Clock Input (CP) if the Master Reset Input (MR) is HIGH. When LOW, the Master Reset Input (MR) resets all flip-flops (Oo*Q3 * LOW, Q0 -Q3 = H IGH ), independent of the Clock (CP) and Oata (Do*D3 ) Inputs. · · · · · T Y P IC A L CLO CK FR EQ U EN C Y OF 16 MHz A T V DD - , GOLDSTAR TECHNOLOGY 4028 75 7 G O L D S T A R T EC HN O L O G Y INC. INCn D4E D | 4D2fl7S7 0 1 , INPUT LOGIC SYM BOL V D D - P in 16 V s s - P in 8 PIN NAMES D0 -D3 21 MR Q0 Q 3 Qo *q 3


OCR Scan
PDF GD40175B 40175B T-46-07-09 GD4-01 GD40175 GD40175B GD4017
PC2721GV

Abstract: PC2722GV
Text: STYLE Embossed tape 12 mm w ide 2.5 k/REEL. Pin 1 indicates pull-out direction of tape. Embossed tape 12 mm w ide 2.5 k/REEL. Pin 1 indicates roll-in direction of tape. Embossed tape 8 mm wide 1 k/REEL. Pin , ) 5.0 4 5 Vcc IF output 5.0 /XPC2721 2.9 S upply voltage pin for the IC . In /xPC2721, IF am , I - ® 6 7 GND RF input 2 (bypass) 0.0 2.4 GND pin for the IC . 7 pin and 8 pin are , -4 9 NEC PACKAGE DIMENSIONS 8 PIN PLASTIC SSOP (175 mil) UPC2721. uPC2722 detail of lead


OCR Scan
PDF uPC2721 uPC2722 PC2721/2722 //PC2721 PC2722: PC2721GV PC2722GV
C2734G

Abstract: 4028 HVU316 SSOP20 UPC2734GR UPC2734GR-E1
Text: UPC2734GR S20 (SSOP20) Saturated Output Power ( PIN = 0 dBm) fRF = 900 MHz, fIF = 402.8 MHz fRF = 900 , Saturated Output Power ( PIN = 0 dBm) fRF = 900 MHz, fIF = 402.8 MHz fRF = 900 MHz, fIF = 479.5 MHz fRF = , PRELIMINARY DATA SHEET SILICON MMIC L-BAND DOWNCONVERTER UPC2734GR INTERNAL BLOCK DIAGRAM , CG Conversion Gain fRF = 900 MHz, fIF = 402.8 MHz fRF = 900 MHz, fIF = 479.5 MHz fRF = 2.1 GHz, fIF = 402.8 MHz fRF = 2.1 GHz, fIF = 479.5 MHz dB dB dB dB 10 9 7.5 7 NF Noise


Original
PDF UPC2734GR SSOP20 UPC2734GR UPC2734GR-E1 2500/Reel 24-Hour C2734G 4028 HVU316 UPC2734GR-E1
PIN DIAGRAM of ic 4028

Abstract: decodar mmc 4011 E IC 4028 8513N
Text:  MMC 40SB bcd-to-decimal decoder general description The MMC 4028 is a BCO-to-decimal or binary-to-octal decoder. This device is a mondflthic IC fabricated in standard Al-gate CMOS technology. MMC 4028 is available in 16-lead dual in line ceramic and plastic package. The MMC 4028 consists of buffering , inputs A to D, results in a high level at the selected one of ten decimal decoded outputs. High dnve , voltage values are referred to Vss pin voltage PECOMMENpED OPERATING CONDITIONS Vdo* Supply voltage: G


OCR Scan
PDF 16-lead PIN DIAGRAM of ic 4028 decodar mmc 4011 E IC 4028 8513N
C2721

Abstract: PC2721
Text: indicates pull-out direction of tape. µPC2721GR-E2 µPC2722GR-E2 8 pin Plastic SOP (225 mil) Embossed tape 12 mm wide 2.5 k/REEL. Pin 1 indicates roll-in direction of tape. µPC2721GV-E1 , points. © 1996, 1999 µPC2721, µPC2722 INTERNAL BLOCK DIAGRAM 8 7 6 PIN CONFIGURATION , inductance. 6 GND 0.0 RF input 2 (bypass) 2.4 5 GND pin for the IC . 7 µPC2722 , µPC2721, µPC2722 PACKAGE DIMENSIONS 8 PIN PLASTIC SOP (225 mil) (UNIT: mm) 8 5 detail of lead


Original
PDF
TTC-4028

Abstract: ic 4028 BT8921
Text: . Dielectric Strength; 1875Vrms 1 second @ Pri to Sec B. Marking; TTC- 4028 , TAMURA, date code and country of , Code White dot indicates Pin 1 Line Side 1 1350 SEC IC Side c 320 E. Mechanical Specifications , HDSL TRANSFORMER TTC- 4028 MODEL SPECIFICATION QUALITY CONTROL: D. Kelley CONTENTS OF THIS DRAWING ARE , /00 MP n PREPARED BY: J. Coleman HDSL transformer designed for use with Brooktree HDSL IC chips , ) Impedance; 1350 2. Secondary ( IC side) Impedance; 320 3. Frequency Response; ±0.1 dB @ 40KHz to 200KHz


OCR Scan
PDF BT8921 /BT8970 784kpbs 40KHz 200KHz, -70dB 40KHz, TTC-4028 ic 4028
1999 - c2721

Abstract: pc2721 UPC2721GV-E1 PIN DIAGRAM of ic 4028 PC2722 1SV210
Text: indicates pull-out direction of tape. µPC2721GR-E2 µPC2722GR-E2 8 pin Plastic SOP (225 mil) Embossed tape 12 mm wide 2.5 k/REEL. Pin 1 indicates roll-in direction of tape. µPC2721GV-E1 , points. © 1996, 1999 µPC2721, µPC2722 INTERNAL BLOCK DIAGRAM 8 7 6 PIN CONFIGURATION , inductance. 6 GND 0.0 RF input 2 (bypass) 2.4 5 GND pin for the IC . 7 µPC2722 , µPC2721, µPC2722 PACKAGE DIMENSIONS 8 PIN PLASTIC SOP (225 mil) (UNIT: mm) 8 5 detail of lead


Original
PDF PC2721, PC2722 PC2721/2722 PC2721: PC2722: c2721 pc2721 UPC2721GV-E1 PIN DIAGRAM of ic 4028 PC2722 1SV210
UT33

Abstract: Ut90 2066 4028 cmos
Text: Features HVCMOS* technology Operating output voltage of 90V Data clock speed 30MHz @ V00=5V Six , parallel data inputs, achieving an effective 180MHz data load rate. A direction pin (DIR) is provided to , controlled based on the latch contents, polarity (POL) pin and output enable (OE) pin inputs. All outputs may , Diagram 04/22/02 Supertex Inc. does not recommend the use of its products in life support applications and will not


OCR Scan
PDF 96-Channel 30MHz HV582 HV582 30MHz 180MHz 04/23/02rev UT33 Ut90 2066 4028 cmos
TIL3V

Abstract: No abstract text available
Text: ) NOTE: T h e S O Package has the sam e pin o u ts (C o n n e c tio n Diagram ) as tha D u al in-line , GOLDSTAR TECHNOLOGY INC-, G4E D | 4 Q S Ö 7 S 7 l ñ c IS M T-m -Z3-Q S D 4028 757 G O L , operation. The 4 7 2 0 B is specified to operate over a power supply voltage range of 4.5 to 12.5 V. T h e 4 7 2 0 B X is specified to operate over a power supply voltage range of 3 to 15 V. · · · · · · · · 3 , T R U E A N D C O M P LE M E N T O U TPU TS A V A IL A B L E F U L L Y S T A T IC LO W P O W E R D


OCR Scan
PDF GD4720B/GD4720BX 256-BIT P3-05 TIL3V
2002 - 2066

Abstract: HV582 din 2066
Text: operate as a data driver for AC plasma display panels. Operating output voltage of 90V Data clock , an effective 180MHz data load rate. A direction pin (DIR) is provided to control the data load , contents, polarity (POL) pin and output enable (OE) pin inputs. All outputs may be temporarily forced , . Functional Block Diagram 6 HVOUT1 RGB DIN 6 Shift Registers CLK 96-bit Latch Output , 09/16/02 Supertex Inc. does not recommend the use of its products in life support applications and


Original
PDF HV582 96-Channel HV582 30MHz 30MHz 180MHz HVOUT1-96 09/16/02rev 2066 din 2066
pin diagram of ic 4518B

Abstract: GD4518B 45188 GOLDSTAR gd451
Text: " H X L X CONNECTION DIAGRAM DIP (TOP VIEW) e 1/2 OF A 4518B LOGIC DIAGRAM © O R © 55 , Diagram ) at the Oual In-line Package. PIN NAMES CPOa, CPob C P la,C Fib © OR © V D O -P in 16 Vgg , 3 -0 5 ! 4028 75 7 G O L D S T A R T E C H N O L O G Y INC. 04E 01775 D ! GD4518B , Reset Input (MR). The counter advances on either tjie LOW-to-HIGH transition of the CPo Input if CPi is HIGH or the HIGH-to-LOW transition of the CPi Input if CPo Is LOW (see the Truth Table). Either Clock


OCR Scan
PDF GD4518B 4518B 0DD1777 pin diagram of ic 4518B GD4518B 45188 GOLDSTAR gd451
40098B

Abstract: GD40097B 40097B
Text: * 6X D " · · · 3-STATE OUTPUTS T T L C O M P A T IB L E -F A N O U T OF ONE T T L LOAD A C T IV E LOW EN ABLE INPUTS c c · c PIN NAMES 1 A -6 A EO4 , EO2 1 X -6 X ' C 4A 3 4X Buffer , 40098B) 1 0 « L NO TE: The SO Package has th e tam e p in o u ts (C o n n e c tio n Diagram ) as th e D ual In -lin e Package. 40097B LOGIC DIAGRAM 40098B LOGIC DIAGRAM © - , SS O - P in 8 Pin N u m b ir i GOLDSTAR TECHNOLOGY I N C t G4E D | 4G2fl7S7 D D G I T S S


OCR Scan
PDF 4GEA757 GD40097B GD40098B 40097B 40098B 40097B GD40097B
72741

Abstract: 2E15 MO-112
Text: _ SIZE DRAWING No. C I PSC- 4028 DO NOT SCALE DRAWING REV 05 I SHEET 1 OF 2 PACKAGE DIAGRAM OUTLINES , DIMENSIONS INCLUDING MOLD MISMATCH A DETAIL OF PIN 1 IDENTIFIER IS OPTIONAL BUT MUST BE LOCATED WITHIN THE , PACKAGE DIAGRAM OUTLINES PQFP (Continued) I» 1.20 (g>I C IA-BID<5H I» 1.20 <8>I H IA-B(5 , IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. A EXACT SHAPE OF EACH CORNER IS OPTIONAL A THESE DIMENSIONS APPLY TO THE FIAT


OCR Scan
PDF 010-338-2OUTLINE MO-112, 12/15/BB PSC-4028 72741 2E15 MO-112
Supplyframe Tracking Pixel