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PIN CONFIGURATION 7420 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2014 - Not Available

Abstract: No abstract text available
Text: Pin configuration s s s s s 3 1 6 7, 8, 9 2, 4, 5 TX Input RX Output Antenna To be , €™ prior express consent is prohibited. SAW Components B4414 SAW Duplexer 707.0 / 742.0 MHz , Duplexer 707.0 / 742.0 MHz Data sheet Characteristics Temperature range for specification: ANT , dB dB dB dB SAW Components B4414 SAW Duplexer 707.0 / 742.0 MHz Data sheet , . 756.0 max. — — MHz — fC typ. @ 25˚C 742.0 2.1 3.0 dB dB


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PDF B4414 B39741B4414P810
TTL 7421

Abstract: 7421 ttl AND gate 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 pin configuration 7420 SIGNETICS TTL 74LS20
Text: load (LSul) is 20/jA l,H and -0.4mA l|L. PIN CONFIGURATION '20, '21 LOGIC SYMBOL LOGIC SYMBOL (IEEE , Signetics I 7420 , 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ( 20) AND ('21) Gate Logic Products H Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns , Manufacturer 853-0546 81501 Signetics Logic Products Gates Product Specification 7420 , 7421, LS20, LS21 , Product Specification 7420 , 7421, LS20, LS21, S20 DC ELECTRICAL CHARACTERISTICS (Over recommended


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PDF 74LS20 74S20 74LS21 N7420N, N74LS20N, N74S20N N7421N, N74LS21N N74LS20D, N74S20D, TTL 7421 7421 ttl AND gate 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 pin configuration 7420 SIGNETICS TTL 74LS20
7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Text: PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) '2 0 , ' 21 1 2 S. 6 4 S & 9 10 12 , Signehcs I 7420 , 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ('20) AND ('21) Gate Product Specification Logic Products TYPE 7420 74LS20 74S20 7421 74LS21 TYPICAL PROPAGATION DELAY , S pecification Gates 7420 , 7421, LS20, LS21, S20 ABSOLUTE MAXIMUM RATINGS PARAMETER VCC , Signetics Logic Products P roduct S pecification Gates 7420 , 7421, LS20, LS21, S20 DC ELECTRICAL


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PDF 74LS20 74S20 74LS21 N7420N, N74LS20N, N74S20N N7421N, N74LS21N N74LS20D, N74S20D, 7421 pin configuration 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
ic 7421

Abstract: TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 function ic 7421 TTL 7420 7421 IC ic ttl 7421 pin configuration ic 7420
Text: Signetics I 7420 , 7421, LS20, LS21, S20 Gates H Dual Four-Input NAND ('20) AND ('21) Gate Product Specification Logic Products TYPE 7420 74LS20 74S20 7421 74LS21 TYPICAL PROPAGATION DELAY , ) is 50juA l|H and -2.0m A I|l, and 74LS unit load (LSul) is 2 0 iiA l|H and -0.4m A l|L. PIN CONFIGURATION LOGIC SYMBOL '2 0 , '2 1 LOGIC SYMBOL (IEEE/IEC) '2 0 , '2 1 1 2 2 -5 4 -Ç s -e ^ & 6 , 5 853-0546 81501 Signetics Logic Products Product Specification Gates 7420 , 7421


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PDF 74LS20 74S20 74LS21 N7420N, N74LS20N, N74S20N N7421N, N74LS21N N74LS20D, N74S20D, ic 7421 TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 function ic 7421 TTL 7420 7421 IC ic ttl 7421 pin configuration ic 7420
TTL 7421

Abstract: 7421 ttl AND gate TTL 7420 74LS21 PIN CONFIGURATION 7421 pin configuration 7420 pin configuration 74LS gates 7420 nand 74ls gate symbols PIN CONFIGURATION 7420
Text: , and 74LS unit load (LSul) is 20/jA l|H and -0.4mA l|L. 50jjA I|h and PIN CONFIGURATION LOGIC SYMBOL , Signetics I 7420 , 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ('20) AND ('21) Gate Logic Products ■Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7420 , Specification Gates 7420 , 7421, LS20, LS21, S20 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature , Product Specification Gates 7420 , 7421, LS20, LS21, S20 DC ELECTRICAL CHARACTERISTICS (Over recommended


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PDF 74LS20 74S20 74LS21 N7420N, N74LS20N, N74S20N N7421N, N74LS21 N74LS20D, N74S20D, TTL 7421 7421 ttl AND gate TTL 7420 74LS21 PIN CONFIGURATION 7421 pin configuration 7420 pin configuration 74LS gates 7420 nand 74ls gate symbols PIN CONFIGURATION 7420
pinout 7420

Abstract: No abstract text available
Text: as 256Kx32 or512Kx16. 68 pin "J" Leaded PLCC Power Consumption Pinout Configuration Memory , organised as 256K x 32 in a JEDEC 68 pin surface mount PLCC, available with access times of 15, 17, 20, or , dramatic space saving advantage over two standard 256Kx16 devices. The PUMA 68S8000X is an pin compatible , immunity. Single 5V±10% Power supply. Block Diagram BS3 BS2 CS2 bs T Pin Definition Ï? o £|S5|Si Is , 52 Ì A 0 -A 1 7 DO - D31 C S 1 -2 BSO-3 WE OE NC Chip Select Byte Select Write Enable Pin


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PDF PUMA68S8000X 68S8000X 256Kx16 68S2000X. 68S8000X-15/17/20/25 68S8000XLI-15 S8000 256Kx32 or512Kx16. pinout 7420
2005 - IC 7400 SERIES list

Abstract: IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 ACML-7410 pin diagram ic 7420 IC 7410
Text: -7400 ACML-7410 ACML- 7420 Channel Configuration Quad, All-in-One Quad, Bi-directional, 3/1 Quad , ACML-7400, ACML-7410 and ACML- 7420 3.3 V/5 V 100 MBd High Speed CMOS Digital Isolator Data , lead-free product Description ACML-7400, ACML-7410 and ACML- 7420 are multi-channel high speed CMOS , distortion of 3 ns. They are capable of running at a 100 MBaud data rate ACML-7400, ACML-7410 and ACML- 7420 are available in 16- pin SOIC wide-body packages. They operate at dual 3.3 V/5 V supply voltages. The


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PDF ACML-7400, ACML-7410 ACML-7420 ACML-7420 ACML-7400 AV02-2675EN IC 7400 SERIES list IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 pin diagram ic 7420 IC 7410
pin configuration ic 7420

Abstract: PUMAS 7420 ic details pinout 7420 pin diagram ic 7420 4007A
Text: Block Diagram of A version) Pin Definition (see page 11 for A version Pinout) O o i - w to Tt Z , O U O O O Q O *! < < < < < <|i3lolo z z z z z § z Pin Functions A0~16 Address Inputs CS1 , -15/17/20/25 DC OPERATING CONDITIONS Voltageonany pin relative to GND StorageTemperature , sampled and not 100% tested. Mosaic Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Dtego, CA 92121 , =5V±10% Output Test Load I/O Pin 645ÎÎ I -15 max - - \W - o 1.76 V 100pF AC OPERATING


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PDF PUMA67E4007/A 16or32 250ns. 100years. MIL-STD-883. 128Kx PUMA67E4007/9 7E4007-15/17/20/25 Junel996 67E4007AMB-15 pin configuration ic 7420 PUMAS 7420 ic details pinout 7420 pin diagram ic 7420 4007A
7420 pin configuration

Abstract: No abstract text available
Text: organised as 32K x 32. This is available in a 66 pin PGA package which is suitable for thermal ladder , -883. Block Diagram Pin Definition A0-AU · O E W Ë4 · W E3 W E2 . W E 1 . 32K x 8 EEPROM C S 1 CS2 C , EEPROM Pin Functions AO-14 CS1-4 WE1-4 Vcc Address Inputs Chip Select Write Enable Power (+5V) DO , * VC C =5V±10% Output Test Load 645o I/O Pin o- · -vW'- o I 1.76V - 100pF Mosaic Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 Tel: 619.271.4565 Fax: 619.271.6058


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PDF PUMA2E1000/X405 120ns. MIL-STD-883. 2E1000-70/90/12/X405 2E1000LMB-70/X405 MIL-STD-883 E1000 32Kx32, 64Kx16 128Kx8) 7420 pin configuration
2003 - pin diagram ic 7420

Abstract: S-8521F48mc-bqh-t2 toyota IC regulator built TM6201
Text: SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR S-8520/8521 Series Pin Configuration SOT-23-5 Top view 5 4 Rev. 7.4_20 Table 3 Pin No. 1 Pin name ON / OFF Pin description Shutdown pin "H": Normal , Rev. 7.4_20 PWM CONTROL, PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS S , -8520/8521 Series Applications Rev. 7.4_20 · On-board power supplies of battery devices for portable , -23-5 Package MP005-A Drawing code Tape MP005-A Reel MP005-A 2 Seiko Instruments Inc. Rev. 7.4_20


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PDF S-8520/8521 S-8520 S-8521 pin diagram ic 7420 S-8521F48mc-bqh-t2 toyota IC regulator built TM6201
KV1870R

Abstract: KV1870RTL KV1870S KV1870STL
Text: 70.74 74.20 PACKAGE OUTLINE Part name KV1870R KV1870S Package SOT23C-3 SOT23-3 ORDERING INFORMATION Marking Pin configuration Ordering information C7 KV1870RTL.Storage direction: TL(Left , 65.80 70.00 74.20 pF VR=1V, f=1MHz Diode Capacitance 12.00 13.40 14.80 pF VR=4.5V, f=1MHz C4


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PDF KV1870R/S KV1870R KV1870S OT23C-3 OT23-3 KV1870RTL. KV1870STL. 100MHz KV1870R KV1870RTL KV1870S KV1870STL
LM 7420

Abstract: No abstract text available
Text: Pin Definitions A18 A16 Ä15 A12 A7 A6 A5 A4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c d cz I z cz cz cz , 10 A1 11 A0 12 DO 13 25 A11 24 O E 2 3 A10 22 21 CS 07 Package Details Pin Count Description 32 32 32 Dual In-line JLCC Ceramic Flatpack Pin Functions Package Type S J G A0-A18 D0-D7 CE WE OE , DC OPERATING CONDITIONS Absolute Maximum Ratingsi1 ) unit Voltage on any pin w.r.t. Gnd Supply , voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V During


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PDF MFM8516 b3S337T 002Lic MFM8516GMB-80E MIL-STD-883 512Kx b35337T LM 7420
2010 - 7404 7408 7432

Abstract: c 2818 7446 ADF4106 7432 pin layout C 2923
Text: Pin Configuration Pin Number Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC , 740.8 742.0 743.2 744.4 744.6 POWER OUTPUT VCO CURRENT PLL CURENT (dBm) (mA) (mA , -28.17 -28.17 -28.20 -28.26 -28.34 -28.35 FREQUENCY (MHz) 739.4 739.6 740.8 742.0 743.2 744.4 744.6 FREQUENCY (MHz) 739.4 739.6 740.8 742.0 743.2 744.4 744.6 F2 +25°C -29.23 , -89.58 -90.92 -90.43 -91.19 -89.80 -90.95 -89.81 739.4 739.6 740.8 742.0 743.2 744.4 744.6


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PDF KSN-745A-119+ DK1042 7404 7408 7432 c 2818 7446 ADF4106 7432 pin layout C 2923
KV1770STL

Abstract: KV1770S KV1770R KV1770RTL marking C45
Text: 70.74 74.20 PACKAGE OUTLINE Part name KV1770R KV1770S Package SOT23C-3 SOT23-3 ORDERING INFORMATION Marking Pin configuration Ordering information C7 KV1770RTL.Storage direction: TL(Left , 65.80 70.00 74.20 pF VR=1V, f=1MHz Diode Capacitance 12.00 13.40 14.80 pF VR=1V, f=1MHz C4


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PDF KV1770R/S KV1770R KV1770S OT23C-3 OT23-3 KV1770RTL. KV1770STL. 100MHz KV1770STL KV1770S KV1770R KV1770RTL marking C45
2003 - toyota IC regulator built

Abstract: pin diagram ic 7420
Text: , PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS Rev. 7.4_20 S-8520/8521 Series Pin Configuration SOT-23-5 Top view 5 4 Table 3 Pin No. 1 Pin name ON / OFF Pin description Shutdown pin "H" , SWITCHING REGULATOR CONTROLLERS Rev. 7.4_20 S-8520/8521 Series 3. EXT pin output current "H" (IEXTH)-Input , Rev. 7.4_20 PWM CONTROL, PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS S , CONTROLLERS Rev. 7.4_20 S-8520/8521 Series Applications · · · · · · On-board power supplies of battery devices


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PDF S-8520/8521 S-8520 S-8521 toyota IC regulator built pin diagram ic 7420
PCX-7420

Abstract: db37 connector 20/7420
Text: PCX- 7420 Data Sheet PCX- 7420 Features: · Output Current up to 21.5 A · Output Voltage up to 24 V , The PCX- 7420 is an air-cooled, high power CW/QCW current source designed to drive diode lasers, bars , when externally triggered. The PCX- 7420 offers the capability of providing both QCW (pulsed), and CW , be pulsed and triggered independent of the Main current trigger. The PCX- 7420 may be operated through , interlocked, so that the PCX- 7420 is disabled when the connector is removed. The PCX- 7420 features advanced


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PDF PCX-7420 PCX-7420 RS-232, db37 connector 20/7420
2005 - KV1770STL-G

Abstract: No abstract text available
Text: 74.20 PACKAGE OUTLINE Part name KV1770R-G KV1770S-G Package SOT23C-3 SOT23-3 Marking Pin configuration C7· C7· ORDERING INFORMATION Ordering information KV1770RTL-G.Storage direction: TL(Left , VR=10V C1 65.80 70.00 74.20 pF VR=1V, f=1MHz Diode Capacitance 12.00 13.40 14.80 pF VR=4.5V, f


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PDF KV1770RTL-G, KV1770STL-G KV1770R-G KV1770S-G OT23C-3 OT23-3 KV1770RTL-G. KV1770STL-G. 50MHz 70MHz KV1770STL-G
7420 pin nc

Abstract: No abstract text available
Text: Applications. 5.0 V +/-10% read, writeand erase minimising system level powerrequirements. Hardware RESET pin - resets internal state machine to the read mode. Pin Functions A0~A23 Address Inputs \ s. D0~D31 Data , Pin C51 OE1 WEI RY/BY1 CS2ÖE2 WE2RY/BY2 CS3OE3 WE3RY/BY3 CS4OE4 WE4 . RY/BY4 . D0-D7. D8-D15 . D16-D23. D24-D31. Note: RY/BYsignal requires externall pull-up resisitor{PrototypeOnly} ^ Pin Definition , > Voltage on any pin w.r.t. Gnd (except A9) Supply Voltage(2 ) Voltage on A9 w.r.t. G n d (3 ) Storage


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PDF 150and 170ns. A0-A20 A21-A23M F516M-12/15/17 F516MMB-12 MIL-STD-883. 512Mbit, 7420 pin nc
Not Available

Abstract: No abstract text available
Text: , inc. Description ThePUMA67E1001/AisalMbitCMOS EEPROM module in a JEDEC 68 pin J leaded Ceramic , with MIL-STD-883 Block Diagram Pin Definition (see page 12 for Block Diagram of option /A ) (seepage 12 for Pin Definition of option/A) n A 0-A 14 9 8 7 n 6 n 5 n 4 n 3 , 32 33 34 35 36 37 38 39 40 41 42 43 U U U U U U T ] ' L 1 U U U U U U L J >< <<< Pin , Condition ^INl ^IN2 VIN -0V Cqut v OT U =ov v,N =ov Mosaic Semiconductor, Inc., 7420


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PDF PUMA67E1001/A-90/12 ThePUMA67E1001/AisalMbitCMOS of90and MIL-STD-883orD0 MIL-STD-883 32Kx32 as64Kx 16and 128Kx8 PUMA67
pin diagram ic 7420

Abstract: pin diagram of ic 7420 IC 7420 7420 TTL diagram 7420 ic TTL 7420 cmos 7420 pinout 7420
Text: =5V±10% Output Load i/o Pin ° 166n ? vW * O 1-76V Mosaic Semiconductor, Inc., 7420 Carroll Rd , processed in accordance with MIL-STD-883. Pin Definition W AO A1 A2 A3 A4 1 C 2 c 3 c 4 c 5 CS , A14 23 A13 22 A12 21 A11 20 D A10 19 NC c c 17 c 18 Pin Functions A0-A18 D0-7 CS OE WE NC Vcc , any pin relative to Vss Power Dissipation Storage Temperature vT PT " ^ " s T G -0.5V to +7 1 -55 , Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 b35337c ì GG2712 71D z > 10


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PDF MSM8512J MSM8128 MIL-STD-883. MSM8512J-015/020/025 JEDEC1014 8512J B-015 0D0271Ö pin diagram ic 7420 pin diagram of ic 7420 IC 7420 7420 TTL diagram 7420 ic TTL 7420 cmos 7420 pinout 7420
pin diagram ic 7420

Abstract: 7420 ic
Text: Module in a 6 8 pin JLCC package, with access times of 90,120 and 150 ns. The oyput width is configurable , be screened in accordance with MIL-STD-883. / ; Pin Definition n /^ 9 DO e 10 D 1 c 11 D 2 C 12 D 3 , I L L ) |CM h» C O Q Q Ü > < < < < < < o fo < < u u Ûo z z o Pin Functions A0-A18 CE1-4 OE GND , i Voltage on any pin w.r.t. Gnd Supply Voltage(2 ) Voltage on A9 w.r.t. G nd (3 ) StorageTemperature , this specification is not implied. Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC


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PDF PUMA67F16006 67F16006 b3S337c F16006MB-90 MIL-STD-883 512Kx 1Mx16and pin diagram ic 7420 7420 ic
Not Available

Abstract: No abstract text available
Text: August 1995 Description The PUMA. 3F16006 is a 16 Megabit CMOS 5.0V only FLASH Module in a 6 6 pin , .) r. Defimticn Pin Block Diagram o 08 © © W2 Ë © © © © © © ©  , © D1B D19 Pin Functions A0-Al8 CE1-4 OE GND Address Input Chip Enables Output Enable , +14 V -65 to +150 °C Voltage cn any pin w.r.t. Ghd Supply Voltage ® Voltage cnA9 w.r.t. Gnd c , . Mininum DC voltage on any input or I/O pin is -0.5V. Maxinum DC voltage on output and I/O pins is Vcc


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PDF 3FI6006-90/12/15 3F16006 3F16006I-90 512Kx32,
Not Available

Abstract: No abstract text available
Text: .), Sector Program time of 1 sec. (typ.). Erase/Write Cycle Endurance 100,000 (min.) Pin Definitions , A8 A9 A11 OE A10 CS D7 D6 D5 = l 18 D4 = > 17 D3 Pin Functions A0-A18 , °C Voltage on any pin w.r.t. Gnd Supply Voltage® Voltage on A9 w.r.t. G n d (3 , voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V During , PF Note: These parameters are calculated, not measured. Mosaic S em iconductor, Inc., 7420


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PDF MFM8T516-90/12/15 MFM8T516 0002b42 MFM8T516SMB-90 MIL-STD-883. 8T516 512Kx b3S3371 00D2b43
ci 7420

Abstract: No abstract text available
Text: a n d 5 1 2 K x 8 F = FLASH PUMA 2 = 66 pin Ceramic PGA Mosaic Semiconductor, Inc., 7420 , in a 66 pin ceramic PGA pack age, which is configerable as 8 , 1 6 , 3 2 bit wide output using Chip , wide. · Operating Power 3 80/693/1320 mW(max.) Low powerstandby6.6m W (m ax.) · JEDEC 66 pin PGA · , · Can be screened in accordance with MIL-STD-883. Block Diagram Pin Definition O D8 ©. , © © © © © © NC 05 03 © © © D17 GNO 021 J Pin Functions A0-A16 CS1-4 OE VC c Address Inputs Chip


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PDF PUMA2F4001 150ns, 170nsand 200nsareavailable 128Kx PUMA2F4001-15/17/20 b3S337c 00D24bl PUMA2F4001MB-15 ci 7420
Not Available

Abstract: No abstract text available
Text: footprint. Pin Definitions Block Diagram X. idr B u lle r □□ □r □ Column t/O | , €¢> _ _ < N -» O 5 12 ID J,W PACKAGE TOP VIEW DO 13 Package Details Pin Count , ) W 32 J-Leaded Chip Carrier (JLCC) J Pin Functions A0-A14 DO-7 CS OE WE Vcc GND , Absolute Maximum Ratings <> 1 Voltage on any pin relative to Vss(2 > VT Power Dissipation PT , % tested. Mosaic Sem iconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 2 ■I


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PDF MSM832-55/70/85/10 MSM832 MIL-STD-883. MSM832SLMB-70 MIL-STD-883
Supplyframe Tracking Pixel