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PIC32MX420F032HT-40I/MR Microchip Technology Inc 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQCC64, 9 X 9 MM, 0.90 MM HEIGHT, LEAD FREE, PLASTIC, QFN-64
PIC32MX420F032HT-40V/PT Microchip Technology Inc IC MCU 32BIT 32KB FLASH 64TQFP
PIC32MX420F032HT-40V/MR Microchip Technology Inc IC MCU 32BIT 32KB FLASH 64QFN
PIC32MX420F032HT-40I/PT Microchip Technology Inc 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-64
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PIC32MX420F032HT-40I/MR MCU 32-bit PIC32 PIC RISC 32KB Flash 2.5V/3.3V 64-Pin QFN EP T/R - Tape and Reel (Alt: PIC32MX420F032HT-40I/MR) PIC32MX420F032HT-40I/MR ECAD Model
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PIC32MX420F032HT-40I/MR datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
PIC32MX420F032HT-40I/MR PIC32MX420F032HT-40I/MR ECAD Model Microchip Technology Embedded - Microcontrollers, Integrated Circuits (ICs), IC MCU 32BIT 32KB FLASH 64QFN Original PDF

PIC32MX420F032HT-40I/MR Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2013 - Not Available

Abstract: No abstract text available
Text: MR Manual Reset Input Pin: active-low 3 GND 4 VDD Ground Pin Input Pin The tab , tab can be left open. RP300N: SOT-23-5 Pin No. Symbol 1 MR 2 GND 3 NC , Output Voltage (CMOS Output) -0.3 to VDD +0.3 -0.3 to VDD +0.3 V 20 mA MR Manual , = 5.5V ILEAK Nch Driver Leakage Current RMR MR Pin Pull-up Resistance VIH MR Pin Input Voltage “H” VDD ≥ -VSET +0.1V VIL MR Pin Input Voltage “L” 0.15 VDD â


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PDF RP300x EA-306-130326 RP300xxxxA/C RP300xxxxB Room403, Room109, 10F-1,
2014 - RICOH Cross Reference

Abstract: R3134N
Text: (R3134xxxEA) CMOS Output (R3134xxxEC) MR VDD Delay Circuit VDD MR DOUT Delay Circuit , Pin 3 GND 4 MR Manual Reset Input Pin* 5 NC No Connection Ground Pin * MR pin is active at "L" input. Pulled up via 1MΩ (Typ.). If MR pin is not necessary, open this node , guaranteed by design engineering at  40ï ‚°C  Ta  85C. (Ta25C) R3134x Symbol Item , 6.00  40ï ‚°C  Ta  85C 0.85 6.00 VDD Operating Voltage VOH "H" Output


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PDF R3134N EC-209-140227 R3134x Room403, Room109, 10F-1, RICOH Cross Reference
2014 - Not Available

Abstract: No abstract text available
Text: PT7M6314USxxD3F/D4F 1 2 GND VCC 4 MR 3 RST SOT143-4 Pin Description Name Type , condition release. RST I/O MR I Manual Reset: A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset timeout period (tRS) after the reset conditions are , to +150C Ambient Temperature with Power Applied . - 40ï ‚°C to +85C , ICC (VTH-) 0.985 (VTH-) 0.975 +25C Voltage Threshold VTH- 40ï ‚°C~85ï


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PDF PT7M6314US 100mV M6314US50D3 PT7M6314US50D4 PT0178-4
Not Available

Abstract: No abstract text available
Text: PT7M6314USxxD3F/D4F 1 2 GND VCC 4 MR 3 RST SOT143-4 Pin Description Name Type , condition release. RST I/O MR I Manual Reset: A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset timeout period (tRS) after the reset conditions are , to +150C Ambient Temperature with Power Applied . - 40ï ‚°C to +85C , -) 0.985 (VTH-) 0.975 +25C Voltage Threshold VTH- 40ï ‚°C~85C Hysteresis VHYS


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PDF PT7M6314US 100mV T7M6314US50D3 PT7M6314US50D4 PT0178-3
8931E-040-178LF

Abstract: 8925R-040-179F c10900D 8931E-040 8931E-040-178L 1248 8931E-040-178 8931E-040-178L-F
Text: ) : 6000 LSB/ mR : 12 × 12 cm (1248 × 1248 ) 13 (Fast mode, Partial mode) () (Fast mode , frames/s electrons M electrons LSB/ mR line pairs/mm - Sf(int) N(rms) Csat S Reso - , electrons LSB/ mR line pairs/mm - Sf(int) N(rms) Csat S Reso - Min. 16.1 2800 3.6 - Typ. 17 1300 2.3 3500 4.5 1700 Max. - frames/s electrons M electrons LSB/ mR line , 2.3 3500 4.5 1700 Max. - frames/s electrons M electrons LSB/ mR line pairs/mm -


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PDF C10900D C10900D2 KACCC0487JA KACCC0385JB KACCC0384JB KACCC0407JA 8931E-040-178LF 8925R-040-179F c10900D 8931E-040 8931E-040-178L 1248 8931E-040-178 8931E-040-178L-F
2013 - Not Available

Abstract: No abstract text available
Text: below its threshold (VIT) or the voltage of manual reset ( MR ) is pulled to a logic low, the RESET , voltage and MR exceed their thresholds, RESET is driven to a logic high after a user-programmable delay , Generator with Adjustable Delay Time: 2.1ms to 10s High Threshold Accuracy: ±1% Typ Manual Reset ( MR , ) - 40ï ‚°C to +125C MPQ6400DG-33-AEC1 QFN6 (2x2mm) - 40ï ‚°C to +125C *For Tape & Reel, add , VCC = 3.3V, RESET not asserted. MR , RESET , CDELAY open 1.6 5 µA VCC = 5.5V, RESET not


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PDF MPQ6400 AEC-Q100 MPQ6400 MPQ6400DG01 MO-229,
2012 - Not Available

Abstract: No abstract text available
Text: Ambient temperature range – 40ï ‚°C to +85C 52-lead LQFP packaging, Pb-free Supports clock , supply and an ambient temperature range of – 40ï ‚°C to +85C. The MPC9449 is pin and function , QD3 DSELD QD4 QD5 MR /OE NC GND QC0 VCC QC1 GND QC2 VCC QC3 GND GND QD5 NC Figure , QD4 GND QD3 VCC QD2 GND QD1 VCC QD0 GND NC MR /OE CCLK_SEL VCC CCLK0 CCLK1 PCLK PCLK , ‚¸1 2 MR /OE 1 Outputs enabled Outputs disabled (high impedance) Table 2. Pin


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PDF MPC9449 MPC9449
2012 - Not Available

Abstract: No abstract text available
Text: Ambient temperature range – 40ï ‚°C to +85C 52-lead LQFP packaging, Pb-free Supports clock , supply and an ambient temperature range of – 40ï ‚°C to +85C. The MPC9449 is pin and function , QD3 DSELD QD4 QD5 MR /OE NC GND QC0 VCC QC1 GND QC2 VCC QC3 GND GND QD5 NC , QD4 GND QD3 VCC QD2 GND QD1 VCC QD0 GND NC MR /OE CCLK_SEL VCC CCLK0 CCLK1 PCLK PCLK , ‚¸1 2 MR /OE 1 Outputs enabled Outputs disabled (high impedance) Table 2. Pin


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PDF MPC9449 MPC9449
2014 - Not Available

Abstract: No abstract text available
Text: in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR /nOE, resets the , QA0 CLK0 Pullup GND MR /nOE CLK_SEL Pulldown 3 32 31 30 29 28 27 26 25 QA[0:2 , MR /nOE Pulldown ICS87946AYI-147 REVISION A APRIL 30, 2014 19 7 GND 0 20 6 , clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 32 MR /nOE Type , Function Table Inputs Outputs MR /nOE DIV_SELA DIV_SELB DIV_SELC QA0:QA2 QB0:QB2


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PDF ICS87946I-147 ICS87946I-147 250MHz
2009 - Not Available

Abstract: No abstract text available
Text: »•æ§˜(*2) MR MR-G 詳細内容 H アクティブ、プルダウン内蔵(セミカスタムï , ) 出力電圧 Time ( 40Î ¼s/div) Time ( 40Î ¼s/div) XA6219x182 XA6219x252 tr=tf=5μs、Ta=25℃ CL , =5μs、Ta=25℃ CL=1μF (ceramic)、IOUT=1mA 出力電圧 Time ( 40Î ¼s/div) Time ( 40Î ¼s/div) XA6219x252 XA6219x252 入力電圧 出力電圧 Time ( 40Î ¼s/div) 14/21 Time ( 40Î ¼s/div) Output Voltage , =1μF (ceramic)、IOUT=10mA tr=tf=5μs、Ta=25℃ CL=1μF (ceramic)、IOUT=1mA Time ( 40Î ¼s/div) Time


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PDF XA6219 JTR0350-001
Not Available

Abstract: No abstract text available
Text: VCC 4 MR 3 RST SOT143-4 Pin Description Name Type RST I/O Description Reset Output: RST is asserted when VCC drops below voltage threshold VTH-. Active low. MR I Manual Reset: A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset , | | Block Diagram Vcc MR VCC Resistor Divider Timing Delay RST T.C. Reference GND Function , drops below 1V. Manual Reset The manual-reset input ( MR ) allows reset to be triggered by a


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PDF PT7M6315US 100mV S29D2 PT7M6315US30D2 PT0197-3
Not Available

Abstract: No abstract text available
Text: of an external resistor connected between SSEXTR and GND. Modulation Rate ( MR ) control selects one , VDD 7 SSEXTR SSON 3 6 MR GND 4 5 ModOUT XOUT 2 PCS3P8504A ORDERING , this data sheet. Publication Order Number: PCS3P8504A/D PCS3P8504A SSON MR VDD XIN , Ground 5 ModOUT O Modulated clock output 6 MR I Modulation Rate Select. When LOW , temperature - 40ï ‚°C to +85C Load capacitance (CP) 18 pF Shunt capacitance 7 pF maximum


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PDF PCS3P8504A PCS3P8504A PCS3P8504A/D
2015 - Not Available

Abstract: No abstract text available
Text: ‘£ 出力電圧精度 A B ⑤⑥-⑦ (*4) パッケージ (発注単位) MR MR-G PR PR-G DR DR-G , œ§ 出力電圧 出力電圧 Time ( 40Î ¼sec/div) 時間 Time ( 40Î ¼sec/div) XC6209B/F122 XC6209B/F122 IOUT=100mA, tr=5μsec, CL=1μF (セラミック) 出力電圧 時間 Time ( 40Î ¼sec/div , ½¸) 入力電圧 Time ( 40Î ¼sec/div) 時間 Time ( 40Î ¼sec/div) 出力電圧 出力電å , (V) XC6209B/F302 Time ( 40Î ¼sec/div) 19/30 XC6209 シリーズ ■特性例 (9


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PDF XC6209 JTR0306-009
2009 - 5252 F 1120

Abstract: No abstract text available
Text: D/H 09 ~ 60 2 1 ④ 出力電圧精度 A B MR MR-G ⑤⑥-⑦ パッケージ形ç , ( 40Î ¼sec/div) 時間 16/25 Time ( 40Î ¼sec/div) VIN (V) 入力電圧 VOUT (V) 出力電圧 VIN (V) 入力電圧 時間 入力電圧 出力電圧 時間 Time ( 40Î ¼sec/div , =1μF (セラミック) 出力電圧 Time ( 40Î ¼sec/div) XC6209/12 B/F122 XC6209/12 B/F122 入力電å , =5μsec, CL=1μF (セラミック) VOUT (V) VIN (V) 入力電圧 Time ( 40Î ¼sec/div) XC6209/12 B


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PDF XC6209/XC6212 JTR0306-005 XC6209/12 5252 F 1120
2013 - Wirewound

Abstract: No abstract text available
Text: Insulation 250V 400V Resistance Range 0.08Ω - 15Ω 0.1Ω - 40Î © Operating Temp. Range , 40Î © Operating Temp. Range 0.18Ω - 220Ω - 40°C to +200°C Temperature Coefficient , J = ±350 ppm/°C M R = MR Type 200 2W = AV = AVIsert 2WS 2WS = PN =


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PDF 300ppm/Â UL-94V-0 UL-1412 SQP500JB-10R JPW-06-T-52- Wirewound
2013 - Not Available

Abstract: No abstract text available
Text: ステップ) MR SOT-26W (3,000/Reel) MR-G SOT-26W (3,000/Reel) DR USP-6B (3,000/Reel , XC6401 (0.8V 品) Time ( 40Î ¼s/div) XC6401 (2.85V 品) tr=tf=5μs CL=1μF(セラミック) IOUT , 入力電圧 2.95 2.75 Time ( 40Î ¼s/div) 入力電圧 2 入力電圧 出力電圧 0.90 , œ§ 出力電圧 2.80 2.75 4 1 0 時間 Time ( 40Î ¼s/div) 入力電圧 2.95 2.95 2.90 , œ§ 4 0.95 VOUT (V) 1.00 1 0 時間 Time ( 40Î ¼s/div) 15/24 XC6401 シリーズ


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PDF XC6401 JTR0309-007 XC6401ã
2014 - Not Available

Abstract: No abstract text available
Text: VDD QA4 QA3 GND QA2 QA1 VDD QA0 MR /nOE GND IDT8V40817 20 LEAD QSOP 0.194” x 0.236” x , QREF2 MR /nOE MR /OE IDT8V40817QG REVISION A JANUARY 14, 2014 2 ©2014 Integrated Device , GND Power Power supply ground. 12 MR /nOE Input 13, 15, 16, 18, 19 QA0, QA1, QA2 , Capacitance (per output) RPULLUP RPULLDOWN Minimum MR /nOE, FSEL0, FSEL1 Typical Maximum , A0 FSEL0 3 FSEL1 5 MR /nO E 12 13 Q A0 Zo = 50 36 FSEL0 FSEL1 Q A1


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PDF IDT8V40817 IDT8V40817 66-MHz 25MHz
2013 - Not Available

Abstract: No abstract text available
Text: ‘£ 出力電圧精度 A MR MR-G ⑤⑥-⑦ パッケージ形状 テーピング仕様(*2) 詳細内容 H , ( 40Î ¼s/div) 時間 ( 40Î ¼s/div) Time (40usec/div) XC6213 B152 XC6213B152 XC6213 B152 , (V) (V) Input Voltage: VIN 3 4 1.70 3 1.65 2 1 1.50 -1 1.45 時間 ( 40Î , Voltage 出力電圧 1.85 0 1.80 -1 1.75 時間 ( 40Î ¼s/div) Time ( 40Î ¼sec/div) 16/33 , œ§ VINOUT (V) V (V) 4 1.55 出力電圧 時間 (40usec/div) Time ( 40Î ¼s/div) 入力電å


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PDF XC6213 JTR0308-008
2006 - Not Available

Abstract: No abstract text available
Text: .) 35 PKG CODE LBF LBR MR RAMP PG3 EN5 LX3 PV3 RSO TOP VIEW V3 Pin Configuration Features MR 2C I INTERFACE V5 SCL SDA SYS_EN EN1,2,5 , (RSO) and MR Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , IN, IN5, IN6, IN67, EN2, EN34, EN5, LBO, RSO, MR , SET1, SET2, V1, V2, V3, V4, SCL, SDA, SRAD to , = +85°C UNITS µs +50 0.5 nA RESET ( MR , RSO) RSO Threshold VRSOTH RSO


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PDF T4055-1 MAX8660AETL+
2013 - Not Available

Abstract: No abstract text available
Text: FSEL[0:1] Pulldown nQB1 MR /nOE Pulldown REF_OUT nREF_OE Pullup ICS841664AGI , FSEL0 FSEL1 QB0 nQB0 V DDOB GND QB1 nQB1 MR /nOE V DD XTAL _IN XTAL_OUT GND ICS841664I 28 , Active low REF_OUT enable/disable. See Table 3E. LVCMOS/LVTTL interface levels. 19 MR /nOE Input , . Table 3D. MR /nOE Function Table Input MR /nOE Function NOTE 1 0 Outputs enabled 1 , 150 µA nREF_OE IIH REF_IN, REF_SEL, BYPASS, MR /nOE, FSEL0, FSEL1 VDD = VIN = 3.465V


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PDF ICS841664I ICS841664I 25MHz 125MHz
2006 - Not Available

Abstract: No abstract text available
Text: .) 35 PKG CODE LBF LBR MR RAMP PG3 EN5 LX3 PV3 RSO TOP VIEW V3 Pin Configuration Features MR 2C I INTERFACE V5 SCL SDA SYS_EN EN1,2,5 , (RSO) and MR Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , IN, IN5, IN6, IN67, EN2, EN34, EN5, LBO, RSO, MR , SET1, SET2, V1, V2, V3, V4, SCL, SDA, SRAD to , = +85°C UNITS µs +50 0.5 nA RESET ( MR , RSO) RSO Threshold VRSOTH RSO


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PDF T4055-1 MAX8660AETL+
2012 - Not Available

Abstract: No abstract text available
Text: lead-free packages Pin Assignment nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA , ·5 (default) 1 ÷4 M = ÷5 (fixed) nQB0 QB1 nQB1 F_SELB Pulldown MR Pulldown IREF OEB , Output Differential output pair. LVDS interface levels. 6 MR Input Pulldown Active High , VDD + 0.3 V VDD – 0.3 VDD + 0.3 V OEA, OEB, MR , F_SELA, F_SELB -0.3 0.8 V , OEA, OEB, MR , F_SELA, F_SELB BW_SEL VIL Input Low Voltage Minimum Typical VIM


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PDF ICS8741004I ICS8741004I 200kHz, 600kHz 200kHz
2013 - Not Available

Abstract: No abstract text available
Text: FSELB 1 Bank C QC0 FSELC QC1 0 POWER-ON RESET MR /OE (all input resistors have a value , FB_IN FSELC 5 GND 4 CCLK 3 MR /OE 2 F_RANGE 9 1 It is recommended to , PLL_EN Input LVCMOS PLL enable/disable MR /OE Input LVCMOS Output enable/disable , FSELC 0 Output divider  2 Output divider  4 MR /OE 0 Outputs enabled (active ,  4 0.99999943  6 RS = 40ï — ZO = 50 ZO = 50 OutA 0.99993663


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PDF MPC93H52 MPC93H52
2012 - XC6219

Abstract: No abstract text available
Text: ‘¢ 出力電圧 09 ~ 50 2(*3) 1(*2) ④ 出力電圧精度 A(*3) B(*2) MR MR-G ⑤⑥-â , œ§ 出力電圧 Time ( 40Î ¼sec/div) 時間 XC6219/11x182 XC6219/11x252 tr=tf=5μsec CL , =100mA 入力電圧 Time ( 40Î ¼sec/div) 出力電圧 時間 VOUT (V) 出力電圧 出力電å , =10mA tr=tf=5μsec CL=1μF (セラミック)、IOUT=1mA 出力電圧 時間 Time ( 40Î ¼sec/div , =100mA 出力電圧 tr=tf=5μsec CL=1μF (セラミック)、IOUT=10mA 入力電圧 Time ( 40Î ¼sec/div


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PDF XC6219/XC6211 JTR0307-009 300mA XC6219
2014 - Not Available

Abstract: No abstract text available
Text: and R5110Sxx2D (Detector with SENSE pin) have a manual reset ( MR ) pin. Watchdog Timer detects the , Current Limit GND CD MR SENSE DOUT TW INH SCK CLOCK DETECTOR WATCHDOG TIMER , MR / INH / WDO pins) are as follows: Product Name Package Quantity per Reel Pb Free , Range 25°C -40°C to 125°C MR / INH / WDO pins − − Yes Yes RESETB/ DOUT pins RESETB , Connection 7 NC No Connection 8 CD VD Release Delay Time Set pin 9 MR Manual Reset


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PDF R5110S EC-326-140213 500mA. 400mA Room403, Room109, 10F-1,
Supplyframe Tracking Pixel