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PIC32MX230F128H-V/PT Microchip Technology Inc RISC MICROCONTROLLER
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PIC32MX230F128H-50V/MR Microchip Technology Inc RISC MICROCONTROLLER
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PIC32MX230F128H-I/PT Microchip Technology Inc 32-BIT, FLASH, 50MHz, RISC MICROCONTROLLER, PQFP64
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PIC32MX230F128H-50I/MR MCU 32Bit PIC32 PIC RISC 128KB Flash 2.5V/3.3V 64-Pin QFN EP Tray - Rail/Tube (Alt: PIC32MX230F128H-50I/MR) PIC32MX230F128H-50I/MR ECAD Model
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PIC32MX230F128H-50I/MR datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
PIC32MX230F128H-50I/MR PIC32MX230F128H-50I/MR ECAD Model Microchip Technology Integrated Circuits (ICs) - Embedded - Microcontrollers - IC MCU 32BIT 128KB FLASH 64QFN Original PDF

PIC32MX230F128H-50I/MR Datasheets Context Search

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2009 - Not Available

Abstract: No abstract text available
Text: © SELA0 SELB1 0.1μF SELB0 QB1 QB1 SELA1 Z0 = 50Î © Z0 = 50Î © ASIC MR X_OUT , Circuit appear at end of data sheet. Block Diagram MR IN_SEL BYPASS SELA[1:0] QA_OE , +4.0V Voltage Range at REF_IN, IN_SEL, FB_SEL, SELA[1:0], SELB[1:0], QA_OE, QB_OE, MR , BYPASS , UNITS mA CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR , , BYPASS 75 k RPULLDOWN Pins MR , FB_SEL RBIAS RPULLUP LVPECL OUTPUTS (QA, QA, QB0, QB0, QB1


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PDF 27MHz MAX3625A 0416MHz U24-1
2013 - Not Available

Abstract: No abstract text available
Text: transition of the clock (CP). A low level on the master reser ( MR )input clears all the register , 9 MR Q0 3 Q1 4 Q2 5  Dsa Dsb 6 10 Q5 11 Q6 12 Q7 , ( MR ) L X X X L H ↑ L L L H ↑ L H L H ↑ H L L H ↑ H H H Note: H , =2.0V, IOH=- 50Î ¼A VCC=3.0V, IOH=- 50Î ¼A VCC=4.5V, IOH=- 50Î ¼A VCC=3.0V, IOH=-4mA VCC=4.5V, IOH=-8mA VCC=2.0V, IOL= 50Î ¼A VCC=3.0V, IOL= 50Î ¼A VCC=4.5V, IOL= 50Î ¼A VCC=3.0V, IOL=4mA VCC=4.5V, IOL=8mA VCC


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PDF U74AHC164 U74AHC164 U74AHC164L-S14-T U74AHC164G-S14-T U74AHC164L-S14-R U74AHC164G-S14-R U74AHC164L-P14-T U74AHC164G-P14-T U74AHC164L-P14-R U74AHC164G-P14at
2012 - Not Available

Abstract: No abstract text available
Text: lead-free packages Pin Assignment nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA , ·5 (default) 1 ÷4 M = ÷5 (fixed) nQB0 QB1 nQB1 F_SELB Pulldown MR Pulldown IREF OEB , Output Differential output pair. LVDS interface levels. 6 MR Input Pulldown Active High , VDD + 0.3 V VDD – 0.3 VDD + 0.3 V OEA, OEB, MR , F_SELA, F_SELB -0.3 0.8 V , OEA, OEB, MR , F_SELA, F_SELB BW_SEL VIL Input Low Voltage Minimum Typical VIM


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PDF ICS8741004I ICS8741004I 200kHz, 600kHz 200kHz
2015 - Not Available

Abstract: No abstract text available
Text: transition of the clock (CP). A low level on the master reser ( MR )input clears all the register ,  PIN CONFIGURATION  FUNCTIONAL DIAGRAM 8 CP 9 MR Q0 3 Q1 4 , TABLE INPUTS(CP) INPUTS(Dsa) INPUTS(Dsb) OUTPUTS(Q0) INPUTS( MR ) L X X X L H ↑ L L L , =3.0V VCC=5.5V VCC=2.0V VCC=3.0V VCC=5.5V VCC=2.0V, IOH=- 50Î ¼A VCC=3.0V, IOH=- 50Î ¼A VCC=4.5V, IOH=- 50Î ¼A VCC=3.0V, IOH=-4mA VCC=4.5V, IOH=-8mA VCC=2.0V, IOL= 50Î ¼A VCC=3.0V, IOL= 50Î ¼A VCC=4.5V, IOL= 50Î


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PDF U74AHC164 U74AHC164 U74AHC164G-S14-R U74AHC164G-P14-R OP-14 TSSOP-14 QW-R502-240
2013 - Not Available

Abstract: No abstract text available
Text: ] RIO_C[0:1] QC1 QC1 MR REF_OUT Figure 1. MPC9850 Logic Diagram Table 1. Pin Configurations , MHz Input (pull-down) VDD High MR Input LVCMOS Master Reset (pull-up) VDD Low , REF_33MHz 0 Selects 25 MHz Reference Selects 33 MHz Reference MR 1 Reset Normal , following equation. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply


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PDF MPC9850 MPC9850
Not Available

Abstract: No abstract text available
Text: ( MR ). A Q output follow s its D input when both Ea and Eb are LOW. When either Ea or Et or both) are HIGH, a latch stores the last valid data present on its D input before Ea o r Et> went HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. PIN NAMES Dn MR On On Ea and Eb , n nn n Eo Ea MR V ee Dj D; Ea L L H X X MR L L L L H Qn L H * * L ]Do ]Q ]0 ]o L , E C L · F100150 LOGIC D IA G R A M D4 MR Ea Eö D5 QO Qo 5l Qi 02 Û2


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PDF F100150 F100K F100150
2012 - Not Available

Abstract: No abstract text available
Text: outputs can be disabled (high-impedance) by deasserting the OE/ MR pin. In the PLL configuration with external feedback selected, deasserting OE/ MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/ MR will enable the outputs and close the phase locked loop, enabling the , x 25 K VCC Power_On Reset 3 x 25 K 3 CLK_STOP0 CLK_STOP1 OE/ MR Figure 1. MPC9331 , 7 VCC_PLL PWR_DN CCLK OE/ MR PCKL PCKL GND NC 8 NC MPC9331 It is


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PDF MPC9331 MPC9331
2008 - Not Available

Abstract: No abstract text available
Text: standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignments CLK nCLK MR VCC nFB_IN FB_IN , 20 K Package 6 19 Top View 7 MR 8 1 Q nQ QFB nQFB nc 17 VCCO nc nc , CLOCK GENERATOR nc 18 nc nc MR Pulldown VCC SEL3 Pulldown VCCO ICS8735AM , regenerating clocks with ï€ â€œzero delay.” MR Input Pulldown Active HIGH Master Reset. When , Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V SEL[0:3], MR VCC = VIN =


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PDF ICS8735-21 700MHz, ICS8735BYI-01LF ICS8735BKI-01LF ICS8735-21 25MHz 700MHz.
2012 - Not Available

Abstract: No abstract text available
Text: outputs can be disabled (high-impedance) by deasserting the OE/ MR pin. In the PLL configuration with external feedback selected, deasserting OE/ MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/ MR will enable the outputs and close the phase locked loop, enabling the , 25 K VCC Power_On Reset 3 x 25 K 3 CLK_STOP0 CLK_STOP1 OE/ MR Figure 1. MPC9331 , 7 VCC_PLL PWR_DN CCLK OE/ MR PCKL PCKL GND NC 8 NC MPC9331 It is


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PDF MPC9331 MPC9331
2013 - Not Available

Abstract: No abstract text available
Text: TEST_CLK nP_LOAD XTAL_SEL VCO_SEL VCO_SEL 32 31 30 29 28 27 26 25 1 M5 MR VCO ÷M 1 S_LOAD 6 19 S_DATA 7 18 S_CLOCK VEE 8 17 MR 9 10 11 12 13 , FOUT0, nFOUT0 Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 , internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values , TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X


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PDF ICS84321 260MHZ, ICS84321 620MHz 780MHz. 84321AY
2012 - Not Available

Abstract: No abstract text available
Text: deasserting the OE/ MR pin. In the PLL configuration with external feedback selected, deasserting OE/ MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/ MR will enable , CLK_STOP0 CLK_STOP1 OE/ MR Figure 1. MPC9331 Logic Diagram MPC9331 REVISION 7 DECEMBER 19, 2012 2 , CLK_STOP0 NC 32 9 1 2 3 4 5 6 7 VCC_PLL PWR_DN CCLK OE/ MR PCKL , LVCMOS PLL enable/disable CLK_STOP0-1 Input LVCMOS Clock output enable/disable OE/ MR


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PDF MPC9331 MPC9331
2013 - Not Available

Abstract: No abstract text available
Text: VCC XTAL_IN XTAL_OUT nc nc VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE ICS8431-21 TEST_I/O , interface levels. 18 VCCO Power 19 DIV_SEL Input 20 MR Input 22 VCCA , internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M and T values , Parameter M0:M8, SSC_CTL0, SSC_CTL1, MR , High Voltage DIV_SEL, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, SSC_CTL1, MR , Low Voltage DIV_SEL, TEST_I/O, nP_LOAD M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO High Current


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PDF ICS8431-21 350MHZ, ICS8431-21 IA64/32 250MHz 700MHz 350MHz.
2009 - Not Available

Abstract: No abstract text available
Text: Phase VCO Detector 11 OE_B Pullup MR Pulldown OE_REF Pulldown S_LOAD Pulldown nP_LOAD , XTAL_OUT0 XTAL_IN0 REF_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR VEE nc VCCO_REF REF_OUT , when using center spread. POWER-UP OPERATION MR PIN OPERATION The 843034-06 has internal , , either due to an external change or a change in the SEL pins, the MR pin must go high and low to relock , 25 MR Input Pulldown 26 S_CLOCK Input Pulldown 27 S_DATA Input


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PDF ICS843034-06 ICS843034-06 ICS84303406
2013 - Not Available

Abstract: No abstract text available
Text: VDD Q0 nQ0 VDDA Pin Assignment 4 21 Q2 nQ2 19 Q1 7 18 nQ1 MR 8 17 VDDO SEL1 VDDO Q0 nQ0 GND ICS8624 MR ICS8624BY REVISION F OCTOBER , input. Inverting differential clock input. 8 MR Input 9, 32 VDD Power 10 nFB_IN , 150 µA PLL_SEL IIH CLK_SEL,ï€ SEL[0:1], MR VDD = VIN = 3.465V 5 µA Input Low Current CLK_SEL,ï€ SEL[0:1], MR VDD = 3.465V, VIN = 0V -5 µA PLL_SEL IIL


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PDF ICS8624 ICS8725BY-01LF ICS8624 250MHz 700MHz. 700MHz
2013 - Not Available

Abstract: No abstract text available
Text: VCC XTAL_IN XTAL_OUT nc nc VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE ICS8431-21 TEST_I/O , interface levels. 18 VCCO Power 19 DIV_SEL Input 20 MR Input 22 VCCA , internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M and T values , Parameter M0:M8, SSC_CTL0, SSC_CTL1, MR , High Voltage DIV_SEL, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, SSC_CTL1, MR , Low Voltage DIV_SEL, TEST_I/O, nP_LOAD M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO High Current


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PDF ICS8431-21 350MHZ, ICS8431-21 IA64/32 250MHz 700MHz 350MHz.
2013 - Not Available

Abstract: No abstract text available
Text: ASSIGNMENT QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 , ) QB0 nQB0 MR Pulldown Pullup OEB IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 1 , interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output 5 MR , OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR VDD = 3.465V, VIN = 0V , 1.8V Zo = 50Î © Zo = 50Î © CLK CLK Zo = 50Î © Zo = 50Î © nCLK nCLK Differential


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PDF ICS874003DI-02 ICS874003DI-02 874003DGI-02LFT ICS4003DI02L ICS874003DGI-02
2013 - Not Available

Abstract: No abstract text available
Text: CLK nCLK MR VDD nFB_IN FB_IN SEL2 GND nQFB QFB 1 2 3 4 5 6 7 8 9 10 20 19 18 , Pulldown SEL3 Pulldown MR Pulldown IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR 1 ICS8725AM , dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 3 MR Input 4, 17 VDD , 0.3 V -0.3 0.8 V SEL[0:3], MR VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 5 µA SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA PLL_SEL VDD =


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PDF ICS8725-21 ICS8725BY-01LF ICS8725-21 25MHz 630MHz.
2009 - Not Available

Abstract: No abstract text available
Text: =10μF (ceramic) 100 VOUT=3.3V PVSS 1 MR NC 70 MR AVSS PVSS 2 NC LX2 NC , 1 NC MR 14 2 PVSS1 AVSS 13 NC 7 4 PVSS2 5 NC PVDD2 6 NC 9 VDOUT 10 QFN , Ground 3 NC No Connection 13 A_VSS 4 P_VSS2 Power Ground 2 14 MR Manual , pad voltage level.) 2/21 XC9515 Series ■FUNCTION CHART ●EN1, EN2 and MR pins are internally pulled up. * PIN EN1 EN2 MR 2) LEVEL OPERATIONAL STATUS High , Open DC/DC_CH1


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PDF XC9515 ETR0706-010 800mA.
2012 - Not Available

Abstract: No abstract text available
Text: deasserting the MR /OE pin (logic high state). Asserting MR /OE will enable the outputs. All control inputs , QA0 0 QA1 QA2 VCC/2 Bank B QB0 0 QB1 1 QB2 QC0 FSELA FSELB FSELC MR /OE , 31 10 QC0 MR /OE 32 9 VCCC VCC PECL_CLK PECL_CLK 5 6 7 8 GND , select input MR /OE Input LVCMOS Internal reset and output tristate control GND Supply , FSELC 0 fQC0:3 = fREF fQC0:3 = fREF  2 MR /OE 0 Outputs enabled Internal reset


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PDF MPC9456 MPC9456
2012 - Not Available

Abstract: No abstract text available
Text: deasserting the MR /OE pin (logic high state). Asserting MR /OE will enable the outputs. All control inputs , QC1 25k 1 QC2 FSELB FSELC QC3 25k MR /OE 25k VCCC VCCB QB2 GND QB1 , 31 10 QC0 MR /OE 32 9 VCCC VCC PECL_CLK PECL_CLK 5 6 7 8 GND , select input MR /OE Input LVCMOS Internal reset and output tristate control GND Supply , FSELC 0 fQC0:3 = fREF fQC0:3 = fREF  2 MR /OE 0 Outputs enabled Internal reset


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PDF MPC9456 MPC9456
2013 - 0437P

Abstract: No abstract text available
Text: XTAL_IN VCO Detector OSC 0 nQ1 0 nc VCCO Q0 nQ0 MR nPLL_SEL nc VCCA nc VCC , nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT nc XTAL_OUT IDT8V43042 nXTAL_SEL MR Pulldown M = 25 , interface levels. No connect 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH , nPLL_SEL, nXTAL_SEL, MR pF TEST_CLK IDT8V43042PGG REVISION A JULY 18, 2013 4 2 pF 51 , Voltage VCC = 3.3V ± 5% -0.3 0.8 V IIH Input High Current TEST_CLK, MR , nPLL_SEL


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PDF IDT8V43042 IDT8V43042 25MHz 24MHz, 25MHz 150MHz, IDT8V43042â 20-pin 0437P
2013 - Not Available

Abstract: No abstract text available
Text: 15 14 13 12 11 10 9 Q nQ VCCO VCC VEE MR nPLL_SEL nc ICS843201-375 16-Lead TSSOP , MARGIN Pulldown MR Pulldown ICS843201AG-375 REVISION A APRIL 26, 2013 1 ©2013 , nPLL_SEL Input Pulldown 11 MR Input Pulldown 14 VCCO Power Positive supply , Input Low Voltage IIH Input High Current MARGIN, MODE, nPLL_SEL, MR IIL Input Low Current MARGIN, MODE, nPLL_SEL, MR Minimum Typical 2 Maximum VCC + 0.3 Units V VCC +


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PDF ICS843201-375 375MHZ, ICS843201-375 375MHz 25MHz 16-pin 25MHz,
2010 - Not Available

Abstract: No abstract text available
Text: 18 nQ1 MR PLL 8 17 VCCO ICS8735-01 9 10 11 12 13 14 15 16 VCCO Q0 , 1.4mm package body Y Package Top View SEL3 MR 32-Lead VFQFN 5mm x 5mm x 0.95 package body K , nCLK0 Input 5 CLK1 Input 6 nCLK1 Input 7 CLK_SEL Input 8 MR Input , 3.465V 5 µA CLK_SEL, MR , SEL0, SEL1, SEL2, SEL3 VIN = 0V, VCC = 3.465V -5 µA PLL_SEL IIL CLK_SEL, MR , SEL0, SEL1, SEL2, SEL3 PLL_SEL VIN = 0V, VCC = 3.465V -150 µA


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PDF ICS8735-01 ICS8735BYI-01LF ICS8735BKI-01LF ICS8735-01 25MHz 700MHz. 8735AY-01
2014 - Not Available

Abstract: No abstract text available
Text: Table Inputs Outputs QA1 VDDO QA0 nQA0 MR F_SEL0 nc 1 2 3 4 5 6 7 8 9 10 20 , VCO nQA1 490 - 640MHz 3 ÷5 ÷4 ÷2 (default) M = ÷5 (fixed) QB0 nQB0 MR , Differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset , -0.3 0.8 V OEA, OEB VDD = VIN = 3.465V 5 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = , , F_SEL2, MR VDD = 3.465V, VIN = 0V -5 µA ICS874003AG-04 REVISION B JANUARY 28, 2014 4 Â


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PDF ICS874003-04 ICS874003-04
2014 - Not Available

Abstract: No abstract text available
Text: MR F_SEL0 nc ÷4 ICS874003DG-02 REVISION A FEBRUARY 5, 2014 QB0, nQB0 VDDA F_SEL1 VDD , ·5 ÷4 ÷2 (default) M = ÷5 (fixed) MR OEB QB0 nQB0 Pulldown Pullup , Differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset , Input High Current IIL Input Low Current OEA, OEB VDD = VIN = 3.465V 5 µA MR , MR , F_SEL[2:0] VDD = 3.465V, VIN = 0V -5 µA ICS874003DG-02 REVISION A FEBRUARY 5, 2014


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PDF ICS874003D-02 ICS874003D-02
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