The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC4400-2EMS8 Linear Technology LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC4403-1EMS8 Linear Technology LTC4403 - Multiband RF Power Controllers for EDGE/TDMA; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LT1328CS8#PBF Linear Technology LT1328 - 4Mbps IrDA Infrared Receiver; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT5521EUF#PBF Linear Technology LT5521 - Very High Linearity Active Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
LT5527EUF#PBF Linear Technology LT5527 - 400MHz to 3.7GHz High Signal Level Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
LTC1758-2EMS#PBF Linear Technology LTC1758-1 - RF Power Controllers with 250kHz Control Loop Bandwidth and 40dB Dynamic Range; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C

PECI 2.0 specification Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2009 - W83795G

Abstract: w83795adg SBI Temperature Sensor Interface SB-TSI SB-TSI Intel PECI2.0 interface tr3 thermistor marking code ADg W83795 Intel PECI2.0 interface, FAN301
Text: CPU temperature PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) Support PECI 2.0 Specification , PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) Support PECI 2.0 Specification Support 8 CPU Address , .105 PECI CONTROL AND SB-TSI FUNCTION . 122 11.1 PECI Control Registers , ) . 128 12.3 PECI Control Register (PCR


Original
PDF W83795G/ADG May/05/2009 W83795G/A W83795G) W83795ADG) W83795G w83795adg SBI Temperature Sensor Interface SB-TSI SB-TSI Intel PECI2.0 interface tr3 thermistor marking code ADg W83795 Intel PECI2.0 interface, FAN301
2010 - 1c 78 adg

Abstract: SB-TSI W83795 marking code ADg W83795G SBI Temperature Sensor Interface SB-TSI W83795ADG Amd 6970 Intel PECI2.0 interface SBI Temperature Sensor Interface SB-TSI Specification,
Text: CONTROL INTERFACE) z Support PECI 2.0 Specification z Support 8 CPU Address and 2 domains per CPU , . (Including PECI_REQ# mechanism). PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) z Support PECI 2.0 , .102 11. 12. 13. PECI CONTROL AND SB-TSI FUNCTION . 118 11.1 PECI Control Registers , ) . 124 12.3 PECI Control Register (PCR


Original
PDF W83795G/ADG Aug/2/2010 W83795G/ADG W83795G) W83795ADG) Aug/2/2010 1c 78 adg SB-TSI W83795 marking code ADg W83795G SBI Temperature Sensor Interface SB-TSI W83795ADG Amd 6970 Intel PECI2.0 interface SBI Temperature Sensor Interface SB-TSI Specification,
Not Available

Abstract: No abstract text available
Text: ¬ Support PECI 2.0 Specification  Support 8 CPU Address and 2 domains per CPU address AMDTM SB-TSI , PECI 2.0 Specification  Support 8 CPU Address and 2 domains per CPU address FAN Up to 2 Fan , . 100 PECI CONTROL AND SB-TSI FUNCTION . 116 - ii – Mar/3/2011 Revision 1.43 W83795G/ADG 12. 13. 11.1 PECI Control , ) . 122 12.3 PECI Control Register (PCR


Original
PDF W83795G/ADG Mar/3/2010 W83795G) W83795ADG) Mar/3/2011
2011 - socket lga 1156 pinout

Abstract: intel i5 MOTHERBOARD pcb CIRCUIT diagram i3 desktop MOTHERBOARD CIRCUIT diagram 115XLM LGA 1156 PIN OUT diagram LGA 1150 Socket PIN diagram Intel socket 1156 PIN LAYOUT Socket 1156 VID pinout 1155 socket REFLOW profile lga socket 1155
Text: 2.1.6 Processor Mass Specification . , Specifications and Design Guidelines 3 6.2 6.3 Processor Specification for Operation Where Digital , .52 Platform Environment Control Interface ( PECI , .52 6.3.2 PECI Client Capabilities , .53 6.1.3 7 Sensor-Based Thermal Specification Design Guidance


Original
PDF i5-600, i3-500 LGA1156 E58389 socket lga 1156 pinout intel i5 MOTHERBOARD pcb CIRCUIT diagram i3 desktop MOTHERBOARD CIRCUIT diagram 115XLM LGA 1156 PIN OUT diagram LGA 1150 Socket PIN diagram Intel socket 1156 PIN LAYOUT Socket 1156 VID pinout 1155 socket REFLOW profile lga socket 1155
2011 - vr 0511 mb

Abstract: bg37 intel G41 MOTHERBOARD pcb CIRCUIT diagram intel g45 MOTHERBOARD pcb CIRCUIT diagram LGA1567 peci specification Intel socket 479 PIN LAYOUT 0000H-FFFFH schematic intel g41 AT8060
Text: Control Interface ( PECI ) DC Specifications. 40 2.6.1 DC Characteristics , 3.1.6 Processor Mass Specification . , . 121 Platform Environment Control Interface ( PECI ) . 121 6.3.1 PECI Client Capabilities , . 50 Differential Clock Crosspoint Specification


Original
PDF E78800/4800/2800 E7-8800/4800/2800 vr 0511 mb bg37 intel G41 MOTHERBOARD pcb CIRCUIT diagram intel g45 MOTHERBOARD pcb CIRCUIT diagram LGA1567 peci specification Intel socket 479 PIN LAYOUT 0000H-FFFFH schematic intel g41 AT8060
2009 - peci specification

Abstract: PECI 2.0 specification intel PC MOTHERBOARD CIRCUIT diagram x86 family 6 model 7 stepping 3
Text: ) . 18 1.2.5 Platform Environment Control Interface ( PECI , ) . 28 2.5 Platform Environment Control Interface ( PECI ) . 29 2.5.1 PECI Client Capabilities , Retry and Timeout Policy . 72 2.5.3.10 Enumerating PECI , . 118 6.5 PECI Signal


Original
PDF E5-2400 peci specification PECI 2.0 specification intel PC MOTHERBOARD CIRCUIT diagram x86 family 6 model 7 stepping 3
2006 - A16HR

Abstract: a14hr circuit diagram laptop motherboard amd athlon 64 x2 voltage pins peci AMD Athlon 64 X2 2N3906 2N3904 MMBT3904 AMD Athlon 64 X2 thermal
Text: Preliminary Specification ­ Subject to change without notice GPIO1 GPIO2 GPIO3 PECI INTERFACE , aSC7621 HARDWARE MONITOR WITH INTEGRATED FAN CONTROL PRODUCT SPECIFICATION Preliminary Specification Measurement System The aSC7621 has a two wire digital interface compatible with SMBus 2.0 , as well as its own die. Support for Platform Environmental Control Interface ( PECI ) is included , 2's complement coding. Supports PECI interface and monitors internal and remote thermal diodes


Original
PDF aSC7621 aSC7621 10-bit 70A06010 A16HR a14hr circuit diagram laptop motherboard amd athlon 64 x2 voltage pins peci AMD Athlon 64 X2 2N3906 2N3904 MMBT3904 AMD Athlon 64 X2 thermal
2009 - PECI 2.0 specification

Abstract: No abstract text available
Text: ) . 17 1.2.5 Platform Environment Control Interface ( PECI , . 28 2.5 Platform Environment Control Interface ( PECI ) . 31 2.5.1 PECI Client Capabilities , Retry and Timeout Policy .74 2.5.3.10 Enumerating PECI , Specification . 115 5.1.2.5 50W 8-Core Thermal


Original
PDF E5-2400 E5-2400 PECI 2.0 specification
2007 - peci specification

Abstract: 8103H peci
Text: Refer to Intel PECI specification . PECI transaction failed for more than the configured number of , VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset , AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input


Original
PDF MAX6621 400kbps. 21-0061I MAX6621AUB+ MAX6621AUB peci specification 8103H peci
2007 - F640

Abstract: MAX6621 8103H peci specification
Text: Refer to Intel PECI specification . 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2 C SCL VREF SDA SCL MASTER RESET MAX6621 PECI CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN


Original
PDF 400kbps MAX6621 F640 8103H peci specification
2007 - Not Available

Abstract: No abstract text available
Text: 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification . PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input


Original
PDF MAX6618 400kbps. 400kbps
2007 - f640

Abstract: No abstract text available
Text: 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification . PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input


Original
PDF MAX6618 400kbps. 400kbps 21-0061I MAX6618AUB+ MAX6618AUB f640
2007 - peci specification

Abstract: MAX6621
Text: 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification . PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input


Original
PDF MAX6618 400kbps. 400kbps 21-0061I MAX6618AUB+ MAX6618AUB peci specification MAX6621
2009 - STS200C

Abstract: CSR BC57 MRC 08 peci specification LGA2011 G41 MOTHERBOARD SERVICE MANUAL mainboard g41 Marking L43 3pin STS200PNRW BR17
Text: 18 1.2.5 Platform Environment Control Interface ( PECI ) . 18 , . 28 2.5 Platform Environment Control Interface ( PECI ) . 30 2.5.1 PECI Client Capabilities , . 144 6.5 PECI Signal , 151 7.1.5 Platform Environmental Control Interface ( PECI ) . 152


Original
PDF E5-1600 E5-2600 STS200C CSR BC57 MRC 08 peci specification LGA2011 G41 MOTHERBOARD SERVICE MANUAL mainboard g41 Marking L43 3pin STS200PNRW BR17
2013 - peci specification

Abstract: No abstract text available
Text: PECI specification . PECI transaction failed for more than the configured number of consecutive retries , MAX6618 PECI-to-I2C Translator General Description The MAX6618 PECI (1.0)-to-I2C translator provides an efficient, low-cost solution for PECI (1.0)-to-SMBus/I2C protocol conversion. The PECI (1.0)-compliant host reads temperature data directly from up to four PECI (1.0)-enabled CPUs. This translator will only communicate with CPUs that support PECI 1.0. The I2C interface provides an independent serial


Original
PDF MAX6618 400kbps. 400kbps peci specification
2007 - F640

Abstract: MAX6621 07HREAD peci I2C BUS address translator 8103H peci specification
Text: Refer to Intel PECI specification . 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2C SCL SDA VREF SCL PECI MASTER RESET MAX6621 CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN


Original
PDF 400kbps MAX6621 F640 07HREAD peci I2C BUS address translator 8103H peci specification
2007 - peci specification

Abstract: No abstract text available
Text: Refer to Intel PECI specification . PECI transaction failed for more than the configured number of , VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset , AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input


Original
PDF MAX6621 400kbps. 21-0061I MAX6621AUB+ MAX6621AUB peci specification
2009 - peci specification

Abstract: peci F640 MAX6621 I2C BUS address translator 8103H
Text: Refer to Intel PECI specification . 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2C SCL VREF SDA SCL MASTER RESET MAX6621 PECI CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN


Original
PDF 400kbps MAX6621 peci specification peci F640 I2C BUS address translator 8103H
2007 - peci

Abstract: F640 MAX6618 MAX6618AUB alternate SDA
Text: COMMAND 09h ERROR CODES DESCRIPTION 8000h­ 80FFh Refer to Intel PECI specification , +120°C Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage , Circuit +3.3V VCPU VTT VCC SDA I2C SCL VREF SDA SCL MASTER AD2 MAX6618 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current , VIL V +2 10 µA pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V


Original
PDF MAX6618 400kbps. 400kbps peci F640 MAX6618AUB alternate SDA
2011 - Not Available

Abstract: No abstract text available
Text: PECI specification . PECI transaction failed for more than the configured number of consecutive retries , Input Refers Logic Levels to the PECI Supply Voltage o Automatic I2C Bus Lockup Timeout Reset o , MAX6618 SCL PECI CPU INTERNAL TEMP SENSOR For pricing, delivery, and ordering information, please , PECI .-0.3V to (VREF + 0.3V) DC Current through , ADDRESS INPUT AD0 Low-Level Input Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI


Original
PDF MAX6618 400kbps. 400kbps PECI-to-16
2013 - Not Available

Abstract: No abstract text available
Text: €“ 80FFh Refer to Intel PECI specification . 8100h PECI transaction failed for more than the , -Wire Serial Interface The MAX6618 PECI (1.0)-to-I2C translator provides an efficient, low-cost solution for PECI (1.0)-to-SMBus/I2C ♦ ♦ ♦ ♦ ♦ ♦ +3V to +3.6V Supply Voltage PECI (1.0)-Compliant Port PECI (1.0)-to-I2C Translation Programmable Temperature Offsets -20°C to +120°C Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage ♦ Automatic I2C Bus Lockup


Original
PDF MAX6618 400kbps MAX6618 10-Pin
2011 - F640

Abstract: MAX6618 MAX6618AUB
Text: COMMAND 09h ERROR CODES DESCRIPTION 8000h­ 80FFh Refer to Intel PECI specification , to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset Lead-Free, 10-Pin µMAX , Circuit +3.3V VCPU VTT VCC SDA I2C SCL SCL VREF SDA MASTER AD2 MAX6618 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current , 10 pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range


Original
PDF 400kbps MAX6618 10-Pin MAX6618 F640 MAX6618AUB
2009 - intel PC MOTHERBOARD CIRCUIT diagram x86 family 6 model 7 stepping 3

Abstract: MSI G41 MOTHERBOARD CIRCUIT diagram STR 6757 OF equivalent g41 msi motherboard circuit diagram MSI G31 Motherboard JESD-A103 INTEL 845 MOTHERBOARD CIRCUIT diagram philips semiconductor data handbook xeon e5 cpuid sddc
Text: 18 1.2.5 Platform Environment Control Interface ( PECI ) . 18 , . 28 2.5 Platform Environment Control Interface ( PECI ) . 30 2.5.1 PECI Client Capabilities , . 144 6.5 PECI Signal , 151 7.1.5 Platform Environmental Control Interface ( PECI ) . 152


Original
PDF E5-1600/ E5-2600/E5-4600 E5-1600/E5-2600/E5-4600 E5-2600 intel PC MOTHERBOARD CIRCUIT diagram x86 family 6 model 7 stepping 3 MSI G41 MOTHERBOARD CIRCUIT diagram STR 6757 OF equivalent g41 msi motherboard circuit diagram MSI G31 Motherboard JESD-A103 INTEL 845 MOTHERBOARD CIRCUIT diagram philips semiconductor data handbook xeon e5 cpuid sddc
2007 - intel i5 MOTHERBOARD pcb CIRCUIT diagram

Abstract: intel core 2 extreme quad-core QX6800 LGA775 socket mechanical design guidelines intel desktop board SERVICE MANUAL intel lga775 MOTHERBOARD pcb CIRCUIT diagram lga775 GTLREF Voltage Regulator-Down 11.0 PVC AM3 W23
Text: . 16 2.5 Voltage and Current Specification , 17 2.5.2 DC Voltage and Current Specification , 2.8 PECI DC Specifications , . 36 3.6 Processor Mass Specification , .78 Platform Environment Control Interface ( PECI


Original
PDF QX6800 775-land i7-2630QM/i7-2635QM, i7-2670QM/i72675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. 720/Intel-Core2-Extreme-Processor-QX6800- 05-Sep-2011 intel i5 MOTHERBOARD pcb CIRCUIT diagram intel core 2 extreme quad-core QX6800 LGA775 socket mechanical design guidelines intel desktop board SERVICE MANUAL intel lga775 MOTHERBOARD pcb CIRCUIT diagram lga775 GTLREF Voltage Regulator-Down 11.0 PVC AM3 W23
f71882

Abstract: 2N3906 pc MOTHERBOARD intel circuit diagram INTEL 8042 peci specification 16C550 circuit diagram of 3 wire cpu fan speed control amikkeytm-2
Text: interface. The SPI interface is for SPI BIOS usage. Others, the F71882 supports newest AMDSI and Intel PECI , SID/SIC interface and Intel SST/ PECI interface 32 GPIO Pins for flexible application 24/48 MHz clock , specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Enhanced , Integrate Intel PECI /SST Interface Package 128-pin PQFP Green Package Noted: Patented TW207103 TW207104 , .29P F71882 3. Key Specification Supply Voltage 3.0V to 3.6V Operating Supply Current - mA typ


Original
PDF F71882 F71882 2N3906. 128-pin TW207103 TW207104 TW220442 US6788131 2N3906 pc MOTHERBOARD intel circuit diagram INTEL 8042 peci specification 16C550 circuit diagram of 3 wire cpu fan speed control amikkeytm-2
Supplyframe Tracking Pixel