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0FLR0726XP Littelfuse Inc FLASHER 726 THERM CARD
0FLR0726XPA Littelfuse Inc FLASHER 726 THERM CARD
HMC726LC3CTR Hittite Microwave Corp OR-AND/OR-AND-Invert Gate, 726 Series, 1-Func, 2-Input, CQCC16, 3 X 3 MM, ROHS COMPLIANT, CERAMIC, SMT-16
HMC726LC3C Hittite Microwave Corp OR-AND/OR-AND-Invert Gate, 726 Series, 1-Func, 2-Input, CQCC16, 3 X 3 MM, ROHS COMPLIANT, CERAMIC, SMT-16

PEC 726 UF1004FCT Datasheets Context Search

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2010 - Zener Diode 13B3

Abstract:
Text: calculates a PEC in the same manner. This byte is compared with the appended byte to check that the data transmission was properly executed. Both PEC bytes are displayed in the top section labeled PACKET ERROR CODE , one board will turn green if the PEC bytes match. Data transmission errors will produce red warning indications if the PEC bytes do not match. 1: READ CONFIGURATION 2: WRITE CONFIGURATION 4B FIRST , six bytes read back should match the six bytes sent and the PEC /CRC check bytes should be a match


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PDF DC1331D LTC6802-1 DC1331D 13msec) 11msec) Zener Diode 13B3 zener 10B1 pec 726 zener 13B3 DC1331 DC590B LTC6801 LTC6802
1998 - vehicle rain sensor

Abstract:
Text: 20 0 Outputs BTS 726 BTS 711 Inputs for switch diagnostics Components 6|97 , CAN Digital outputs Smart power BTS 711 BTS 726 8 15 2 EEPROM I2C . To , Siemens in Stuttgart. A PEC transfer function (100 ns at 20 MHz) is used to store the A/D values in


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PDF C167CR C167CR* ISO-9141 products/ICs/34/167 vehicle rain sensor PEC 726 UF1004FCT rain sensor rain sensor automotive pec 726 ISO 9141 K line interface iso 9141 driver diesel control
2009 - RTL8111C-GR

Abstract:
Text: ) 16 lbs ( 7.26 kg) Black Mid-Tow er CSE-731i-300B CPU LEDs Ports Drive Bays Internal System , trademarks of their res pec tive c ompanies or mark holders . P age V iewed: T ues day, M arc h 2 4 , 2 0 0 9


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PDF 5035L-IB LGA775 32-bit 33MHz RTL8111C-GR SYS-5035L-IB CSE-731i-300B CBL-0139L PWS-303-PQ 945 motherboard bios chip AMI Intel Pentium D 925
voice recognition kit interfacing 8051

Abstract:
Text: in the PEC register (bit 1). The pin is configured by bit 2 of the PEC register. An alternate , interface. P4 11 PERIPHERAL INTERFACE OUTPUT PIN: This pin outputs data stored in the PEC register (bit 0 , 'J J NOTE: Status indicators are activated by the SST Bit in the PEC Register Figure 7. 29C53 SLD Status Indicators 7-26 JIM This Material Copyrighted By Its Respective Manufacturer 29C53 (A) S* I , WR (RT) LCR Loop Interlace Control 00011 RDWR PEC Peripheral Interface and E-Channel Control 00100


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PDF 29C53 29C53 voice recognition kit interfacing 8051 pec 730 MARK A03 fxs interface integrated circuit Alternate Mark Inversion 8088 microprocessor block diagrammed with direction 8086 microprocessor pin diagram 29CS3 29C530
29C53

Abstract:
Text: data stored in the PEC register (bit 1). The pin is configured by bit 2 of the PEC register. An , SLD interface. P4 11 PERIPHERAL INTERFACE OUTPUT PIN: This pin outputs data stored in the PEC , SLAVE- MASTER JT _r NOTE: Status indicators are activated by the SST Bit ir> the PEC Register Figure 7. 29C53 SLD Status Indicators 7-26 Powered by ICininer.com Electronic-Library Service CopyRight , Interface Status 00010 WR (RT) LCR Loop Interface Control 00011 RDWR PEC Peripheral Interface and


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PDF 29C53 29C53 Alternate Mark Inversion 0PLC 29C48 N29C53 Matra Semiconductor counter LXC14 "SLDC" 64KBPS P29C53
Not Available

Abstract:
Text: 4 -4 7-26 Functional Description The 'FCT374A consists ot eight edge-triggered flip-flops , guaranteed but not tested. Not« 3: Pec TTL driven input (Vin = 3.4V); all other inputs at Vcc or GND. Not« 4


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PDF 54FCT/74FCT374A FCT374A 54/74FCT374A 54/74FCT374A 54FCTA/74FCTA
2004 - Super10

Abstract:
Text: ) . 14 2.5 INTERRUPT AND PEC CONTROLLER , . 21 3.4.1 PEC Source and Destination Pointers , . 113 7.2.1 PEC Control Registers . 114 7.2.2 PEC Interrupt Control Register . 115 7.2.3 PEC Source and Destination Pointers


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PDF Super10 Super10 Super10, phbx M340 equivalent ST10 R000 M342 M341 M340 EE28H unex phe
2004 - IC M345 data

Abstract:
Text: ) . 15 2.5 INTERRUPT AND PEC CONTROLLER , . 21 3.4.1 PEC Source and Destination Pointers , . 116 7.2.1 PEC Control Registers . 117 7.2.2 PEC Interrupt Control Register . 119 7.2.3 PEC Source and Destination Pointers


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PDF Super10 M345/M350 Super10 Super10, SUPER10UM IC M345 data 125-SPUM m35011 BEI15 00-F6 C16x Family Instruction Set Manual phbx EE44h M340
2012 - Not Available

Abstract:
Text: No file text available


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PDF LTC6804-1/LTC6804-2 16-Bit ISO26262 LTC6804 LTC3300 LiFeP04 48-Lead com/LTC6804-1 680412fb
1998 - STK 419 140

Abstract:
Text: . . . . . . . . . . . . . . . . . . . 5-5 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Prioritization of Interrupt and PEC , 5-16 PEC Response Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . 7-26 Alternate Functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Introduction C161RI 8-Channel Peripheral Event Controller ( PEC ) · · · Interrupt driven single cycle


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PDF C161RI 16-Bit STK 419 140 i2c vhdl code SDA2526 MULTIMASTER c167 i2c incremental encoders siemens C500 C167 C166 C161RI-LM C161RI-LF
2012 - TG110-AE050N5

Abstract:
Text: No file text available


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PDF LTC6804-1/LTC6804-2 n16-Bit ISO26262 n48tionally LTC6802 LTC6804 LiFeP04 48-Lead 680412f com/LTC6804-1 TG110-AE050N5 THERMISTORS - SCK 054 LT6804-2 LT6804-1 LTC6804-1 TG110-AEX50N5LF isospi LTC6804G-2 LTC6804-2 LTC6804IG-2
2012 - LTC6804IG-1

Abstract:
Text: No file text available


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PDF LTC6804-1/LTC6804-2 16-Bit ISO26262 LTC6804 LTC3300 LiFeP04 48-Lead 680412fa com/LTC6804-1 LTC6804IG-1
1998 - Siemens MTT 95 A 12 N

Abstract:
Text: . . . . . . . . . . . . . . . . . . . . . . . 5-5 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Prioritization of Interrupt and PEC , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 PEC Response Times . , 7-26 7-27 1998-05-01 C161RI General Information Table of Contents Page 14 14.1 The , C161RI 8-Channel Peripheral Event Controller ( PEC ) · · · Interrupt driven single cycle data


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PDF C161RI 16-Bit Siemens MTT 95 A 12 N STK 419 140 stk 8051 STK 419 130 "Duty cycle measurement" Siemens MTT 95 A 16 N barrel shifter block diagram C161RI-LF C161RI all stk ic diagram
CPU21

Abstract:
Text: affects FAsteps only) BUS.18 ( PEC transfers after JMPR) CPU.17 (Arithmetic Overflow by DIVLU instruction , overflow. Interrupts and PEC transfers, however, can not be processed. In case NMI# is asserted low while , conditions are true at the same time: (1) the previous 'instruction' is a PEC transfer which writes to IRAM , previous instruction or PEC transfer within the instruction pipeline ('back-to-back' execution), i.e. decode phase of BFLDx and execute phase of the previous instruction or PEC transfer coincide. This


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PDF SAB-C161O-LM SAF-C161O-LM SAB-C161O-LM3V SAF-C161O-LM3V P-MQFP-80-1 C161K/C161O C161V/K/O C161O C161O/K C161PI CPU21 AP1628 rtx166 SAB-C161O-LM RTX-166 P-MQFP-80-1 IDCHIP FIX166 C166 WDTCON
2005 - AVR316

Abstract:
Text: Supports 9 different SMBus protocols Packet error checking ( PEC ) Interrupt-driven SMBus slave driver , each byte, even if it is the last byte in the transfer. 2.2 Packet Error Code ( PEC ) The SMBus specification includes a CRC based error detection algorithm called Packet Error Code ( PEC ). An SMBus device is not required to use PEC , but any device with PEC capability must be able to communicate with other SMBus devices that do not implement PEC . 2 AVR316 2583A-AVR-10/05 AVR316 The PEC is


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PDF AVR316: 583A-AVR-10/05 AVR316 PEC 408 ATMEGA16 note application STK500
2001 - magnetizer circuit

Abstract:
Text: PCC HP for High Power Converters - Application Guide PEC as DC Link capacitor or For , Solutions for July 16th, 2001 FK PM PEC Compact Converter Structures PCC HP PCC HP , systems n Link capacitors n Series resonant circuit capacitors PEC New applications n Industrial , etc. July 16th, 2001 FK PM PEC PCC HP PCC HP for Compact Converter - Your Advantages , PEC PCC Example of compact converter structure with PCC HP July 16th, 2001 FK PM PEC PCC


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PDF
2010 - b25620

Abstract:
Text: Film capacitors ­ Power electronic capacitors MKP PEC DC Series/Type: Ordering code: B2562 , /Classification 2 (header 2 + bottom left header bar): MKP PEC DC Ordering code: (top right header bar , ) Preliminary data Department: FK PEC Date: June 2010 Version: 3.2 EPCOS AG 2010 , capacitors MKP PEC DC B2562* Preliminary data Metallized polypropylene film capacitors - aluminum , between terminals of 50 mm is available only for capacitors with diameter 116 mm. FK PEC June 2010


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PDF B2562* b25620 MKP and MKK power capacitor power electronic MKd 480 power capacitor epcos B25620B1147K981 B25620B1297K982 B25620B0757K881 MKd 480 power capacitor B25620b MKP power capacitor
2006 - programmer st10f273

Abstract:
Text: chips with the ST10 core. IRAM 2K 16 16 Watchdog XRTC PEC Oscillator 16 16 , GPT1/GPT2 XCAN2 10-bit ADC XRAM 16 2K ( PEC ) 16 XI2C 16 XCAN1 With the DSP-MAC , of 3.0µs 8-channel peripheral event controlled ( PEC ) interrupts 16 priority-levels, 56 interrupt , 64MHz (PQFP), 40MHz (LQFP), PEC , PWM, CAPCOM, MAC, EMI ST10F273Z4 · 512K 36K 24x10 , ), 40MHz (LQFP), PEC , PWM, CAPCOM, MAC, EMI ST10F272Z2 · 256K 20K 24x10-bit 5x16


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PDF 16-bit ST10F276 32kHz FLST10FAM0706 programmer st10f273 st10f168s PQFP144 programmer st10f272 ST10F273 ST10F269 5X16 ST10F273 programmer LQFP144 ST10F27X
2011 - RQJ0303PGDQALT

Abstract:
Text: the PEC fails to match then the command is ignored and the voltage register contents also will not , the rising edge of SCKI. PEC Byte: The packet error code ( PEC ) byte is a cyclic redundancy check , initial PEC value of 01000001 and the following characteristic polynomial: Data Transfers: Every byte , CSBI. x8 + x2 + x + 1 To calculate the 8-bit PEC value, a simple procedure can be established: 1. Initialize the PEC to 0100 0001. 2. For each bit DIN coming into the register group, set IN0 = DIN XOR PEC


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PDF LTC6803-2/LTC6803-4 ISO26262 LTC6803-1 LTC6803-3 LTC6802-2 LTC6803-2/LTC6803-4. LTC6803-2 LTC6803-1/ LTC6803-2/LTC6803-4, RQJ0303PGDQALT LTC6803-4 LTC6803G-4 LTC6803IG-4 LTC6802-2 LTC6803-2 LTC6803G-2 LTC6803
AP1628

Abstract:
Text: on CS# Lines after access with RDCS# and/or WRCS# - affects FAsteps only) BUS.18 ( PEC transfers , Watchdog Timer will reset the device upon an overflow. Interrupts and PEC transfers, however, can not be , incorrect if the following conditions are true at the same time: (1) the previous 'instruction' is a PEC , instruction immediately follows the previous instruction or PEC transfer within the instruction pipeline ('back-to-back' execution), i.e. decode phase of BFLDx and execute phase of the previous instruction or PEC


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PDF SAB-C161K-LM SAF-C161K-LM P-MQFP-80-1 C161K/C161O C161V/K/O C161K C161O/K C161PI upload/0/000/011/711/c161pi AP1628 SAB-C161K-LM P-MQFP-80-1 INFINEON PART MARKING ES IDCHIP FIX166 C166 instruction set C166 C161K SAF-C161K-LM
siemens C166 instruction set

Abstract:
Text: on CS# Lines after access with RDCS# and/or WRCS# - affects FAsteps only) BUS.18 ( PEC transfers , overflow. Interrupts and PEC transfers, however, can not be processed. In case NMI# is asserted low while , following conditions are true at the same time: (1) the previous 'instruction' is a PEC transfer which , follows the previous instruction or PEC transfer within the instruction pipeline ('back-to-back' execution), i.e. decode phase of BFLDx and execute phase of the previous instruction or PEC transfer


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PDF SAB-C165-LM, SAF-C165-LM, SAB-C165-L25M, -L25F SAF-C165-L25M, SAB-C165-LM3V, SAF-C165-LM3V, P-MQFP-100, P-TQFP-100 siemens C166 instruction set SAB-C165-L25M C165 CPU21 SAB-C165-LM SAB-C165-LM3V SAF-C165-L25M SAF-C165-LM SAF-C165-LM3V
1997 - AP1633

Abstract:
Text: Conversion-Time) by using the PEC and the 50ns Resolution on the CAPCOM-Unit Harald Lehmann / Siemens Cupertino , to be an (external) interrupt to trigger the PEC and transfer the ADC result (8 Bit from a Port) to , falling edge of CC3 channel. Now the timing of PEC transfer can be fine tuned by selecting the Capture channel for generating the PEC . Example: Have the interrupt request flag (IR) set at the beginning at , (<50ns @100nF Port-load) Q Signal definitely available! S "point of perfect timed PEC


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PDF AP1633 APXXXX01 800ns 100ns AP1633 450ns 150ns, 150ns
2011 - RQJ0303PGDQALT

Abstract:
Text: stay the same. If a start ADC conversion command is sent to the LTC6803 but the PEC fails to match then , command, data is latched in on the rising edge of CSBI. Network Layer PEC Byte: The packet error code ( PEC , order they are passed, using the initial PEC value of 01000001 and the following characteristic polynomial: x8 + x2 + x + 1 To calculate the 8-bit PEC value, a simple procedure can be established: 1. Initialize the PEC to 0100 0001. 2. For each bit DIN coming into the register group, set IN0 = DIN XOR PEC [7


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PDF ISO26262 44-Lead LTC6802 LTC6803 LTC6803-1 LTC6803-3 LTC6803-2/LTC6803-4. LTC6803-2 LTC6803-2/LTC6803-4, 680324fa RQJ0303PGDQALT LTC6803G-4 LTC6803G-2 LTC6803-4 pec 820 SCR POWER SUPPLY zener diode c5v c12V Zener Diode
CRC8

Abstract:
Text: Maxim > App Notes > DIGITAL POTENTIOMETERS Keywords: DS1862, CRC-8, CRC8, PEC Mar 20, 2006 , explains packet-error checking ( PEC ) as it applies to the DS1862 laser-control and digital-diagnostics IC , calculation examples, and a how-to guide on implementation specific to the DS1862. What Is PEC and How Does It Work? The DS1862 features a packet-error checking ( PEC ) mode ( PEC enable, 76h, bit 0, = 1 , enabling PEC , extra information is included in the data string during each read and/or write sequence


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PDF DS1862, DS1862 DS1862. com/an3749 DS1862: AN3749, APP3749, CRC8 CRC 8 AN3749 APP3749
infineon IOM2 application note

Abstract:
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEC , functionality of the Peripheral Event Controller ( PEC ) in the C166 core, allowed the size of the FIFOs , Controller ( PEC ) functionality of the C166 core is a perfect fit for a new interworking concept. 1.2.1 PEC Functionality The PEC provides service channels which move single bytes or words on interrupt , the fastest possible interrupt response. A PEC Channel is assigned by the interrupt priority. The


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PDF C165UTAH SAF-C165UTAH D-81541 infineon IOM2 application note C165UTAH C166 C166 INFINEON hdlc infineon IOM2 "application note"
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