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PCI9060-3A PLX Technology Bristol Electronics 4 - -
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PCI9060 datasheet (12)

Part Manufacturer Description Type PDF
PCI9060 Others 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original PDF
PCI9060 PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original PDF
PCI9060 PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original PDF
PCI9060ES Others 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original PDF
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original PDF
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original PDF
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Scan PDF
PCI9060SD Others 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original PDF
PCI9060SD PLX Technology PCI bus master interface chip Original PDF
PCI9060SD PLX Technology PCI Bus Master Interface Chip Original PDF
PCI9060SD PLX Technology PCI Bus Master Interface Chip for Master and Slave Adapters Scan PDF
PCI9060SD PLX Technology PCI Bus Master Interface Chip for Master and Slave Adapters Scan PDF

PCI9060 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1995 - 10B5

Abstract: 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960JX
Text: to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , the base address specified in the PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base


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PDF PCI9060 10B5 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960JX
1995 - 93CS46

Abstract: 0x00000018 E 32.0000 C 10B5 c code for pci master
Text: returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. , devices on the PCI bus using the direct master feature of the PCI9060. First the 68040 must arbitrate for , transitions to state C0 where ADS~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060. , PCI9060 /68040 AN July 1995 PCI9060 /68040 Application Note VERSION 1.0


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PDF PCI9060/68040 PCI9060 32-bit PCI9060, 16-bit 93CS46) 93CS46 0x00000018 E 32.0000 C 10B5 c code for pci master
1996 - i486 DX2

Abstract: SiS chipset 430FX 21052-AB intel pentium p5 micro i486 dx2 transistor P2P SiS chipset Pentium HP Vectra OLIVETTI
Text: cards were tried behind DEC 2.1 P2P bridge. PCI9060 (EB) and PCI9060ES (EB) passed the PCI SIG discard , ) PCI9060 (EB) was configured. DS, DM, and DMA transactions were performed. 2) PCI9060ES (EB) was , -AB bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, and DMA (Rev3 only , . PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, DMA (Rev3 only , Compatibility Test Report April 1996 Two evaluation boards with an I960 and PCI9060 Rev. 3, and another


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PDF 9060ES PCI9060 PCI9060ES 133MHz PCI9060 440FX i486 DX2 SiS chipset 430FX 21052-AB intel pentium p5 micro i486 dx2 transistor P2P SiS chipset Pentium HP Vectra OLIVETTI
1996 - 16V8H-15

Abstract: U0401 20-2136J PT3877 512 eeprom dip 32-pin 20V8H 1n4148 0805 16v8h IC 4020 HEADER 10X2
Text: PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address , - PLX TECHNOLOGY PCI9060 Demo Board 0x00000010 0-31 0 1 1-2 I/O MAP 06/16/96 3 , Reserved 0x00000038 0-31 Reserved - 2 - PLX TECHNOLOGY PCI9060 Demo Board 0x0000003C , sequentially in the EEPROM. Therefore, a 256-bit device can be used. - 3 - PLX TECHNOLOGY PCI9060 Demo , power of 2 (Default size = 1 Mbyte) - 4 - PLX Technology PCI9060 DEMO List of Materials 06


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PDF PCI9060 0x00000000 0x00000002 0x00000004 MCON8-12 MCON13-15 16V8H-15 U0401 20-2136J PT3877 512 eeprom dip 32-pin 20V8H 1n4148 0805 16v8h IC 4020 HEADER 10X2
1995 - 9060ES

Abstract: PCI9060ES PCI9060SD small endian AD-1508
Text: of the PCI9060ES. PCI bus parity checking and generation is independent of local bus parity checking , both a PCI bus Master and Target General Description _ The PCI9060ES provides a , . The PCI9060ES allows the i960® processors and other intelligent controllers to perform direct bus master transfers on the PCI bus. The PCI9060ES also enables the local processor to configure other PCI devices in the system, an important feature for embedded systems. The PCI9060ES supports both memory


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PDF 9060ES PCI9060ES PCI9060SD PCI9060ES 9060ES small endian AD-1508
Not Available

Abstract: No abstract text available
Text: bus writes, only the bytes specified by a PCI bus master or the PCI9060's DMA controller are written , is optional. The signals on the data parity pins do not effect operation of the PCI9060. PCI bus , SECTION 2 BUS OPERATION 2. SECTION 2 - BUS OPERATION 2.1 PCI BUS CYCLES The PCI9060 is PCI Compliant. 2.1.1 PCI Target Command Codes As a target, the PCI9060 allows access to the PCI9060 internal , the PCI9060 can be byte, word or long word accesses. All memory commands are aliased to the basic


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PDF PCI9060 PCI9060.
Not Available

Abstract: No abstract text available
Text: SECTION 1 GENERAL DESCRIPTION 1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION The PCI9060 is a , , multiplexed 80960 processor Cx, Hx Jx, Kx Sx The PCI9060 bus interface chip offers substantial performance , transfer large amounts of data to and from the adapter. The PCI9060 provides two independent bi-directional , . Using the PLX PCI9060 bus master chip also reduces total hardware and software development costs for disk controller, communication adapter and embedded system designs. The PCI9060 provides a single chip


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PDF PCI9060 PCI9060
Not Available

Abstract: No abstract text available
Text: PCI9060. Ground pins. Table 61 EEPROM Interface Pin Description Twal'Tifrtrt Number : ftii* SiMai;-.' , byte lanes on the local bus. Parity is checked for writes to the PCI9060 or reads by the PCI9060. Parity is generated for reads from the PCI9060 or writes by the PCI9060. When a channel is programmed , the bottom. Parity is checked for writes to the PCI9060 or reads by the PCI9060. Parity is checked for , tables describe the PCI9060 pins. The pins in the following tables are common to all three local bus


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PDF PCI9060 PCI9060: PCI9060, PCI9060
Not Available

Abstract: No abstract text available
Text: bytes specified by a PCI bus master or the PCI9060†™s DMA controller are written. An access to an 8 or , parity is optional. The signals on the data parity pins do not effect operation of the PCI9060. PCI bus , in the PCI9060†™s PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060†™s PCI Base Address for I/O Mapped , /from PCI host bus data transfers The PCI9060 provides a compact high performance PCI bus master


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PDF PCI9060 100Version 00Q07 PCI9060
1995 - 68040* part numbering

Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Text: , SRRDY~ is asserted in S0, causing READYI~ to be returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. During state S0, SRINC is true which allows the , direct master feature of the PCI9060. First the 68040 must arbitrate for the local bus by asserting BR~. , ~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local configuration registers , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060.


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PDF PCI9060/68040 PCI9060 32-bit PCI9060, 100ns 200ns 300ns 68040* part numbering 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
1995 - 10B5

Abstract: 93CS46
Text: returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. , devices on the PCI bus using the direct master feature of the PCI9060. First the 68040 must arbitrate for , transitions to state C0 where ADS~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060. , local bus priority to the PCI9060. "If the 68040 wants the bus, it waits until the PCI9060 "negates


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PDF PCI9060/68040 PCI9060 32-bit PCI9060, 100ns 200ns 300ns 10B5 93CS46
1995 - NM93CS46

Abstract: PCI9060ES PCI9060SD 10B5 9060ES 93CS56
Text: of the PCI9060ES. PCI bus parity checking and generation is independent of local bus parity checking , specified in the PCI9060ES's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060ES's PCI Base Address for I/O , both a PCI bus Master and Target General Description _ The PCI9060ES provides a , . The PCI9060ES allows the i960® processors and other intelligent controllers to perform direct bus


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PDF 9060ES 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns A31-29 NM93CS46 PCI9060ES PCI9060SD 10B5 9060ES 93CS56
PC19060

Abstract: EI96
Text: SECTION 8 TIMING DIAGRAMS 8. SECTION 8- TIMING DIAGRAMS The PCI9060 operates in three modes , . 78 Timing Diagram 2. PCI9060 Local bus Arbitration , #.79 Timing Diagram 5. (CX Mode) Local Bus Write to PCI9060 Configuration Register. 80 Timing Diagram 6. (CX Mode) Local Bus Read from PCI9060 Configuration Register , .86 Timing Diagram 13. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Enabled


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PDF PCI9060 PCI9060 PC19060 EI96
1995 - 10B5

Abstract: 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960 hx
Text: to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , the base address specified in the PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base


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PDF PCI9060 10B5 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960 hx
LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 NM93CS46 NM93CS06 I960CX 93C06
Text: specified by a PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus , parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation is independent , the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for Memory , the PCI9060's PCI Base Address for I/O Mapped Runtime Register. All PCI read or write accesses to the , Package General Description_ The PCI9060 provides a compact high performance PCI bus master interface


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PDF PCI9060 Q0007bl xi6-31 Page-100- 0Q007b2 PCI90S0 LA3101 PC19060 Igus LD-310 LDL8 pci9080 NM93CS46 NM93CS06 I960CX 93C06
1995 - I960CX

Abstract: I960 hx eeprom 1011 I960JX
Text: to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , The PCI9060 provides a compact high performance PCI bus master interface for adapter boards and , . The PCI9060 provides two independent bi-directional DMA channels with bi-directional FIFOs supporting


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PDF PCI9060 PCI9060 I960CX I960 hx eeprom 1011 I960JX
1996 - Asus P5

Abstract: 430FX i486 DX2 SiS chipset magma pxb-7 HP Vectra INTEL I486 DX2 X451 9060ES TRITON HX
Text: PCI9060 Rev. 3, and another with an I960 and PCI9060ES were checked on different systems. The test , performed. 3) Both cards were tried behind DEC 2.1 P2P bridge. PCI9060 (EB) and PCI9060ES (EB) passed the , Passed 1) PCI9060 (EB) was configured. DS, DM, and DMA transactions were performed. 2) PCI9060ES (EB , 21052-AB bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, and DMA , Intel P2P Moon Bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, DMA


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PDF 9060ES PCI9060 PCI9060ES 133MHz PCI9060 PCI9060ES 440FX Asus P5 430FX i486 DX2 SiS chipset magma pxb-7 HP Vectra INTEL I486 DX2 X451 9060ES TRITON HX
1995 - Not Available

Abstract: No abstract text available
Text: DMA Master Command Codes The PCI9060's DMA controllers can generate the following memory cycles , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results in , not effect operation of the PCI9060. PCI bus parity checking and generation is independent of local , PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for I/O Mapped Runtime Register


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PDF PCI9060 9060-SIL-ER-P0-1
doorbell application

Abstract: No abstract text available
Text: PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for I/O Mapped Runtime Register , the appropriate application specific action. It can then clear the abort bits in the PCI9060's PCI , applies only to direct ("pass through") master and slave accesses through the PCI9060. Deadlock will not , request that the external arbiter not grant the bus to any local bus master except the PCI9060. A status


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PDF PCI9060 doorbell application
1996 - 16V8H-15

Abstract: 20-2136J res 10k sip 16V8H-15 pc IC 4020 MSL-260-G-H pulse TRANSFORMER valor res 0402 ic 0808 data sheet 16v8h
Text: PLX Technology PCI9060 DEMO List of Materials 06/16/96 Description Qty Vendor Vendor Part Reference Designator PCB, PCI9060 DEMO,Rev A IC, PCI9060 ,PQFP IC,80960CA,33 MHz,PQFP IC,82596CA,33 MHz,PFQP IC,82C503,PLCC IC,16550A,PLCC IC,Static Ram, 32Kx8, 15 nsec, 28 Pin 300 Mil SOJ IC,Flash EPROM,256Kx8,90 nsec,DIP IC,EEPROM,256 Bit Serial,DIP 1 1 1 1 1 1 4 1 1 , J1001 DS0702 DS0301,0601,0701 RP1110,1111 RP1101-1109 -1- PLX Technology PCI9060 DEMO


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PDF PCI9060 80960CA 82596CA 82C503 6550A 32Kx8, 256Kx8 NS16550AV 16V8H-15 20-2136J res 10k sip 16V8H-15 pc IC 4020 MSL-260-G-H pulse TRANSFORMER valor res 0402 ic 0808 data sheet 16v8h
LA3101

Abstract: PC19060
Text: Power Supply Current 130 mA Version 1.2 Section B PCI9060 SECTION 7 PACKAGE SPECIFICATIONS LOCAL CLOCK y (MAX) X . _TVALID (MN) OUTPUTS VALID Figure 10. PCI9060 Local , #) can be as much as 25 ns Page - 70 Version 1.2 Section B PCI9060 SECTION 7 PACKAGE SPECIFICATIONS LOCAL CLOCK y T h OLD INPUTS Figure 10. PCI9060 Local Input Setup and Hold Waveform


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PDF PCI9060 PCI9060 LDf31 PC19060 LA3101 PC19060
1996 - resistor bank

Abstract: U0101 u0102
Text: |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH 7 8 ECN HISTORY PCI9060 , EEPROM DRAM , B B C C D D PLX TECHNOLOGY, MOUNTAIN VIEW, CA PCI9060 /DRAM DEMO SCHEMATICS Title Size B 1 2 3 4 5 6 Date: TITLE PAGE Document Number PCI9060 /DRAM DEMO Monday


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PDF U0101 PCI9060, 9060/DRAM U0102 20V8R resistor bank U0101 u0102
1996 - 68040

Abstract: I3 CPU I5 CPU DATASHEET PCI i/o schematics 80960CA U0101 PCI9060 68040 I11-I12
Text: |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH 7 8 ECN HISTORY PCI9060 , EEPROM , , MOUNTAIN VIEW, CA PCI9060 /68040 DEMO SCHEMATICS Title Size B 1 2 3 4 5 6 Date: TITLE PAGE Document Number PCI9060 /68040 DEMO Monday, July 22, 1996 7 Rev 1 Sheet 1 8


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PDF U0101 PCI9060, 80960CA U0102 20V8R 68040 I3 CPU I5 CPU DATASHEET PCI i/o schematics U0101 PCI9060 68040 I11-I12
1995 - MACH210A

Abstract: No abstract text available
Text: local bus arbiter, and controls "accesses from the 68040 to the PCI9060 configuration "registers, and direct master accesses to the PCI bus. "The arbiter gives local bus priority to the PCI9060. "If the 68040 wants the bus, it waits until the PCI9060 "negates its LHOLD request. Once the 68040 has been "granted the bus, the arbiter allows it to park on the "bus until the PCI9060 needs the bus again, or a , "the PCI9060. @page "pin assignments "INPUTS bclk pin 13; !reset !ts !tip r_w tt0 tt1


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PDF MACH210A' 0xc58e PCI9060 PCI9060. PCI9060 h00000000 h80000000 MACH210A
PC19060

Abstract: No abstract text available
Text: revision of the PCI9060. Yes Local Bus Current Rev # Page - 34 Version 1.2 Section B PCI9060 , versions of PCI9060 familv and to ensure comDatibilitv with future enhancement, all unused bits should be , Section B PCI9060 SECTION 4 REGISTERS LOCAL CONFIGURATION REGISTERS Local (Offset from chip select address) To ensure software comDatibilitv with other versions of PCI9060 family and to ensure , ) To ensure software comDatibilitv with other versions of PCI9060 family and to ensure comDatibilitv


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PDF PCI9060 PCI9060 PC19060
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