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Part Manufacturer Description Datasheet Download Buy Part
XC3130A-4PC44I Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 227MHz, CMOS, PQCC44, PLASTIC, LCC-44
XC3130A-3PC44C Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 270MHz, CMOS, PQCC44, PLASTIC, LCC-44
XC3130A-3PC84C Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 270MHz, CMOS, PQCC84, PLASTIC, LCC-84
XC3130A-4VQ64I Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 227MHz, CMOS, PQFP64, PLASTIC, VQFP-64
XC3130A-3VQ64C Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 270MHz, CMOS, PQFP64, PLASTIC, VQFP-64
XC3130A-4VQ64C Rochester Electronics LLC Field Programmable Gate Array, 100 CLBs, 1500 Gates, 227MHz, CMOS, PQFP64, PLASTIC, VQFP-64

P51-1500-S-A-D-4.5V-000-000 datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
P51-1500-S-A-D-4.5V-000-000 P51-1500-S-A-D-4.5V-000-000 ECAD Model SSI Technologies Pressure Sensors, Transducers, Sensors, Transducers, SENSOR 1500PSI 1/4-18NPT .5-4.5V Original PDF

P51-1500-S-A-D-4.5V-000-000 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
AC100

Abstract: HD61830 M6800
Text: =0°,=0° V 15.0 - - - - -35 -30 2.0 1500 150 3000 200 - - 5.0 4 , -08 6 SADL 08H 16 8 7 SADH 09H 16 8 HN SAD SAD +1 SAD + HN ­1 . SAD+HN SAD + HN +1 SAD +2HN­1 . · · · · · · · · · · · · SAD+MHN SAD + MHN +1 SAD+MHN­1 . SAD 16 12 SADH 4 SAD 12 21 LCD 8 CACL 0AH 16 8 9 CACH


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PDF EDM25664-01 96hrs AC100 HD61830 M6800
2001 - SB21150BC

Abstract: SB21150AC dc1111d GD21150BC SB21150 dc1030g SB21150-AC GD21150AC INTEL SB21150AC 21150BC
Text: 35 120 40 115 45 110 50 100 95 90 85 80 75 70 65 vss vdd s_ad <10> cfg<1> s_ad <9> vdd s_ad <8> s_cbe_l<0> vss s_ad <7> s_ad <6> vdd s_ad <5> s_ad <4> vss s_ad <3> s_ad <2> vdd s_ad <1> s_ad <0> vss s_vio trst_l tck tms vdd tdo tdi nc nc msk_in cfg<0 , > s_ad <31> vss s_ad <30> s_ad <29> vdd s_ad <28> s_ad <27> vss s_ad <26> s_ad <25> vdd s_ad <24> s_cbe_l<3> vss s_ad <23> s_ad <22> vdd s_ad <21> s_ad <20> vss s_ad <19> s_ad <18> vdd s_ad <17> s_ad


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PDF m66ena: SB21150BC SB21150AC dc1111d GD21150BC SB21150 dc1030g SB21150-AC GD21150AC INTEL SB21150AC 21150BC
2001 - SB21150BC

Abstract: SB21150AC GD21150BC dc1111d SB21150 DC1030G 74ls166 SB21150-AC 21150-AC GD21150AC
Text: 35 120 40 115 45 110 50 100 95 90 85 80 75 70 65 vss vdd s_ad <10> cfg<1> s_ad <9> vdd s_ad <8> s_cbe_l<0> vss s_ad <7> s_ad <6> vdd s_ad <5> s_ad <4> vss s_ad <3> s_ad <2> vdd s_ad <1> s_ad <0> vss s_vio trst_l tck tms vdd tdo tdi nc nc msk_in cfg<0 , > s_ad <31> vss s_ad <30> s_ad <29> vdd s_ad <28> s_ad <27> vss s_ad <26> s_ad <25> vdd s_ad <24> s_cbe_l<3> vss s_ad <23> s_ad <22> vdd s_ad <21> s_ad <20> vss s_ad <19> s_ad <18> vdd s_ad <17> s_ad


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PDF m66ena: SB21150BC SB21150AC GD21150BC dc1111d SB21150 DC1030G 74ls166 SB21150-AC 21150-AC GD21150AC
EDM240128-02

Abstract: HD61830 M6800
Text: - -35 -30 =0°,=0° 2.0 22.1 21.0 20.3 1500 150 3000 200 - - 5.0 23.0 V , VP CP VP EDM240128-02 6 SADL 08H 16 8 7 SADH 09H 16 8 HN SAD SAD +1 SAD + HN ­1 . SAD+HN SAD + HN +1 SAD +2HN­1 . · · · · · · · · · · · · SAD+MHN SAD + MHN +1 SAD+MHN­1 . SAD 16 12 SADH 4 SAD 8 CACL 0AH 16 8 12


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PDF EDM240128-02 96hrs EDM240128-02 HD61830 M6800
Not Available

Abstract: No abstract text available
Text: SAD | 5 20 | RWCK SASl 6 19 I FAM TASl 7 18 I RFSH Vccl 8 17 | RS/A , Data Input Write Enable T est Test Input cs Chip Select NC SAD No Connection , €” 1500 ns tOFF 0 50 0 50 ns 50 3 50 ns ns Access time Output , 3000 10000 1500 10000 ns SAS cycle time tssc 1 00 — 100 — ns , tRF — — 1500 10000 ns tRRP — — 500 — ns Fast mode cycle


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PDF MSM6389B_ MSM6389B 18-pin 1024-word
p714h

Abstract: p804h EDM160160-05 P650H SED1330 SED1335 TA 7217 AP SAD 512 HC-33/SED1330 p120h
Text: ,=0° - 22.0 - - =0°,=0° - - -35 -30 =0°,=0° 2.0 24.8 24.0 23.2 1500 150 , SAD2H SL2 00H~L/FH SL2+1 3SAD3SAD3L SAD3H 4. SAD4SAD4L SAD4H 5. SL3SL4 L/F 6. SL1SL2 SAD , SED1330 W/S=0FX=8FY=8 SAD C/R SAD SAD +1 SAD SAD + +AP AP+1 SAD + AP+2 1 8 SAD+A 9 P+C/R +2 SAD +C/R SAD SAD 16 17 1 SAD + 2AP 24 AP SAD+C/R SAD +1 SAD


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PDF EDM160160-05 96hrs p714h p804h EDM160160-05 P650H SED1330 SED1335 TA 7217 AP SAD 512 HC-33/SED1330 p120h
2000 - a7523

Abstract: 27832
Text: A20 A21 A22 A23 AA1 AA2 AA3 AA4 AA5 AA6 Signal Name s_req_l[4] s_req_l[3] s_req_l[1] s_ad [29] s_ad [27] s_ad [25] s_cbe_l[3] s_ad [22] s_ad [20] s_ad [16] s_frame_l s_devsel_l s_par s_ad [13] s_ad [10] s_m66ena s_cbe_l[0] s_ad [6] s_ad [3] s_ad [1] s_req64_l vdd s_cbe_l[6] p_ad[18] vss p_ad[17] vss vdd p_par Type I I I , s_ad [26] s_ad [24] s_idsel vss s_ad [18] vss vss s_trdy_l s_serr_l s_ad [14] s_ad [12] vdd s_ad [9] s_ad [7] s_ad [4] vdd vss vss vdd s_req_l[6] s_req_l[7] s_req_l[2] s_ad [31] s_ad [28] vss s_ad [23] s_ad [21] s_ad


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PDF 5M-1982 a7523 27832
EDM320240

Abstract: K/EDM320240 p714h FFH1 interface SAD 512 TA 7217 AP 00-EFH1-240 SED1335 P849H EDM320240-02
Text: - 25.0 - 1500 150 3000 200 - - 5.0 - V 1,2,5 - - 2000 200 mS 1,3,5 , /FH SL2+1 3SAD3SAD3L SAD3H 4. SAD4SAD4L SAD4H 5. SL3SL4 L/F 6. SL1SL2 SAD 1 W/S W , CRT C/R APFY FY AP SED1335 AP>C/R SED1335 W/S=0FX=8FY=8 SAD C/R SAD SAD SAD +1 SAD SAD + SAD + +AP AP+1 AP+2 8 SAD+A 9 P+C/R 1 +C/R +2 SAD 16 17 SAD + 2AP 1


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PDF EDM320240-02 EDM320240 K/EDM320240 p714h FFH1 interface SAD 512 TA 7217 AP 00-EFH1-240 SED1335 P849H EDM320240-02
2003 - CHEERTEK

Abstract: CT212 ct212s Serial Ports cheertek AVD18 CT-212S 4-pin 27mhz crystal MA487 7-seg display CHINA TV MEMORY RESET
Text: code of the external program memory. conveying type select input. LATS=0, mux with SAD [7:0]; LATS , port. SAD [7:0]: low byte address and In accesses to external memory, port0 outputs data bus , enable. It is used to latch the low byte address of SAD [7:0] as LATS=0. LATS I Low byte address conveying type select, input only. LATS=0, mux with SAD [7:0]; LATS=1, conveyed on SA[7:0]. SAD [7:0 , , input. When LATS=0, two options: one is SA[7:0] output of the low byte address latched from SAD [7:0


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PDF CT212 CHEERTEK CT212 ct212s Serial Ports cheertek AVD18 CT-212S 4-pin 27mhz crystal MA487 7-seg display CHINA TV MEMORY RESET
EDM240160-01

Abstract: SED1330 p714h AC110 SED1335 sram 6800 160X160 SCR 131- 6 W 49 LCm 320240
Text: - - - 15.0 - - - - - 15.0 - 1500 150 3000 200 - - 5.0 , SL2+1 3SAD3SAD3L SAD3H 4. SAD4SAD4L SAD4H 5. SL3SL4 L/F 6. SL1SL2 SAD 1 W/S W/S , CRT C/R APFY FY AP SED1335 AP>C/R SED1335 W/S=0FX=8FY=8 SAD C/R SAD SAD SAD +1 SAD SAD + SAD + +AP AP+1 AP+2 8 SAD+A 9 P+C/R 1 +C/R +2 SAD 16 17 SAD + 2AP 1


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PDF EDM240160-01 EDM240160-01 SED1330 p714h AC110 SED1335 sram 6800 160X160 SCR 131- 6 W 49 LCm 320240
"Pressure Transducers" p51 50

Abstract: 734-1104-ND MG-15-A-9V-R MG1-3000-A-9V-R P51-200-G-A-I36-5V-R P51-1000-A-A-I36-20MA-R 734-1004-ND 1/tef 6851 MG1-100-A-9V-R P51-100-G-A-I36-5V-R
Text: Gauge 5 15 50 75 100 200 300 500 750 1000 1500 2000 , 1500 2000 3000 5000 5 30 100 200 500 1000 3000 5000 30 100 , -1000-A-9V-R MG- 1500 -A-9V-R MG-2000-A-9V-R MG-3000-A-9V-R MG-5000-A-9V-R MG-100-A-9V-F-R MG-200-A-9V-F-R MG , -300-A-MD-R MG-500-A-MD-R MG-750-A-MD-R MG-1000-A-MD-R MG- 1500 -A-MD-R MG-2000-A-MD-R MG-3000-A-MD-R MG


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PDF MG-15-A-9V-R MG-50-A-9V-R MG-75-A-9V-R MG-100-A-9V-R MG-200-A-9V-R MG-300-A-9V-R MG-500-A-9V-R MG-750-A-9V-R MG-1000-A-9V-R MG-1500-A-9V-R "Pressure Transducers" p51 50 734-1104-ND MG-15-A-9V-R MG1-3000-A-9V-R P51-200-G-A-I36-5V-R P51-1000-A-A-I36-20MA-R 734-1004-ND 1/tef 6851 MG1-100-A-9V-R P51-100-G-A-I36-5V-R
2001 - a7835

Abstract: pci non-transparent bridge AA10 AA13 AA15 AA17
Text: ] TS A4 s_ad [29] TS AA10 p_ad[5] TS A5 s_ad [27] TS AA11 vss P A6 s_ad [25] TS AA12 vdd P A7 s_cbe_l[3] TS AA13 vss P A8 s_ad [22] TS AA14 p_cbe_l[7] TS A9 s_ad [20] TS AA15 p_cbe_l[4] TS A10 s_ad [16 , STS AA18 p_ad[54] TS A13 s_par TS AA19 vss P A14 s_ad [13] TS AA20 vdd P A15 s_ad [10] TS AA21 p_ad[46] TS A16 s_m66ena I AA22


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PDF 5M-1982 a7835 pci non-transparent bridge AA10 AA13 AA15 AA17
1998 - MSM6388

Abstract: MSM6389 MSM6588 MSM6597A MSM6597A-XXX SSOP30
Text: tRDC 2500 ns tACC 1500 ns tOFF 0 200 ns RDCK tRDP 1000 ns RDCK tRD 1500 ns 4/9 CS2 (I) AX0 SADX (I) AX1 AX2 , TEST RESET MSM6588 RD WR CE MIN + VDD VDD SAD SAS TAS RWCK WE DIN DOUT SADX SASX TAS RDCK MSM6389 SAD SAS TAS RWCK WE DI/O D3 D2 D1 D0 AU/D TEST TEST


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PDF J2D0040-38-Z1 MSM6597A-XXX MSM6597A-XXX MSM6597AMSM6597TAT MSM6597A1 MSM6597A1 X1024Y1024 MSM6597ALSI MSM6597AMSM6388MSM6588 MSM6597AMSM6597 MSM6388 MSM6389 MSM6588 MSM6597A SSOP30
1998 - MSM6388

Abstract: MSM6389 MSM6588 MSM6597A MSM6597A-XXX SSOP30
Text: tRDC 2500 ns tACC 1500 ns tOFF 0 200 ns RDCK tRDP 1000 ns RDCK tRD 1500 ns 4/9 CS2 (I) AX0 SADX (I) AX1 AX2 , TEST RESET MSM6588 RD WR CE MIN + VDD VDD SAD SAS TAS RWCK WE DIN DOUT SADX SASX TAS RDCK MSM6389 SAD SAS TAS RWCK WE DI/O D3 D2 D1 D0 AU/D TEST TEST


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PDF J2D0040-38-Z1 MSM6597A-XXX MSM6597A-XXX MSM6597AMSM6597TAT MSM6597A1 MSM6597A1 X1024Y1024 MSM6597ALSI MSM6597AMSM6388MSM6588 MSM6597AMSM6597 MSM6388 MSM6389 MSM6588 MSM6597A SSOP30
1998 - DIP18

Abstract: MSM6388 MSM6389 MSM6588 MSM6595 MSM6595A MSM6595A-XXX R290 SSOP30
Text: tRDC 2500 ns tACC 1500 ns tOFF 0 200 ns RDCK tRDP 1000 ns RDCK tRD 1500 ns 5/12 AX2 AX3 AX4 AX5 AX6 AX7 , GND 1M MSM6389 RD WR CE VDD VDD SAD SAS TAS RWCK WE DIN DOUT MSM6389 MCU SAD SAS TAS RWCK WE DI/O CS GND VDD SADX SASX TAS RDCK DOUT SASY SADY TEST


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PDF J2D0038-38-Z0 MSM6595A-XXX MSM6595A-XXX MSM6595AMSM6595TAT MSM6595A1 MSM6595A1 X1024Y1024 MSM6595ALSI MSM6595AMSM6388MSM6588 MSM6595AMSM6595 DIP18 MSM6388 MSM6389 MSM6588 MSM6595 MSM6595A R290 SSOP30
1998 - DIP18

Abstract: MSM6388 MSM6389 MSM6588 MSM6596A MSM6596A-XXX R290 SSOP30 DIP18-P-300-2
Text: 1500 ns tOFF 0 RDCK tRDP 1000 200 ns ns RDCK tRD 1500 , TEST TEST TEST TEST MSM6588 RD WR CE VDD VDD SAD SAS TAS RWCK WE DIN DOUT MSM6389 MCU SAD SAS TAS RWCK WE DI/O CS GND VDD SADX SASX TAS RDCK DOUT SASY


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PDF J2D0039-38-Z0 MSM6596A-XXX MSM6596A-XXX MSM6596AMSM6596TAT MSM6596A1 MSM6596A1 X1024Y1024 MSM6596ALSI MSM6596AMSM6388MSM6588 MSM6596AMSM6596 DIP18 MSM6388 MSM6389 MSM6588 MSM6596A R290 SSOP30 DIP18-P-300-2
1998 - DIP18

Abstract: SSOP30 R290 MSM6595A-XXX MSM6595A MSM6595 MSM6588 MSM6389 MSM6388 cs415
Text: tRDC 2500 ns tACC 1500 ns tOFF 0 200 ns RDCK tRDP 1000 ns RDCK tRD 1500 ns 5/12 AX2 AX3 AX4 AX5 AX6 AX7 , GND 1M MSM6389 RD WR CE VDD VDD SAD SAS TAS RWCK WE DIN DOUT MSM6389 MCU SAD SAS TAS RWCK WE DI/O CS GND VDD SADX SASX TAS RDCK DOUT SASY SADY TEST


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PDF J2D0038-38-Z0 MSM6595A-XXX MSM6595A-XXX MSM6595AMSM6595TAT MSM6595A1 MSM6595A1 X1024Y1024 MSM6595ALSI MSM6595AMSM6388MSM6588 MSM6595AMSM6595 DIP18 SSOP30 R290 MSM6595A MSM6595 MSM6588 MSM6389 MSM6388 cs415
1998 - DIP18

Abstract: MSM6388 MSM6389 MSM6588 MSM6596A MSM6596A-XXX R290 SSOP30
Text: ns tRDC 2500 ns tACC 1500 ns tOFF 0 RDCK tRDP 1000 200 ns ns RDCK tRD 1500 ns 5/12 AX1 AX2 AX3 AX4 , TEST TEST TEST TEST MSM6588 RD WR CE VDD VDD SAD SAS TAS RWCK WE DIN DOUT MSM6389 MCU SAD SAS TAS RWCK WE DI/O CS GND VDD SADX SASX TAS RDCK DOUT SASY


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PDF J2D0039-38-Z0 MSM6596A-XXX MSM6596A-XXX MSM6596AMSM6596TAT MSM6596A1 MSM6596A1 X1024Y1024 MSM6596ALSI MSM6596AMSM6388MSM6588 MSM6596AMSM6596 DIP18 MSM6388 MSM6389 MSM6588 MSM6596A R290 SSOP30
Not Available

Abstract: No abstract text available
Text: address/data bus, and s_ad is secondary interface address/data bus. 1.4.6 SSGNAME# PCI signals that , Bus Interface Signais (Sheet 1 of 2) S ig n a l Nam e T ype D e s c rip tio n s_ad [31:0 , s_ad [31:0], During the data phases of a transaction, the initiator drives write data, or the target drives read data, on s_ad [31:0], When the secondary PCI bus is idle, the 21554 drives s_ad to a valid , transaction, assertion of s j r d y j indicates that valid write data is being driven on the s_ad bus. During


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PDF intellig-332-2717
1998 - AA10

Abstract: AA13 AA15 AA17 21554
Text: secondary bus signal. For example, p_ad is primary interface address/data bus, and s_ad is secondary , of 2) Signal Name Type Description s_ad [31:0] TS Secondary PCI interface address/data , transaction, the initiator drives a physical address on s_ad [31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data, on s_ad [31:0]. When the secondary PCI bus is idle, the 21554 drives s_ad to a valid logic level when its secondary bus grant is


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2001 - Intel 21555

Abstract: 21555AB FW21555BB Intel 21555 user manual CLS4 -C20 278320 278321 21554 fw21555ba FW21555AB
Text: s_req_l[4] s_req_l[3] s_req_l[1] s_ad [29] s_ad [27] s_ad [25] s_cbe_l[3] s_ad [22] s_ad [20] s_ad [16] s_frame_l s_devsel_l s_par s_ad [13] s_ad [10] s_m66ena s_cbe_l[0] s_ad [6] s_ad [3] s_ad [1] s_req64_l vdd , C15 C16 C17 Signal Name vdd s_ad [26] s_ad [24] s_idsel vss s_ad [18] vss vss s_trdy_l s_serr_l s_ad [14] s_ad [12] vdd s_ad [9] s_ad [7] s_ad [4] vdd vss vss vdd s_req_l[6] s_req_l[7] s_req_l[2] s_ad [31] s_ad [28] vss s_ad [23] s_ad [21] s_ad [17] vdd s_irdy_l s_stop_l s_perr_l s_ad [15] vdd vss vss Type P TS TS I P TS


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2003 - HB1-SE66

Abstract: B40 C 1000 8841 PCI6152-33PC HB1-SE PCI 6152-CC33PC HB1-SE33 hint hb1-se33p Intel 21152 schematic hb1-se33p C08-C09
Text: S_DEVSEL_L S_STOP_L S_AD [31:0] S_CBE[3:0] S_PAR S_REQ_L[3:0] S_GNT_L[3:0] S_RST_L S_SERR_L S_PERR_L , S_AD [31:0] PTS Secondary Address/Data: Multiplexed address and data bus. Address is indicated by , S_TRDY_L are asserted. During bus idle, PCI 6152 drives S_AD to a valid logic level when the S_GNT_L is , : Parity is even across S_AD [31:0], S_CBE[3:0], and S_PAR (i.e. an even number of `1's). S_PAR is an input , . Signal S_PAR is three-stated one cycle after the S_AD lines are three-stated. During bus idle, PCI 6152


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2000 - HB1-SE33

Abstract: HB1-SE66 hint hb1-se33p HB1-SE 0220H hint HB1 hint hb1-se hb1-se33p Intel 21152 schematic 21152 PCI-to-PCI Bridge Hardware Implementation
Text: S_STOP_L S_AD [31:0] S_CBE[3:0] S_PAR S_REQ_L[3:0] S_GNT_L[3:0] S_RST_L S_SERR_L S_PERR_L S_CLKRUN , Description S_AD [31:0] PTS Secondary Address/Data: Multiplexed address and data bus. Address is , and S_TRDY_L are asserted. During bus idle, HB1-SE drives S_AD to a valid logic level when the , Parity: Parity is even across S_AD [31:0], S_CBE[3:0], and S_PAR (i.e. an even number of `1's). S_PAR is , asserted. Signal S_PAR is tristated one cycle after the S_AD lines are tristated. During bus idle, HB1-SE


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PDF 7923A HB1-SE33 HB1-SE66 hint hb1-se33p HB1-SE 0220H hint HB1 hint hb1-se hb1-se33p Intel 21152 schematic 21152 PCI-to-PCI Bridge Hardware Implementation
1997 - 21554 PCI-to-PCI Bridge

Abstract: AA10 AA13 AA15 21554
Text: , p_ad is the primary interface address/data bus, and s_ad is the secondary interface address/data bus , Driving s_ad , s_cbe_l, and s_par during reset Asserting s_req64_l during reset IEEE Standard 1149.1 , Interface Signals (Sheet 1 of 5) Signal Name Description s_ad [31:0] TS Secondary PCI , phase or phases of a transaction, the initiator drives a physical address on s_ad [31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data, on s_ad


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1998 - AA10

Abstract: AA13 AA15 21554 PCI-to-PCI Bridge CSR BC4 CSR BC4 rom 21554
Text: , p_ad is the primary interface address/data bus, and s_ad is the secondary interface address/data bus , · Driving s_ad , s_cbe_l, and s_par during reset Asserting s_req64_l during reset IEEE , s_ad [31:0] TS Secondary PCI interface address/data. These signals are a 32-bit multiplexed , physical address on s_ad [31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data, on s_ad [31:0]. When the secondary PCI bus is idle, the 21554 drives


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PDF R93JA AA10 AA13 AA15 21554 PCI-to-PCI Bridge CSR BC4 CSR BC4 rom 21554
Supplyframe Tracking Pixel