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Part Manufacturer Description Datasheet Download Buy Part
ADS1000A1IDBVR Texas Instruments 12-Bit, 128SPS, 1-Ch Delta-Sigma ADC w/ PGA, Oscillator & I2C 6-SOT-23 -40 to 125
SN74AS1000ANSR Texas Instruments Quadruple 2-Input Positive-NAND Buffers/Drivers 14-SO 0 to 70
ADS1000A1IDBVTG4 Texas Instruments 12-Bit, 128SPS, 1-Ch Delta-Sigma ADC w/ PGA, Oscillator & I2C 6-SOT-23 -40 to 125
SNJ54AS1000AJ Texas Instruments Quadruple 2-Input Positive-NAND Buffers/Drivers 14-CDIP -55 to 125
SN74AS1000ADG4 Texas Instruments Quadruple 2-Input Positive-NAND Buffers/Drivers 14-SOIC 0 to 70
SNJ54AS1000AW Texas Instruments Quadruple 2-Input Positive-NAND Buffers/Drivers 14-CFP -55 to 125

P51-1000-A-I-P-4.5V-000-000 datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
P51-1000-A-I-P-4.5V-000-000 P51-1000-A-I-P-4.5V-000-000 ECAD Model SSI Technologies Pressure Sensors, Transducers, Sensors, Transducers, SENSOR 1000PSI 7/16-20UNF 4.5V Original PDF

P51-1000-A-I-P-4.5V-000-000 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
53C1010

Abstract: 1BL20 SYM53C1010 SYM53C1010-33 53C101 SYM53C1010-66 SYM53C896
Text: indicate it detected an error. 2.4 Asynchronous Information Protection ( AIP ) The Asynchronous Information Protection ( AIP ) feature provides error checking for asynchronous, non-data phases through BCH , ". The AIP error status and the live AIP code values are captured in the AIPCNTL1 register for debug purposes. AIP checking and generation is enabled by setting bit 6 in the SCNTL4 register. The sequence ID , writing the RSQAIP bit in the AIPCNTL0 register. The AIP sequence value can be read via the SEQAIP bit


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PDF SYM53C1010-33 SYM53C896 S11009 SYM53C1010-33 SYM53C896. SYM53C896 53C1010 1BL20 SYM53C1010 53C101 SYM53C1010-66
1993 - MSP58C80

Abstract: No abstract text available
Text: PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 , positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the , CONVERTER SPSS015B ­ DECEMBER 1993 ­ REVISED JULY 1996 functional block diagram ADCLK PWAD AIP AIM , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this , operating conditions. AIP is a positive differential input for the ADC. AIP and AIM together form a balanced


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PDF MSP58C20 SPSS015B 024-MHz spss015b MSP58C20DW MSP58C20DWR MSP58C80
2013 - Not Available

Abstract: No abstract text available
Text: -25 to +85 °C IP-Protection IP 40 Front Side mechanical,  IP 67 Front Side Contact Area, IP 40 / IP 67 , IP 67 /  IP 40 ;IP 40 MSM 19  ST  1241.6621.1110000 19 5 / 3  A 125 / 250  VAC non-illuminated Stainless Steel ,no IP 67 /  IP 40 ;IP 40 MSM 19  ST  1241.6621.1120000 19 10  A 250  VAC non-illuminated Stainless Steel ,no IP 67 /  IP 40 ;IP 40 MSM 19  ST  1241.6621.1130000 19 6  A 250  VAC non-illuminated Stainless Steel ,no IP 67 /  IP 40 ;IP


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PDF com/pg70
uPD71054

Abstract: PD71054 KFA81
Text: AIP -8d Analogue Input Board User Manual AIP -8d User Manual Document Part N° Document Reference Document Issue Level 127-145 AIP -8d\.\127_145.DOC 1.1 Manual covers PCBs identified AIP -8d Rev.C All rights reserved. No part of this publication may be reproduced, stored in any , . Filename was .\User_g.doc Introduction Page 4 Introduction Thank you for purchasing the AIP , chapter covers a different aspect of using the AIP -8d. In order to get the best results from the product


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8250 16550 UART

Abstract: serial port 8250 16450 UARTs interface device ide port
Text: intei ÂIQWÂKfêS 82091AA ADVANCED INTEGRATED PERIPHERAL ( AIP ) I Floppy Disk Controller , Powerup Configuration The AIP is 100% Compatible with EISA, ISA and AT Host Interface Features - 8 , ECP The 82091AA Advanced Integrated Peripheral ( AIP ) is an integrated I/O solution containing a , performance, the AIP contains six 16-byte FIFOstwo for each serial port, one for the parallel port, and one for the floppy disk controller. The AIP also includes power management and 3.3V capability for power


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PDF 82091AA 82077SL 16-bit 82091AA 16-byte 8250 16550 UART serial port 8250 16450 UARTs interface device ide port
2004 - "read channel" hdd lsi

Abstract: No abstract text available
Text: EOC DO[11] (MSB) AIP SAH AIN 4 BIT MDAC 3 BIT MDAC 3 BIT MDAC 3 BIT MDAC DO[10 , without any notice. SAMSUNG ELECTRONICS Co. LTD 12BIT 40MSPS ADC CORE PIN NAME AIP AIN PD SU[1:0 , Substrate Bias CORE CONFIGURATION AVDD33A AVSS33A AVBB33A RPA RNA RPD RND CML IT AIP AIN CK PD SU[1] SU , Storage Temperature Range ADC1387X RATINGS Symbol AVDD33A AVDD33D AIP / AIN CK VOH, VOL Tstg , AVSS33A AVDD33D - AVSS33D AVDD33A - AVDD33D RP RN AIP / AIN Tpwh Tpwl VIL VIH Topr NOTES 1. It is


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PDF 12BIT 40MSPS ADC1387X 12-bit ADC1387X "read channel" hdd lsi
2002 - samsung dvd power supply circuit diagram

Abstract: ADC1298X AIP Systems STC 12
Text: AVBB33D DO[0] (LSB) AIP 3 BIT MDAC 3 BIT MDAC SAH AIN 3 BIT MDAC DO[1] DO[2] DO[3 , PIN DESCRIPTION AIP AI phiar50_abb Analog Input (RB ~ RT) AIN AI phiar50_abb Analog , ] CML DO[2] IT DO[3] AIP adc1298x AIN CK DO[4] DO[5] DO[6] DO[7] STBY DO , Supply Voltage AVDD33A AVDD33D -0.3 to 4.5 V Analog Input Voltage AIP / AIN -0.3 to , AVDD33A - AVDD33D -0.1 0.0 0.1 V RT RB AVSS33A 2.15 1.15 AVDD33A - V AIP


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PDF 10BIT 30MSPS ADC1298X ADC1298X 10-bit 10Bit 30MSPS samsung dvd power supply circuit diagram AIP Systems STC 12
2013 - Not Available

Abstract: No abstract text available
Text: -25 to +85 °C IP-Protection IP 40 Front Side mechanical,  IP 67 Front Side Contact Area, IP 40 / IP 67 , IP 67 /  IP 40 ;IP 40 MSM 30  ST  1241.6661.1110000 30 5 / 3  A 125 / 250  VAC non-illuminated Stainless Steel ,no IP 67 /  IP 40 ;IP 40 MSM 30  ST  1241.6661.1120000 IP 67 /  IP 40 ;IP 40 30 10  A 250  VAC non-illuminated Stainless Steel ,no MSM , /  IP 40 ;IP 40 MSM 30  RI  red 1241.6664.1111000 30 100  mA 30  VDC Ring


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PDF com/pg70
PC MOTHERBOARD CIRCUIT diagram of LG computers

Abstract: AD585 AIP-24 H300 H301 H302 lm35 to 1-5 volts
Text: AIP -24 24 Channel Analogue Input Board User Manual AIP -24 User Manual Document Part N , AIP -24 Rev F All rights reserved. No part of this publication may be reproduced, stored in any , . 11 5.0 COMMERCIAL DATA ACQUISITION PACKAGES . 13 5.1 Use of the AIP -24 Board , 0-10, -5 to +5 or-10 to +10 volts. The AIP board may be thought of as s number of functional blocks , must occupy the same address. 2.2 Port Map In order to use the AIP card a channel must be


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PDF AIP-24 AIP-24 PC MOTHERBOARD CIRCUIT diagram of LG computers AD585 H300 H301 H302 lm35 to 1-5 volts
1993 - MS-013

Abstract: MSP58C20
Text: Consumption Mode DW PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 , maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones. The , AUDIO-BAND CONVERTER SPSS015B ­ DECEMBER 1993 ­ REVISED JULY 1996 functional block diagram ADCLK AIP , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 SPSS015B 024-MHz MS-013 MSP58C20
2003 - ADC1298X

Abstract: 4-bit flash adc 3bit flash adc
Text: AVSS33D AVDD33D AVBB33A AVSS33A AVDD33A FUNCTIONAL BLOCK DIAGRAM DO[0] (LSB) AIP 3 , Description AIP AI phiar50_abb Analog Input (RB ~ RT) AIN AI phiar50_abb Analog Input , ] (LSB) RT RB CML IT AIP DO[1] DO[2] DO[3] DO[4] adc1298x DO[5] DO[6] AIN CK , Supply Voltage AVDD33A AVDD33D -0.3 to 4.5 V Analog Input Voltage AIP / AIN -0.3 to , AVDD33A ­ V AIP /AIN RB ­ RT V Tpwh ­ ­ 16.6 16.6 ­ ­ ns ­ 3.0


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PDF ADC1298X 10-BIT 30MSPS ADC1298X 10-bit 30MSPS AVDD33D 4-bit flash adc 3bit flash adc
1993 - MS-013

Abstract: MSP58C20
Text: Consumption Mode DW PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 , maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones. The , AUDIO-BAND CONVERTER SPSS015B ­ DECEMBER 1993 ­ REVISED JULY 1996 functional block diagram ADCLK AIP , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 SPSS015B 024-MHz MS-013 MSP58C20
1993 - MS-013

Abstract: MSP58C20 MSP58C8
Text: Consumption Mode DW PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 , maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones. The , DECEMBER 1993 ­ REVISED MAY 1995 functional block diagram ADCLK AIP AIM PWAD Antialiasing , input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 SPSS015A 024-MHz MS-013 MSP58C20 MSP58C8
1993 - MS-013

Abstract: MSP58C20
Text: Consumption Mode DW PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 , maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones. The , AUDIO-BAND CONVERTER SPSS015B ­ DECEMBER 1993 ­ REVISED JULY 1996 functional block diagram ADCLK AIP , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 SPSS015B 024-MHz MS-013 MSP58C20
uPD71054

Abstract: PD71054
Text: AIP -8d 8 Channel Analogue Input Board User Manual AIP -8d User Manual Document Part N° Document Reference Document Issue Level 127-1004.doc AIP -8d\.\127-1004.doc 2.0 Manual covers PCBs identified AIP -8d Rev. C All rights reserved. No part of this publication may be reproduced, stored in , .3 Installing the AIP , Connection to the AIP -8d .8 Analogue Connector (25


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uPD71054

Abstract: PD71054 8259 programmable interval timer
Text: AIP -8d 8 Channel Analogue Input Board User Manual AIP -8d User Manual Document Part N° Document Reference Document Issue Level 0127-1004.doc AIP -8d\.\0127-1004.doc 2.0 Manual covers PCBs identified AIP -8d Rev. C All rights reserved. No part of this publication may be reproduced , Installing the AIP -8d. 3 Base Address , Connection to the AIP -8d . 8 Analogue Connector (25


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Not Available

Abstract: No abstract text available
Text: NC 1 l~ V Ss 1 -1 - AIP UJZ AIM 1 1 pw ad pw da ADOUT Nc Nc nn. nnz nsz nnz nnz NC , input voltage (i.e., a maximum positive voltage difference of A IP -A IM ) is applied at the AIP and AIM , sam pled at 1.024 MHz. AIM is a negative differential input for the ADC. AIP and AIM together form a , , external com m on-m ode bias should satisfy recom m ended operating conditions. AIP is a positive differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 024-MHz
2012 - Not Available

Abstract: No abstract text available
Text: .-0.3V to +4V AOP, AON, AIP , AIN, OVDD, AIN0–AIN13, CNVST/AIN14, REF+, REF-/AIN15 to GND , 1000 ns 0.16 Aperture Delay 16 MHz 8 Aperture Jitter 30 RMS ns ps , clocked, fSCLK = 16MHz, 16 cycles (Note 8) ns µs 1000 ns 0.16 fSCLK Aperture Delay , MAX11321 toc10 MAX11321 toc09 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN THD vs. INPUT RESISTANCE 73 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN fSAMPLE = 1Msps fIN = 100kHz


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PDF MAX11321â MAX11328 10-/12-Bit, 4-/8-/16-Channel MAX11328 12-/10-bit 500kHz,
2012 - MAX11321

Abstract: No abstract text available
Text: 0 500 AOP SHORTED TO AIP AON SHORTED TO AIN -85 fSAMPLE = 1Msps fIN = 100kHz -90 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 500 1000 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN , , AON, AIP , AIN, OVDD, AIN0­AIN13, CNVST/AIN14, REF+, REF-/AIN15 to GND , 0.1 Q1.5 V FA V RMS tCONV fSCLK Externally clocked, fSCLK = 16MHz, 16 cycles (Note 8) 1000 0.16 8 30 , clocked, fSAMPLE = 1Msps, (Note 8) Externally clocked, fSCLK = 16MHz, 16 cycles (Note 8) 1000 0.16 8 RMS


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PDF MAX11321 MAX11328 10-/12-Bit, 4-/8-/16-Channel 12-/10-bit 500kHz,
1993 - Not Available

Abstract: No abstract text available
Text: VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 , positive voltage difference of AIP - AIM) is applied at the AIP and AIM inputs, the resulting code at the , functional block diagram ADCLK PWAD AIP AIM Antialiasing Filter 1.024 MHz Analog , is a negative differential input for the ADC. AIP and AIM together form a balanced differential input , should satisfy recommended operating conditions. AIP is a positive differential input for the ADC. AIP


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PDF SPSS015B MSP58C20 024-MHz
1993 - Not Available

Abstract: No abstract text available
Text: Voltage Generation Very Low Power Consumption Mode VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC , When a maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP − AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones , diagram ADCLK AIP AIM Antialiasing Filter PWAD Analog Sigma-Delta 2 Modulator 1.024 , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this


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PDF MSP58C20 SPSS015B 024-MHz
ASX-1000

Abstract: xylan Elan SRB Nortel HDX ATM SYSTEM PROJECT- modules C1000 C100 NORTEL 6440 asn router Catalyst Enterprises
Text: installed from Fore Systems and Cisco, composed of one ASX- 1000 core switch and a Cisco router with an AIP , cost of bid was $300,000 or less Already had full-time on-site support ES-3810/3850 ATM ASX- 1000 ASX- 1000 ES-AV0000000 12 ES-AYSL24001 7-12 Fore's approach was to update software and add , administer/spare/ train T Contrasted ARE to Cisco's slower AIP ES-AV0000000 13 ES-AYSL24001 7-13 , 10/100 dge s for desktops Cis 1000 shared w co rou s to b i ches Stressed resiliencyeof


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PDF ES-AYSL24001 ES-AV0000000 V0000000 ASX-1000 xylan Elan SRB Nortel HDX ATM SYSTEM PROJECT- modules C1000 C100 NORTEL 6440 asn router Catalyst Enterprises
FP10SH

Abstract: VF-6e amv j D30TC ag qm LM100 LM300 LM-100 G120 FP-10SH
Text: I P O M20 AIP I P O M30 AIP , I P O D40TH AID AIP VF6E VF6 , AFP I P O B01 M01 D01 AIB AIP AID


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PDF LM200 LM300 FP10SH VF-6e amv j D30TC ag qm LM100 LM300 LM-100 G120 FP-10SH
2013 - Not Available

Abstract: No abstract text available
Text: bis +100 °C) IP 68 /  IP 69K proTect+ Reflexions-Lichtschranke Kontrastsensor FNDR , €‰/  IP 69K proTect+ Rotlicht Rotlicht Rotlicht Weisslicht Rotlicht Nennschalt , Temperaturzyklen die Schutzarten IP 68 /  IP 69K erfüllen. Langzeitdicht Temperaturschocktest in Wasser und , SmartReflect FNDH Umgebungstemperatur  40 … +80 °C (kurzzeitig bis +100 °C) IP 68 /  IP 69K , Lichtquelle Erstklassiges Dichtigkeitskonzept IP 68 /  IP 69K proTect+ Rotlicht Rotlicht


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PDF CH-8501
1993 - Not Available

Abstract: No abstract text available
Text: PACKAGE (TOP VIEW) VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 , positive voltage difference of AIP ­ AIM) is applied at the AIP and AIM inputs, the resulting code at the , CONVERTER SPSS015B ­ DECEMBER 1993 ­ REVISED JULY 1996 functional block diagram ADCLK PWAD AIP AIM , differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this , operating conditions. AIP is a positive differential input for the ADC. AIP and AIM together form a balanced


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PDF MSP58C20 SPSS015B 024-MHz
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