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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
V62/03622-01XE V62/03622-01XE ECAD Model Texas Instruments Enhanced Product Ieee 1394-1995 And P1394A Compliant General Purpose Link-Layer Controller 100-LQFP -40 to 105
TSB12LV32TPZEP TSB12LV32TPZEP ECAD Model Texas Instruments Enhanced Product Ieee 1394-1995 And P1394A Compliant General Purpose Link-Layer Controller 100-LQFP -40 to 105
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GoldX
GP1394AA-15 15 ft IEEE 1394 Firewire Cable 6 Pin to 6 Pin GoldX; Connector Type A:USB A Plug; Connector Type B:USB A Plug; Cable Length - Imperial:15ft; Cable Length - Metric:4.57m; Jacket Color:Black; Product Range:-
GP1394AA-15 ECAD Model
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Newark GP1394AA-15 Bulk 0 1 - - - - - More Info
Farnell GP1394AA-15 Each 0 2 Weeks, 6 Days 1 £11.14 £9.42 £9.42 £9.42 £9.42 More Info
JDI Technologies Inc
GP1394AB-06 GOLDX IEEE-1394 FIREWIRE CABLES, LENGTH: 6 FEET, CONNECTORS: 6 PIN TO 4 PIN, SHIELDING: FOIL AND BRAID, APPLICATION: PC TO A/V, CONNECTOR PLATING: GOLD
GP1394AB-06 ECAD Model
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Newark GP1394AB-06 Bulk 0 1 - - - - - More Info

P1394a Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - S400

Abstract: S100 S200 P1394a
Text: begins by providing a brief summary of the protocol enhancements in P1394a. It then goes on to explain , improvement translates into greater throughput for P1394a. This is especially good for disk drives, but also , . This feature is also a part of the power management features proposed for P1394a. Power Management , Protocol Enhancements In P1394a And Why They Are Important For 1394 Devices In A PC Environment Rev 1.0 A White Paper By Bill Pearson Intel Corporation January 15, 1998 P1394a Protocol


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PDF P1394a S400 S100 S200
D72852

Abstract: IC D016 P1394 uPD72850A uPD72851 uPD72852
Text: 45 46 47 48 Fig. 2 µPD72851 Pin Configuration The standardization of P1394a , an update of the , new standard, P1394a Draft 5.0, and support transfer speeds of 100 Mbps, 200 Mbps, and 400 Mbps , product. 4. Interoperability and P1394a Draft 5.0 The µPD72851 and µPD72852, which were developed in compliance with P1394a Draft 5.0, are upwardly compatible with both the µPD72850A, which was developed in compliance with P1394a Draft 2.1, and physical layer LSIs incorporated in existing systems. Through


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PDF IEEE1394 PD72851/ PD72852 IEEE1394 P1394a D72850 80QFP D72850A D72852 IC D016 P1394 uPD72850A uPD72851 uPD72852
1998 - 9 pin connector 1394

Abstract: IEEE 1394 cable S100-400 IEEE 1394 cable 4 to 4 IEEE standards intel microsoft MMC-2 mobile 4 pin battery connector P1394 S100
Text: specified in IEEE P1394.a and the proposed enhancements in IEEE P1394.b are well suited to multistreaming , IEEE 1394 standards, specifically IEEE 1394-1995 and IEEE P1394.a · Support for the 1394 Open Host , support mandatory features in IEEE P1394.a with backward compatibility with IEEE 1394-1995 Required , supplemental specifications: · IEEE 1394-1995 standard · IEEE P1394.a , an amendment to IEEE 1394-1995 · IEEE , . OpenHCI controllers and devices support advances defined in IEEE P1394.a Required The advances in the


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PDF 100-Mb/sec, 200-Mb/sec, 400-Mb/sec P1394 1394-enabled 9 pin connector 1394 IEEE 1394 cable S100-400 IEEE 1394 cable 4 to 4 IEEE standards intel microsoft MMC-2 mobile 4 pin battery connector S100
1997 - 1A16

Abstract: S100 EIA-364-B
Text: P1394a Draft 2.0 March 15, 1998 P1394a Draft Standard for a High Performance Serial Bus , of voting members of the IEEE P1394a working group at the time of publication. Peter Johansson , list of other major participants in the IEEE P1394a working group (those that attended at least 3 , .149 vi This is an unapproved standards draft, subject to change © 1997, 1998 IEEE P1394a , 1 High Performance Serial Bus (Supplement) P1394a Draft 2.0 March 15, 1998 IEEE Std


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PDF P1394a P1394a 32-bit 64-bit 1A16 S100 EIA-364-B
2000 - CS4103

Abstract: CS4103VHG CS4210 IS100 CS4301
Text: GeodeTM CS4103 IEEE P1394a Physical Layer Device General Description The National Semiconductor , to revision 2.0 of the P1394a specification. The device is a three port implementation of a reusable , , (usually referred to as 100, 200, and 400 Mbit/sec respectively). The CS4103 supports all of the P1394a , updated in the P1394a specification for direct connection with the Geode CS4210 IEEE 1394 Open Host , PHY-Link interface compliant with 1394-1995 and P1394a specifications The CS4103 generates the


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PDF CS4103 P1394a CS4103 CS4103VHG CS4210 IS100 CS4301
2000 - PWR74

Abstract: No abstract text available
Text: GeodeTM CS4103 IEEE P1394a Physical Layer Device July 2000 GeodeTM CS4103 IEEE P1394a , Mbit/sec IEEE 1394 Physical Layer (PHY) device. The CS4103 complies to revision 2.0 of the P1394a , ports. The CS4103 supports all of the P1394a enhancements including connection debounce, arbitrated , defined in IEEE specification 1394-1995 and updated in the P1394a specification for direct connection with , CS4103 can receive and respond to all the PHY packet types defined in revision 2.0 of the P1394a


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PDF CS4103 P1394a CS4103VHG PWR74
2000 - uPD72862

Abstract: uPD72862GC-9EU
Text: µPD72862 IEEE1394 IEEE1394a OHCI-LINK ASSP Product Letter Description The µPD72862 is NEC's OHCI-LINK layer controller compliant with P1394a specification draft 2.0. It supports the connection to standard IEEE1394-1995/ P1394a PHY layer implementation with transmission speeds up to 400Mbps , Interface specification release 1.0 Compliant with protocol enhancement as defined in P1394a draft 2.0 , isochronous transmit DMAs and 4 isochronous receive DMAs IEEE1394-1995 compliant PHY and P1394a compliant PHY


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PDF PD72862 IEEE1394 IEEE1394a PD72862 P1394a IEEE1394-1995/P1394a 400Mbps. S15071EE1V0PL00 uPD72862 uPD72862GC-9EU
1999 - Not Available

Abstract: No abstract text available
Text: FEATURES AND SPECIFICATIONS Features and Benefits s Sizes 4 circuit to 4 circuit IEEE P1394a cable assembly s Offered in three standard lengths s Uses S100 cable for speeds up to 100 Mbs (contact Inside Sales for S400 cable) s Full metal shielding for ESD protection s Detent feature provides grounding and secure Reference Information Packaging: Bag Mates With: 54030 PCB socket Designed In: Millimeters to +85°C 0.80mm (.031") Pitch IEEE P1394a Shielded I/O Cable Assembly Plug 59233 4-4 Pin


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PDF P1394a
2006 - TSB12LV23

Abstract: TSB12LV21 TSB12LV22 TSB12LV31 TSB12LV41 TSB12LV42 TSB41LV03A TSB41LV03AI TSB41LV03PFP
Text: Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus1 and the P1394a , Compliant With OpenHCI Requirements Provides Three P1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s) Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset , Active Control Bit and P1394a Features Data Interface to Link-Layer Controller Through 2/4/8 Parallel , Std 1394-1995 and in the P1394a Supplement section 5.9.4) (hereafter referred to as Annex J type


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PDF TSB41LV03A TSB41LV03AI SLLA225 1394a P1394a TSB12LV23 TSB12LV21 TSB12LV22 TSB12LV31 TSB12LV41 TSB12LV42 TSB41LV03A TSB41LV03AI TSB41LV03PFP
2000 - Not Available

Abstract: No abstract text available
Text: CS4103 Geode CS4103 IEEE P1394a Physical Layer Device Literature Number: SNOS922A GeodeTM CS4103 IEEE P1394a Physical Layer Device July 2000 GeodeTM CS4103 IEEE P1394a Physical Layer Device , Physical Layer (PHY) device. The CS4103 complies to revision 2.0 of the P1394a specification. The device is , supports all of the P1394a enhancements including connection debounce, arbitrated reset, ack-accelerated , 1394-1995 and updated in the P1394a specification for direct connection with the Geode CS4210 IEEE 1394 Open


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PDF CS4103 CS4103 P1394a SNOS922A
2001 - MD8405E

Abstract: uPD72850B uPD72850BGK-9EU S400
Text: µPD72850B IEEE1394 IEEE1394a PHY Layer ASSP Product Letter Description The µPD72850B is NEC's three-port implementation of the PHY layer compliant with P1394a standard draft 2.0. Featuring the IEEE1394 speed range up to S400, it offers application- specific chip implementation of a , PHY layer LSI compliant to IEEE P1394a draft 2.0 Connection debounce Fly-by concatenation , /Resume function as defined in P1394a draft 2.1 24.576 MHz crystal clock generation, 393.216 MHz PLL


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PDF PD72850B IEEE1394 IEEE1394a PD72850B P1394a IEEE1394 PD72850BGK-9EU S15070EE2V0PL00 MD8405E uPD72850B uPD72850BGK-9EU S400
1999 - Not Available

Abstract: No abstract text available
Text: FEATURES AND SPECIFICATIONS Features and Benefits s Sizes 6 circuit IEEE 1394-1995 to 4 circuit IEEE P1394a cable assembly s Offered in three standard lengths s Uses S100 cable for speeds up to 100 Mbs (contact Reference Information Packaging: Bag Mates With: 53462, 53460, 53984 and 54030 PCB sockets Designed In: Millimeters Inside Sales for S400 cable) s Full metal shielding for ESD , IEEE 1394-1995 & IEEE P1394a Shielded I/O Cable Assembly Plug 59233 6-4 Pin Harness mating


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PDF P1394a P1394a
1998 - TSB11C01

Abstract: S100 S1600 S200 S800 TSB11LV01 TSB21LV03 TSB21LV03A SLLA019
Text: . 8 Goals of IEEE P1394a Supplement (Draft 1.1 , physical layers from Texas Instruments (TIä ) support the many features added by the P1394a Supplement , on IEEE STD 13941995 buses. This document describes the goals of the P1394a Supplement, the features , Supported by TI TSB41LV0x Physical Layer Devices SLLA019 Goals of IEEE P1394a Supplement (Draft 1.1) One of the primary goals of IEEE P1394a Supplement was to ensure interoperability between 1394a


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PDF 1394a TSB41LV0x SLLA019 non-1394a P1394a TSB11C01 S100 S1600 S200 S800 TSB11LV01 TSB21LV03 TSB21LV03A SLLA019
2001 - FW801

Abstract: No abstract text available
Text: Product Brief, Rev. 2 June 2001 FW801 PHY IEEE * 1394A One-Cable Transceiver/Arbiter Device Distinguishing Features I I I I I I I I I Compliant with IEEE P1394a Draft 2.0 Standard for a High Performance Serial Bus (Supplement) Supports extended BIAS_HANDSHAKE time for enhanced , IEEE 13941995 and IEEE P1394a network. The cable port incorporates two differential line transceivers , P1394a Draft 2.0 standard. See Table 1 for the address space of the Pwr_class register. Table 1. PHY


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PDF FW801 P1394a PB01-110CMPR-2 PB01-110CMPR-1)
1999 - S100

Abstract: TSB12LV01A TSB12LV21 TSB12LV22 TSB12LV23 TSB12LV31 TSB12LV41 TSB12LV42 TSB41LV01
Text: 4.2.2.2 in IEEE P1394A. 10 mV ms TPA, TPB cable inputs, S400 operation Receive input skew , accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware reset and is unaffected , Serial Bus and the P1394a Supplement Fully Interoperable With FireWireTM and i.LINKTM Implementation of IEEE Std 1394 Fully Compliant With OpenHCI Requirements Provides One P1394a Fully Compliant Cable Port at 100/200/400 Megabits per Second (Mbits/s) Full P1394a Support Includes: Connection Debounce


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PDF TSB41LV01 SLLS365 P1394a S100 TSB12LV01A TSB12LV21 TSB12LV22 TSB12LV23 TSB12LV31 TSB12LV41 TSB12LV42 TSB41LV01
molex connector catalog

Abstract: S100 S400 Molex 59233 IEEE grounding
Text: FEATURES AND SPECIFICATIONS Features and Benefits s Sizes 6 circuit IEEE 1394-1995 to 4 circuit IEEE P1394a cable assembly s Offered in three standard lengths s Uses S100 cable for speeds up to 100 Mbps (contact Reference Information Packaging: Bag Mates With: 53462, 53460, 53984, 54030, 54515 and 54516 PCB sockets Designed In: Millimeters Molex for S400 cable) s Full metal shielding , 0.80mm (.031") Pitch IEEE 1394-1995 & IEEE P1394a Shielded I/O Cable Assembly Plug 59233 6-4 Pin


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PDF P1394a molex connector catalog S100 S400 Molex 59233 IEEE grounding
molex connector catalog

Abstract: S100 S400 Molex 59233
Text: 0.80mm (.031") Pitch IEEE P1394a Shielded I/O Cable Assembly Plug FEATURES AND SPECIFICATIONS Features and Benefits s Sizes 4 circuit to 4 circuit IEEE P1394a cable assembly s Offered in three standard lengths s Uses S100 cable for speeds up to 100 Mbps (contact Molex for S400 cable) s Full metal shielding for ESD protection s Detent feature provides grounding and secure mating retention Reference Information Packaging: Bag Mates With: 54030, 54515 and 54516 PCB sockets Designed In: Millimeters 59233


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PDF P1394a P1394a molex connector catalog S100 S400 Molex 59233
2006 - TSB12LV23

Abstract: No abstract text available
Text: Bus1 and the P1394a Supplement Fully Interoperable With FireWire™ and i.LINK™ Implementation of IEEE Std 1394 Fully Compliant With OpenHCI Requirements Provides Three P1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s) Full P1394a Support Includes: Connection Debounce , Contender Bit, Power Class bits, Link Active Control Bit and P1394a Features Data Interface to Link-Layer , barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement section 5.9.4


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PDF TSB41LV03A TSB41LV03AI SLLA225 1394a P1394a TSB12LV23
2000 - FW1394C00

Abstract: No abstract text available
Text: Interface !" Compliant with IEEE1394-1995 and IEEE P1394a Draft Version 2.0 protocols Supports Serial Data Transfer Rates: 100, 200, and 400 Mbps Supports P1394a ACK-Acceleration Arbitration and Fly-by , of 100, 200, and 400 Mbps, it is 100% compatible with the IEEE1394-1995 and P1394a specifications


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PDF FW1394C00 IEEE1394 IEEE1394-1995 P1394a FW1394C00
2001 - D2631

Abstract: No abstract text available
Text: Product Brief, Rev. 1 May 2001 FW801 PHY IEEE * 1394A-2000 One-Cable Transceiver/Arbiter Device Distinguishing Features Compliant with IEEE P1394a Draft 2.0 Standard for a High Performance Serial Bus (Supplement) I Supports extended BIAS_HANDSHAKE time for enhanced interoperability with , implement a one-port node in a cable-based IEEE 13941995 and IEEE P1394a network. The cable port , LLC using the PHY Register Map Figure 6-1 of the IEEE P1394a Draft 2.0 standard. See Table 1 for the


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PDF FW801 394A-2000 P1394a PB01-110CMPR-1 PN99-059CMPR-1) D2631
2001 - LQFP-176

Abstract: P1394 S100 S200 S400
Text: Product Profile MB86617 Mai 2001 Edition 1.00 IEEE1394 Serial Bus Controller for DTV FME/MM/PP/0501 OVERVIEW The MB86617 is Fujitsu's IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394-1995) and P1394.a Standard Draft (rev.2.0). This MB86617 has three ports for network under the 1394 cable environment, differential transceiver, and comparator, and the , · · Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft


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PDF MB86617 IEEE1394 FME/MM/PP/0501 MB86617 P1394 LQFP-176 S100 S200 S400
MD8408B

Abstract: MD8408 S100 S200 S400 IEEE-P1394A
Text: IEEE Std 1394-1995 Standard for a High Performance Serial Bus IEEE P1394a Draft Ver3.0 Standard for a , .37 Figure 5-10 IEEE P1394a Draft Ver3.0 Isolation barrier (an example , to support the transfer speed of 400/200/100Mbit/sec., conforming to IEEE P1394a Draft Ver3.0. It , differential transceiver conforming to IEEE P1394a Draft Ver3.0. - Used to support the data rates of 393.216 , conforming to P1394a Draft Ver3.0. - A port connection state machine conforming to P1394a Draft Ver3.0. -


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PDF MD8408B 16-bit 32-bit 64-bit MD8408B MD8408 S100 S200 S400 IEEE-P1394A
1995 - vlit 1240

Abstract: 1S400 MD8405E uPD72850 uPD72850A uPD72850AGK-9EU S100 N1 545 27 009 00 S1445
Text: MOS MOS Integrated Circuit µPD72850A IEEE1394 400Mbps PHY PD72850A P1394a draft 2.0 3 LSI PD72850A 400 Mbps PD72850A PD72850 PD72850 P1394a draft 2.0 3 LSI 1. Connection , Link layer) 393.216/196.608/98.304 Mbps P1394a Draft 2.1 3.3 V Link 24.576 MHz 393.216 MHz PLL CPS IEEE std 1394 LinkFireWireTM, i.LINKTM 3 GND 80 TQFP P1394a Draft , September 2000 NS CP(K) 1999 µPD72850A PD72850 PD72850A PD72850A PD72850 PD72850 P1394a draft


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PDF PD72850A IEEE1394 400Mbps PD72850A P1394a PD72850 PD72850 vlit 1240 1S400 MD8405E uPD72850 uPD72850A uPD72850AGK-9EU S100 N1 545 27 009 00 S1445
1998 - Not Available

Abstract: No abstract text available
Text: P1394a D2.0 proposal s S100, S200 and S400 speeds s IEEE P1394a proposal PHY-LINK interface s IEEE P1394a proposal Suspend/Resume s OHCI support s Per port disable s Automatic power saving s Optional isolation support s IEEE P1394a proposal arbitration enhancements s IEEE P1394a proposal register set , s Repeaters 16 March 1998 The information in this datasheet is subject to change P1394a Link , to the IEEE 1394-1995 Annex J with 2 control lines and an 8 bit data bus, as modified by the P1394a


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PDF SBPH400-3 IEEE1394 400Mbps P1394a P1394a
1999 - Not Available

Abstract: No abstract text available
Text: = 25°C. For a node that does not source power; see Section 4.2.2.2 in IEEE P1394A. ± 0.5 ns , differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware , Standard for High Performance Serial Bus and the P1394a Supplement Fully Interoperable With FireWireTM , One P1394a Fully Compliant Cable Port at 100/200/400 Megabits per Second (Mbits/s) Full P1394a , Contender Bit, Power Class bits, Link Active Control Bit and P1394a Features Data Interface to Link-Layer


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PDF TSB41LV01 SLLS365A P1394a
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