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Part Manufacturer Description Datasheet Download Buy Part
LTC2255CUH Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: 0°C to 70°C
LTC2255IUH Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
LTC2255IUH#TR Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
LTC2255IUH#PBF Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
LTC2255CUH#PBF Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: 0°C to 70°C
LTC2255IUH#TRPBF Linear Technology LTC2255 - 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C

OPB 2255 Datasheets Context Search

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OPB 2255

Abstract:
Text: 27E I ) OPTEK TECHNOLOGY INC ■L,7iaSflO 0000=14^ 3 M OPTEK Product Bulletin OPB86O July 1989 Replaces January 1988 Slotted Optical Switches -p m -i3 . Types OPB 86O , 20mA PART NUMBER GUIDE OPB 8 X X X X X Aperture Width in Front of Sensor 5 = .050” 1 =0.10" , OPB 86O Series, QPB870 Series < 0 OPTEK Package Configuration N Package Configuration T MCHDED , 025(0 64} en ljrU| 015(0 36) W ,0 M 225.5 721 na .325(8 2 61 215(54® 315(300) NOTES 1 ANO 5


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PDF OPB86O OPB87Q OPB 2255 OPB-8870
2006 - OPB 2255

Abstract:
Text: 0 OPB PCI Full Bridge (v1.02a) DS437 January 25, 2006 0 Product Specification 0 Introduction LogiCORETM Facts The OPB PCI Full Bridge design provides full bridge functionality between the Xilinx 32-bit OPB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI) bus. The bridge is referred to as the OPB PCI Bridge in this document. The Xilinx OPB is a 32-bit bus subset of the IBM OPB described in the 64-Bit On-Chip Peripheral Bus Architecture Specification


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PDF DS437 32-bit 32-bit 64-Bit OPB 2255 IPIF PCI32 G89 DATASHEET G106 G105 G104-G106 G104 G103 G102
Not Available

Abstract:
Text: OPB Arbiter Core, 4 masters C27E303_OPB_ARB and OPBARB4M High performance core for highly integrated Core+ASIC systems Highlights The on-chip peripheral bus ( OPB ) arbiter is an internal core designed for on-chip peripheral bus arbitration. The OPB arbiter is a byte-wide slave device for configuration of the on-chip peripheral bus. Its address in the OPB memory map is determined by hardwiring , significant bits (MSB) of the OPB address bus are compared to this value during valid OPB transfer cycles


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PDF C27E303 SA14-2579-01
2002 - DS437

Abstract:
Text: 0 OPB IPIF/LogiCore V3 PCI Core Bridge DS437 (v1.2) July 30, 2002 Summary 0 This document provides the design specification for the bridge between the OPB IPIF and the LogiCORE PCI64 , Product Specification 0 v1.00a The OPB IPIF/LogiCORE PCI64 v3.0 bridge design described in this document bridges between the OPB IPIF (On-Chip Peripheral Bus Intellectual Property InterFace) and the , OPB and a 32-bit V2.2 compliant PCI (Peripheral Component Interconnect) bus. This bridge will is


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PDF DS437 PCI64 32-bit 32bit 64-Bit DS437 0X00 REQ64
2004 - chipscope manual

Abstract:
Text: 0 Chipscope OPB IBA DS282 (v2.5.1) Jan 16, 2004 0 0 Product Overview Introduction LogiCORETM Facts The Chipscope OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect On-Chip Peripheral Bus ( OPB ). The Chipscope OPB IBA core in EDK is based on Tcl script that generates a HDL wrapper to the OPB IBA and calls the Chipscope Core , Slices N/A N/A The Match Units for the OPB IBA are LUTs N/A N/A - OPB Control


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PDF DS282 chipscope manual ChipScope DS282
2005 - XC5VLX220-FF1760

Abstract:
Text: 0 OPB to DCR Bridge (v1.00b) DS442 April 24, 2009 0 Product Specification 0 Introduction LogiCORETM IP Facts The OPB to DCR Bridge translates transactions received on its OPB slave , to abstract OPB transactions into a simple SRAM style protocol that is easier to design with. The , within the various OPB masters and slaves. The main advantage of using the bridge, instead of the CPU , clock frequency than the CPU, its timing requirements are also less stringent. The OPB to DCR Bridge


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PDF DS442 XC5VLX220-FF1760 xc5vlx220ff1760-2 XC4VLX200-FF1513-10 xc4vlx200ff1513
OPB32PLB3

Abstract:
Text: 64-bit OPB to PLB Bridge Core C27E318_PLB_OPB_BR and OPB32PLB3 High performance core for highly integrated Core+ASIC systems Highlights The 64-bit OPB to PLB bridge core enables transfers of data between the onchip peripheral bus ( OPB ) and the processor local bus (PLB) under the direction of OPB master devices. The OPB to PLB bridge is a slave on the OPB and a master on the PLB. The OPB to PLB bridge core is required for any application using the OPB master devices that access system resources


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PDF 64-bit C27E318 OPB32PLB3 SA14-2585-01 OPB32PLB3
2005 - DS401

Abstract:
Text: 0 On-Chip Peripheral Bus V2.0 with OPB Arbiter (v1.10c) DS401 December 2, 2005 0 0 , OPB Arbiter (OPB_V20) module is used as the OPB interconnect for Xilinx FPGA based embedded processor systems. The bus interconnect in the OPB V2.0 specification is a distributed multiplexer , parameterized OPB Arbiter · Includes parameterized I/O signals to support up to 16 masters and any number of slaves. Xilinx recommends a maximum of 16 slaves on the OPB . Min Max Slices 46 410


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PDF DS401 64-Bit 32-Bit CR209288 CR208644
2005 - DS401

Abstract:
Text: 0 OPB Arbiter (v1.02e) DS469 September 23, 2005 0 Product Specification 0 Introduction LogiCORETM Facts The On-Chip Peripheral Bus ( OPB ) Arbiter design described in this document , authoritative specification. Any differences between the IBM OPB Arbiter implementation and the Xilinx OPB , .02e Resources Used Min The Xilinx OPB Arbiter design allows the user to tailor the OPB Arbiter to suit a , these parameters may cause the Xilinx OPB Arbiter design to deviate slightly from the IBM OPB Arbiter


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PDF DS469 32-bit 64-Bit DS401 QPro Family
IBM Processor Local Bus PLB 64-Bit Architecture

Abstract:
Text: 64-bit PLB to OPB Bridge Core C12E319_PLB_OPB_BR High performance core for highly integrated Core+ASIC systems Highlights The processor local bus (PLB) to onchip peripheral bus ( OPB ) bridge is a soft core which enables transfers of data between the PLB and OPB under the direction of PLB master devices. The bridge is a slave on the PLB and a master on the OPB . The bridge is necessary in any system implementation with OPB slave devices, which must be accessed by the processor. .


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PDF 64-bit C12E319 SA14-2581-00 IBM Processor Local Bus PLB 64-Bit Architecture
1996 - bus arbitration protocol

Abstract:
Text: IBM OPB Bus, until otherwise indicated in new versions or application notes. The following paragraph , . . . . . . . . . . . 13 Chapter 1. OPB Overview . . . . . . . . . . . . . . . . . . . . . . . . . , . OPB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . 8 OPB_pendReqn ( OPB Pending Master Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 OPB_busLock, Mn_busLock( OPB Bus Arbitration Lock) . . . . . . . . . . . . . . . .


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PDF SA-14-2528-02 bus arbitration protocol M2-10 NC27709 SA-14-2528-02
2005 - uart16550

Abstract:
Text: 0 OPB 16550 UART (v1.00d) DS430 December 2, 2005 0 Product Specification 0 Introduction LogiCORETM Facts This document provides the specification for the OPB 16550 UART (Universal Asynchronous Receiver/Transmitter) Intellectual Property (IP). Core Specifics The OPB 16550 UART , the OPB 16550 UART Point Design implementation are highlighted and explained in Specification , Specification www.xilinx.com 1 OPB 16550 UART (v1.00d) Functional Description The OPB 16550 UART


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PDF DS430 PC16550D com/pf/PC/PC16550D CR202609; uart16550 16550 uart national 16550 uart UART-16550 16550 Cr2026 16550 uart timing diagram 17256 XILINX National Semiconductor PC16550D UART UART DESIGN
2004 - 000000A5

Abstract:
Text: 0 OPB Synchronous DRAM (SDRAM) Controller (v1.00e) DS426July 21, 2005 0 0 Product Specification Introduction LogiCORETM Facts The Xilinx OPB SDRAM Controller provides a SDRAM Controller that connects to the OPB and provides the control interface for SDRAMs. It is assumed that the reader , , Virtex-II Pro, Virtex-4 Features The OPB SDRAM Controller is a soft IP core designed for Xilinx FPGAs and contains the following features: · OPB interface · Performs auto-refresh cycles ·


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PDF DS426July CR204161. CR208644. 000000A5 sdram controller SDRAM baa0 DRAM controller memory FPGA Spartan-IITM 200 vhdl code for DCM XAPP132
2005 - ds lite

Abstract:
Text: 0 OPB to OPB Bridge (Lite Version) (v1.00a) DS475 December 2, 2005 0 Product , the OPB to OPB Lite Bridge. The OPB to OPB Lite Bridge is used to connect two OPB buses. The bridge , between two OPB V2.0 buses Min Max 21 26 LUTs 22 30 FFs 27 27 · Requires the two OPB buses to be on the same clock and the same size Block RAMs 0 0 · No support , widths · Simple transaction forwarding reduces LUT count The top level block diagram for the OPB to


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PDF DS475 DS254 ds lite ModelSim spartan-3E
2005 - flash memory controller using xilinx vhdl code

Abstract:
Text: 0 OPB SYSACE (System ACE) Interface Controller (v1.00c) DS453 December 2, 2005 Product Specification 0 0 Introduction The OPB System ACE Interface Controller is the interface between the OPB , module attaches to the OPB (On-chip Peripheral Bus). LogiCORETM Facts Core Specifics Supported , Resources Used · OPB v2.0 bus interface with byte-enable support · Used in conjunction with System ACE , Specification www.xilinx.com 1 OPB SYSACE (System ACE) Interface Controller (v1.00c) Functional


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PDF DS453 CR193674: CR206050; flash memory controller using xilinx vhdl code vhdl code for memory controller ACE FLASH DS423 SPARTAN 6
2005 - priority arbiter list dynamic

Abstract:
Text: IBM Title Page 32-Bit OPB Arbiter Core Databook SA15-5821-01 Revision 1 March 9, 2007 , Core Databook 32-Bit OPB Arbiter Table of Contents Contents Preface , . 3.1.1 OPB Arbiter Priority Register . 3.1.2 OPB Arbiter Control Register . 3.1.3 OPB Arbiter Revision ID Register


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PDF 32-Bit SA15-5821-01 64-bit 16-bit priority arbiter list dynamic dynamic parking guidelines IBM ASIC Products Databook SA15-5821-01
2006 - VLYNQ

Abstract:
Text: signaling at up to 100 MHz Documentation · OPB bus signaling on user-side Design File Formats · , OPB Bus Signaling on User-side. The standard OPB bus interface is used on the user interface, which , commands. The VLYNQ core has two interfaces: · An OPB bus interface for the user side · The VLYNQ serial interface When the user masters transactions on the OPB bus to the VLYNQ OPB slave interface, they are , decoded, stored into the OPB Slave Read Return FIFO, and returned to the user on the VLYNQ OPB Slave


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PDF DS324 VLYNQ 00FF RX 3E vlynq vhdl
2006 - 3S1500

Abstract:
Text: System: MCH OPB EMC with OPB Central DMA Author: Sundararajan Ananthakrishnan This application note demonstrates the use of the Multi-CHannel (MCH) On Chip Peripheral Bus ( OPB ) External Memory Controller (EMC) in a MicroBlazeTM processor system. The MCH ports of the MCH OPB EMC connect to the cache ports of the MicroBlaze processor to allow efficient cacheline accesses by the processor. The OPB Central DMA controller is also included in this system to illustrate the capability of the MCH OPB EMC to handle


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PDF XAPP923 UG081, DS500, 3S1500 emc core for MCH microblaze application note P160 X923 XAPP923 XAPP932
PLB3OPB32

Abstract:
Text: 64-bit PLB to OPB Bridge Core C27E319_PLB_OPB_BR and PLB3OPB32 High performance core for highly integrated Core+ASIC systems Highlights The processor local bus (PLB) to onchip peripheral bus ( OPB ) bridge is a soft core which enables transfers of data between the PLB and OPB under the direction of PLB master devices. The bridge is a slave on the PLB and a master on the OPB . The bridge is necessary in any system implementation with OPB slave devices, which must be accessed by the processor. Two


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PDF 64-bit C27E319 PLB3OPB32 SA14-2582-01 PLB3OPB32
2005 - VHDL code for dac

Abstract:
Text: 0 OPB Delta-Sigma DAC (v1.01a) DS487 December 1, 2005 0 Product Specification 0 , 16 entry deep data FIFO · 32 bit OPB slave interface v1.01a Min Max I/Os 80 92 , , 2005 Product Specification www.xilinx.com 1 OPB Delta-Sigma DAC (v1.01a) Functional , of the OPB Delta-Sigma DAC. The width of the binary input in the implementation described below is , December 1, 2005 Product Specification OPB Delta-Sigma DAC (v1.01a) The Delta Adder calculates the


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PDF DS487 XAPP154 VHDL code for dac vhdl code for spartan 6 audio 12 bit DAC VHDL CODE IPIF XAPP155 DAC spartan 3 XAPP130 adc DAC FPGA Spartan3E
IBM Processor Local Bus PLB 64-Bit Architecture

Abstract:
Text: 128-bit PLB to OPB Bridge Core C27E502_PLB_OPB_128BR and PLB4OPB32 High performance core for , ( OPB ) bridge is a soft core which enables transfers of data between the PLB and OPB under the direction of PLB master devices. The bridge is a slave on the PLB and a master on the OPB . The bridge is necessary in any system implementation with OPB slave devices, which must be accessed by the processor , single quadword buffer, two doubleword buffers, or four word buffers, (most anticipated PLB to OPB


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PDF 128-bit C27E502 128BR PLB4OPB32 is128-bit SA14-2583-01 IBM Processor Local Bus PLB 64-Bit Architecture PLB4OPB32
2004 - DS404

Abstract:
Text: 0 OPB to PLB Bridge (v1.00c) DS404 April 24, 2009 0 0 Product Specification Introduction LogiCORETM IP Facts The On-Chip Peripheral Bus ( OPB ) to Processor Local Bus (PLB) Bridge module translates OPB transactions into PLB transactions. It functions as a slave on the OPB side and a , from either the OPB or an optional DCR interface. The OPB to PLB Bridge is necessary in systems where an OPB master device, such as a DMA engine or an OPB based coprocessor, requires access to PLB


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PDF DS404 xbm 898
2005 - vhdl code for 4 channel dma controller

Abstract:
Text: 0 OPB Central DMA Controller DS472 December 1, 2005 0 0 Product Specification Introduction LogiCORETM Facts The OPB Central DMA Controller provides simple Direct Memory Access (DMA) services for peripherals and memory devices on the OPB bus. The controller moves a programmable quantity of , OPB burst transfers Block RAMs 0 0 Provided with Core Documentation Product , www.xilinx.com 1 OPB Central DMA Controller DMA Operation A DMA operation is set up and started by


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PDF DS472 vhdl code for 4 channel dma controller dma spartan 3 vhdl code dma controller
2004 - Virtex-4 XC4VLX60

Abstract:
Text: 0 DS496 November 15, 2005 0 MCH OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM , ) On-chip Peripheral Bus ( OPB ) Double Data Rate Synchronous DRAM (SDRAM) controller for Xilinx FPGAs provides a DDR SDRAM controller which connects to the OPB and multiple channel interfaces and provides the , Features Min The Xilinx MCH OPB DDR SDRAM Controller is a soft IP core designed for Xilinx FPGAs and , 34, and Table 11 on page 35. LUTs Optional OPB interface · Slices · Performs


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PDF DS496 UG081. DS494. DS424. CR211535 Virtex-4 XC4VLX60 A01055 CLK180 DS424 sdram controller vhdl code for ddr sdram controller XC2VP20 XC3S1500 XC4VLX60
CMOS-6SF

Abstract:
Text: 64-bit OPB to PLB Bridge Core C12E318_OPB_PLB_BR High performance core for highly integrated Core+ASIC systems Highlights The OPB to PLB bridge is a CMOS-6SF technology soft core which enables transfers of data between the on-chip peripheral bus ( OPB ) and the processor local bus (PLB) under the direction of OPB master devices. The OPB to PLB bridge is a slave on the OPB and a master on the PLB. The OPB to PLB bridge core is required for any application using the OPB master devices that access


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PDF 64-bit C12E318 CMOS-6SF
Supplyframe Tracking Pixel