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Part Manufacturer Description Datasheet Download Buy Part
X9520B20I-AT1 Intersil Corporation DIGITAL POTENTIOMETER, PBGA20, XBGA-20
X9520B20I-BT1 Intersil Corporation DIGITAL POTENTIOMETER, PBGA20, XBGA-20
X9520V20I-BT1 Intersil Corporation DIGITAL POTENTIOMETER, PDSO20, PLASTIC, TSSOP-20
X9523V20I-A Intersil Corporation DIGITAL POTENTIOMETER, PDSO20, PLASTIC, TSSOP-20
X9520V20I-B Intersil Corporation DIGITAL POTENTIOMETER, PDSO20, PLASTIC, TSSOP-20
X9521V20IT1 Intersil Corporation DIGITAL POTENTIOMETER, PDSO20, PLASTIC, TSSOP-20

NSP POTENTIOMETER Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
CLC014

Abstract: nrz to nrzi decoder sd901asm SD901ASM-2 CLC016 "Pin for Pin" CLC012 CLC011 CLC006 P6245
Text: . Default is no jumper FE: Set this jumper to disable frame enable. FE may also be tied to NSP as described in the CLC011 datasheet. Default is no jumper. NSP , TRS, EAV: Monitor points for new sync position , by a 50K potentiometer labeled VR1. The serial clock may be viewed at TP3 and TP4. MUTE can be , also be tied to NSP at this jumper block. TRS (timing reference signal), EAV (end of active video), and NSP (new sync position) may also be monitored at JP3. Parallel Outputs The parallel clock and


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PDF SD901ASM CLC014 CLC016 CLC011 SD901ASM: SD901ASM-1 SD901ASM-2 nrz to nrzi decoder "Pin for Pin" CLC012 CLC006 P6245
HC2010

Abstract: mhac Hughes Aircraft Company HC2012 VE310 Hughes Microelectronics Hughes aircraft Hughes HC-201 Hughes Solid State
Text: HUGHES MICROELECTRONICS b4E D ■4bl32S0 QOOElfih hûD MHAC HC2010 / HC2012 NSP FAMILY NONVOLATILE SERIALLY PROGRAMMABLE SOLID STATE TRIM POTENTIOMETERS HUGHES SEMICONDUCTOR PRODUCTS CENTER DESCRIPTION The , . A standard serial interface, common to all the NSP devices, is used to access the nonvolatile memory. FEATURES PIN CONFIGURATION ° CMOS ° Wide Supply Range (3 to 10 volts) ° Standard " NSP " Serial Interface , DESCRIPTION The Potentiometer function is provided by an eight stage R-2R ladder circuit. This circuit


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PDF 4bl32S0 HC2010 HC2012 16612S HC2812 mhac Hughes Aircraft Company VE310 Hughes Microelectronics Hughes aircraft Hughes HC-201 Hughes Solid State
2010 - nsp 05

Abstract: No abstract text available
Text: NSP /NSPP Series Ceramic Housed ­ Consumer Grade Stackpole Electronics, Inc. Resistive Product , / lead-free Electrical Specifications Type / Code NSP 2 NSP 3 NSP 5 NSP 7 NSP 10 NSP 15 NSP 20 Power , 20K 0.1 - 20K 0.1 - 20K 0.1 - 2K 0.1 - 2K 0.1 - 5.1K NSP 25 25W (*) Lesser of PR or maximum working voltage. How to Order SEI Type Code Nominal Resistance Tolerance Packaging NSP Type NSP NSPP , and/or use. 1 www.seielect.com marketing@seielect.com NSP /NSPP Series Ceramic Housed ­


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PDF 200ppm/ from100% nsp 05
Not Available

Abstract: No abstract text available
Text: NSP /NSPP Series Stackpole Electronics, Inc. Ceramic Housed – Consumer Grade Resistor , Rating (Watts) @ 25ºC NSP 2 2W NSP 3 3W NSP 5 5W NSP 7 7W NSP 10 10W NSP 15 15W NSP 20 20W NSP 25 25W (*) Lesser of √PR or maximum working voltage. Maximum Working Voltage , marketing@seielect.com NSP /NSPP Series Stackpole Electronics, Inc. Ceramic Housed – Consumer Grade Resistor , C Body Height D Lead Length (Bulk) E Lead Diameter F Standoff Height Units NSP 2


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PDF 200ppm/Â from100%
2000 - Not Available

Abstract: No abstract text available
Text: NSP /NSPP Series - Ceramic Housed - Consumer Grade Features · Flameproof construction · , 20K 0.1 ­ 20K 0.1 ­ 2K 0.1 ­ 2K 0.1 ­ 5.1K NSP 2 NSP 3 NSP 5 NSP 7 NSP 10 NSP 15 NSP 20 NSP 25 * Lesser of PR or maximum working voltage. How to Order NSP SEI Type 7 Code 1.2K Nominal Resistance 5% Tolerance A Packaging Code NSP Description Standard Code 2 3 5 7 10 15 20 25 , ) SEI-SEIS (888) 734-7347 www.seielect.com 61 email: marketing@seielect.com NSP /NSPP Series -


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PDF 200ppm/
2000 - Not Available

Abstract: No abstract text available
Text: NSP Series — Ceramic Housed - Consumer Grade Features • Flameproof construction â , Temperature Coefficient NSP 2 2W 100 ±200 ppm/°C 0.1Ω – 20K NSP 3 3W 200 ±200 ppm/°C 0.1Ω – 20K NSP 5 5W 300 ±200 ppm/°C 0.1Ω – 20K NSP 7 7W 350 ±200 ppm/°C 0.1Ω – 20K NSP 10 10W 500 ±200 ppm/°C 0.1Ω – 20K NSP 15 15W 600 ±200 ppm/°C 0.1Ω – 2K NSP 20 20W 700 ±200 ppm/°C


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PDF 200ppm/Â
2010 - nsp 05

Abstract: 1R00
Text: NSP /NSPP Series Stackpole Electronics, Inc. Ceramic Housed ­ Consumer Grade Resistor , (Watts) @ 25ºC NSP 2 2W NSP 3 3W NSP 5 5W NSP 7 7W NSP 10 10W NSP 15 15W NSP 20 20W NSP , ±5% ±2% ±2% ±2% 1 www.seielect.com marketing@seielect.com NSP /NSPP Series Stackpole , Lead Diameter F Standoff Height Units NSP 2 0.71 ± 0.02 18.0 ± 0.5 0.28 ± 0.04 7.0 ± , 0.12 36.0 ± 3.0 0.026 ± 0.002 0.65 ± 0.05 0.04 1.00 inches mm NSP 3 0.87 ± 0.02


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PDF 200ppm/ from100% nsp 05 1R00
2010 - NS256P

Abstract: CR013 S29NS-P S29NS-R VS256R SA555H SPANSION date code format VS128R
Text: . Feature Comparisons Summary The following lists the items to consider when migrating from NS-P to VS-R , features in NS-P VS-R features a Status Register, instead of DQ Polling on the NS-P Command Set Changes , banks of the NS-P VS-R has different Device ID values than the NS-P VS-R has significant changes in , Configuration Register, instead of two Configuration Registers in the NS-P VS-R has differences in Electrical , NS-P VS-R Technology MirrorBit MirrorBit Process Node 90 nm 65 nm Densities


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PDF S29NS-P S29VS-R S29VS-R S29NS-P. S29NS-R, S29NS-R NS256P CR013 VS256R SA555H SPANSION date code format VS128R
2007 - nsp 05

Abstract: No abstract text available
Text: NSP Series - Ceramic Housed - Consumer Grade Features · Flameproof construction · Temperature , ­ 2K 0.1 ­ 5.1K NSP 2 NSP 3 NSP 5 NSP 7 NSP 10 NSP 15 NSP 20 NSP 25 * Lesser of PR or maximum working voltage. How to Order NSP SEI Type 7 Code 1.2K Nominal Resistance 5% Tolerance A Packaging Code NSP Description Standard Code 2 3 5 7 10 15 20 25 Tolerance 5 , (888) 734-7347 www.seielect.com 61 email: marketing@seielect.com NSP Series - Ceramic Housed


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PDF 200ppm/ nsp 05
2000 - 08 nsp

Abstract: NSP Series nsp 05
Text: NSP /NSPP Series - Ceramic Housed - Consumer Grade Features · Flameproof construction · , Coefficient NSP 2 2W 100V ±200 ppm/°C 0.1 ­ 20K NSP 3 3W 200V ±200 ppm/°C 0.1 ­ 20K NSP 5 5W 300V ±200 ppm/°C 0.1 ­ 20K NSP 7 7W 350V ±200 ppm/°C 0.1 ­ 20K NSP 10 10W 500V ±200 ppm/°C 0.1 ­ 20K NSP 15 15W 600V ±200 ppm/°C 0.1 ­ 2K NSP 20 20W 700V ±200 ppm/°C 0.1 ­ 2K NSP 25 25W 700V ±200 ppm/°C


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PDF 200ppm/ 08 nsp NSP Series nsp 05
2002 - CLC011

Abstract: CLC011BCQ CLC014 CLC016 nrz to nrzi decoder SD901EVK V28A
Text: the parallel clock output. NSP 14 New sync position. Indicates that the most recent TRS is in , current PCLK, is received, output NSP will go high. However, the phase of PCLK will not be adjusted. NSP , TRS is received, PCLK is aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that is out of phase with the existing PCLK is detected, NSP will go high, but the phase of PCLK will


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PDF CLC011 CLC011, 10-bit CLC011 CLC011BCQ CLC014 CLC016 nrz to nrzi decoder SD901EVK V28A
1997 - CLC011

Abstract: Receiver Circuit Schematic 27mhz CLC011ACQ CLC014 CLC016 SMPTE259M
Text: Delayed Clock VCP PCLK Advanced Clock EAV FE Framer TRS CLC011 Block Diagram NSP , FE 11 19 PD1 VDP PDO PCLK TRS NSP VCP VCC 12 13 14 15 16 17 18 Name , clock output. NSP 14 New sync position. Indicates that the most recent TRS is in a new , 000 000 PCLK NSP TRS EAV Resynchronization Timing ­ FE tied to NSP PDATA 3FF 000 000 PCLK NSP TRS EAV Figure 1: Timing Diagrams CLC011 Operation Overview The CLC011


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PDF CLC011 CLC011 Receiver Circuit Schematic 27mhz CLC011ACQ CLC014 CLC016 SMPTE259M
CLC011

Abstract: CLC011BCQ CLC014 CLC016 V28A
Text: . NSP 14 New sync position. Indicates that the most recent TRS is in a new position relative to the , Resynchronization Timing - FE tied to Vcc pdata X~ X~3ff~X 000 X~000~X sav X" X X 3ff X""ooo~X 000 X eav X~ nsp _i i_ trs-1_i-1_t eav |_r Resynchronization Timing - FE tied to NSP pdata ~X X X~3fFX , By Its Respective Manufacturer + Input Interfacing—Control Inputs (Continued) NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high until a TRS, in-phase with the


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PDF CLC011 CLC011, 10-bit CLC011 dsl00086 CLC011BCQ CLC014 CLC016 V28A
Not Available

Abstract: No abstract text available
Text: INRZI DESC FE V cc VCP NSP TRS PCLK PD0-9 VDP Parallel data high level programming pin. The , Resynchronization Timing - FE tied to Vcc PDATA PCLK NSP TRS EAV X X "X 3FF X ~Ö Ö O 000 X SAV % "X 3FF X ^O Ö Q Q00 X EAV X" Resynchronization Timing - FE tied to NSP PDATA PCLK NSP TRS EAV FIGURE 1. ~X )C K 3 f f jT ooQ Q O Q X SAV )T X X ~ 3 ff , . When FE is held low and a TRS, out of phase with the current PCLK, is received, output NSP will go high


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PDF CLC011 CLC011, 10-bit
2000 - OSRAM MR16 halogen lamp 50w

Abstract: OSRAM MR16 halogen lamp OSRAM MR16 halogen lamp 12v 50w osram MR16 dimensions electronic transformer halogen 12v 58550 Sylvania OSRAM osram sylvania OSRAM MR16 halogen lamp dimension OSRAM 12V halogen lamp
Text: SP 10° FL 35° NSP 8° Beam Angle 35W 50W FL 40° TRU-AIM MR16 STANDARD TRU-AIM MR16 , consistent color over life · Transmits heat through back of reflector 20W SP 10° FL 40° NSP 8° SP 20° FL 40° SP 8° FL 35° NSP 10° FL 35° NSP 10° NSP 10° NFL 25°* FL 40° VWFL 60 , back of lamp *Available with covered lens HAL008R1 NSP 10° NFL 25° FL 40° NSP 12° NFL 25° FL 40° VWFL 60° NSP 11° NFL 25° FL 35° NSP 10° NFL 25° FL 40° VWFL 60° NSP 10° NFL 25° FL


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PDF 6000-hour OSRAM MR16 halogen lamp 50w OSRAM MR16 halogen lamp OSRAM MR16 halogen lamp 12v 50w osram MR16 dimensions electronic transformer halogen 12v 58550 Sylvania OSRAM osram sylvania OSRAM MR16 halogen lamp dimension OSRAM 12V halogen lamp
2000 - NSP Series

Abstract: No abstract text available
Text: NSP /NSPP Series - Ceramic Housed - Consumer Grade Features · Flameproof construction · , 20K 0.1 ­ 20K 0.1 ­ 20K 0.1 ­ 2K 0.1 ­ 2K 0.1 ­ 5.1K NSP 2 NSP 3 NSP 5 NSP 7 NSP 10 NSP 15 NSP 20 NSP 25 * Lesser of PR or maximum working voltage. How to Order NSP SEI Type 7 Code 1.2K Nominal Resistance 5% Tolerance A Packaging Code NSP Description Standard Code 2 3 5 7 10 , : marketing@seielect.com Rev 10/06 NSP /NSPP Series - Ceramic Housed - Consumer Grade Mechanical Specifications


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PDF 200ppm/ NSP Series
1998 - CLC011

Abstract: CLC011ACQ CLC014 CLC016
Text: logic high level for the parallel clock output. NSP 14 New sync position. Indicates that the , . When FE is held low and a TRS, out of phase with the current PCLK, is received, output NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high until a TRS, in-phase with , TRS is received, PCLK is aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that


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PDF CLC011 CLC011, 10-bit CLC011 word959 CLC011ACQ CLC014 CLC016
electromagnetic lock

Abstract: XMCC350M electronic locks XMCC201M XMCC201U sliding door datasheet XMCC202U different types of electronic lock XMCC350U XZCC350
Text: nsp magtec u l t r a r a n g e Section 2 nsp magtec u l t r a r a n g e , releasing, per NFPA 101. 2.1 nsp XMCC201U & XMCC201M - Ultra magtec u l t r a r a n g e , Z Bracket Installation Inswing door installation 2.2 nsp XMCC202U & XMCC202M - Ultra , nsp XMCC350U & XMCC350M - Ultra magtec u l t r a r a n g e Description Steel standard , installation 2.4 XMCC500U & XMCC500M - Ultra nsp magtec u l t r a r a n g e Description


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PDF 12vdc 500mA. XQMCC201 XMCC17U XMCC17M XLCC350 XMCC40U, XMCC40M, XMCC50U XMCC50M electromagnetic lock XMCC350M electronic locks XMCC201M XMCC201U sliding door datasheet XMCC202U different types of electronic lock XMCC350U XZCC350
2000 - CLC011

Abstract: CLC011BCQ CLC014 CLC016 V28A
Text: voltage at this supply pin defines the logic high level for the parallel clock output. NSP 14 , received, output NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high , this mode, when a TRS is received, PCLK is aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that is out of phase with the existing PCLK is detected, NSP will go high, but the


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PDF CLC011 CLC011, 10-bit CLC011 CLC011BCQ CLC014 CLC016 V28A
CLC011

Abstract: CLC011BCQ CLC014 CLC016
Text: g -O NSP DS100086-1 ) 1998 National , level for the parallel clock output. NSP 14 New sync position. Indicates that the most recent TRS is in , to Vcc PDATA ~X X~ X~3FF~X 000 X~~000~X SAV X" X X 3FF x 000 X~000~X EAV x~ NSP _I I_ TRS -1_I-1_r EAV I_r Resynchronization Timing — FE tied to NSP PDATA ~X X X~~3FF~X 000 X~000~X~SAV~X" X X 3FF X 000 X~~000~X EAV X~ PCLK NSP TRS EAV ~L DS100086-3 www.national.com This Material


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PDF CLC011 CLC011, 10-bit CLC011 CLC011BCQ CLC014 CLC016
CLC011

Abstract: CLC014 CLC016 SMPTE259M
Text: . The voltage at this supply pin defines the logic high level for the parallel clock output. NSP 14 New , X eav X~ pdata ~X X" pclk nsp trs eav "l Resynchronization Timing - FE tied to NSP X~3ff~X ooo X , Connection Output Interface All outputs on the CLC011 (PDO-9, EAV, TRS NSP and PCLK) are CMOS compatible , , by applying the VDD voltage from the CMOS logic to VDP (PDO-9, EAV, TRS and NSP ) and VCP (PCLK). , -9 PCLK EAV TRS NSP 7 10 vdd CLC011 Figure 5: Typical Output Interface The CLC011 has constant slew


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PDF CLC011 CLC014 CLC016 SMPTE259M
1998 - CLC011

Abstract: CLC011ACQ CLC014 CLC016 V28A
Text: pin. VCP NSP Parallel clock high level programming pin. The voltage at this supply pin defines , Interfacing-Control Inputs (Continued) NSP will go high. However, the phase of PCLK will not be adjusted. NSP will , received, PCLK is aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that is out of phase with the existing PCLK is detected, NSP will go high, but the phase of PCLK will not be


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PDF CLC011 CLC011, 10-bit CLC011 word959 CLC011ACQ CLC014 CLC016 V28A
1999 - CLC011

Abstract: CLC011ACQ CLC014 CLC016
Text: the parallel clock output. NSP 14 New sync position. Indicates that the most recent TRS is in , is held low and a TRS, out of phase with the current PCLK, is received, output NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high until a TRS, in-phase with the , , PCLK is aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that is out of


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PDF CLC011 CLC011, 10-bit CLC011 word959 CLC011ACQ CLC014 CLC016
CLC011

Abstract: CLC011ACQ CLC014 CLC016 V28A
Text: Register Advanced Clock 2nd Register {>-OE NSP DS100086-1 © 1998 National Semiconductor , . NSP 14 New sync position. Indicates that the most recent TRS is in a new position relative to the , ~X oop X eav X~ NSP _I I_ TRS -1_I-1_r EAV I_r Resynchronization Timing - FE tied to NSP , Manufacturer Input Interfacing—Control Inputs (Continued) NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high until a TRS, in-phase with the current PCLK, is received


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PDF CLC011 CLC011, 10-bit CLC011 CLC011ACQ CLC014 CLC016 V28A
2000 - 2013 ASSEMBLY OF CODE TI

Abstract: No abstract text available
Text: SNLS017D ­ JULY 2000 ­ REVISED APRIL 2013 Table 1. Pin Descriptions (continued) Name NSP TRS PCLK PD0 , , output NSP will go high. However, the phase of PCLK will not be adjusted. NSP will remain high until a , aligned to the new TRS. If a new sync position ( NSP ) is identified, the NSP output will go high until the next TRS is received. 2. FE tied to NSP . When in this mode, if a TRS that is out of phase with the existing PCLK is detected, NSP will go high, but the phase of PCLK will not be adjusted. If the next TRS


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PDF CLC011 SNLS017D CLC011 CLC011B 360Mbps CLC011, 10-bit 2013 ASSEMBLY OF CODE TI
Supplyframe Tracking Pixel