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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC3730CG Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3730CG#TRPBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3730CG#TR Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3730CG#PBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3735EG#TR Linear Technology LTC3735 - 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C
LTC3735EG#PBF Linear Technology LTC3735 - 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C

Mobile DDR SDRAM Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
TRCD3C

Abstract: mobile ddr
Text: Mobile DDR SDRAM MOBILE DDR SDRAM Device Operations & Timing Diagram 1 DEVICE OPERATIONS Mobile DDR SDRAM Precharge The precharge command is used to precharge or close a bank that , deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile , OPERATIONS Mobile DDR SDRAM Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The Mobile DDR SDRAM has four


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PDF 200us A10/AP TRCD3C mobile ddr
2008 - HY5MS5B6BLFP

Abstract: HY5MS5B6BL
Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.0 / Jun. 2008 1 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR SDRAM , Remark Preliminary Preliminary Rev 1.0 / Jun. 2008 2 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer


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PDF 128Mbit 8Mx16bit) 128Mbit 16bit) H5MS1262EFP 16bits) HY5MS5B6BLFP HY5MS5B6BL
2009 - hynix mcp

Abstract: HY5MS5B6BL H5MS1262EFP 2Mx16
Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile , DDR SDRAM based on 2M x 4Bank x16 I/O Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR , licenses are implied. Rev 1.1 / July. 2009 2 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM - Double data rate , READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM ) Mobile DDR SDRAM INTERFACE CAS


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PDF 128Mbit 8Mx16bit) 128Mbit 16bits) 16bit) H5MS1262EFP 00Typ. hynix mcp HY5MS5B6BL 2Mx16
2009 - H5MS5162

Abstract: H5MS5162DFR h5ms5162dfr-j3m hynix mcp DDR333 DDR370 DDR400
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb (32Mx16bit) Mobile , Apr. 2009 Rev 1.3 / Apr. 2009 2 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM - Double data rate , READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM ) Mobile DDR SDRAM INTERFACE , ) INITIALIZING THE MOBILE DDR SDRAM - Occurring at device power up or interruption of device power - DPD


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PDF 512Mbit 512Mb 32Mx16bit) 512Mbit 16bit) H5MS5162DFR 16bits) H5MS5162 h5ms5162dfr-j3m hynix mcp DDR333 DDR370 DDR400
2008 - hynix ddr ram

Abstract: H5MS1222EFP
Text: 128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O Specification of 128M (4Mx32bit) Mobile , . 2008 Rev 1.0 / Jun. 2008 2 Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , regulation (Low Power DDR SDRAM ) Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP - , DDR SDRAM . - Keep to the JEDEC Standard regulation INITIALIZING THE MOBILE DDR SDRAM - Occurring


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PDF 128Mbit 4Mx32bit) 128Mbit 32bit) H5MS1222EFP 32bits) hynix ddr ram
2008 - H5MS1G62

Abstract: H5MS1G62MFP-J3M H5MS1G62MFP h5ms1g hynix mcp ap die hen mcp DDR400 H5MS1G62MFP-K3M
Text: 1Gbit MOBILE DDR SDRAM based on 16M x 4Bank x16 I/O Specification of 1Gb (64Mx16bit) Mobile DDR , SDRAM 1Gbit (64M x 16bit) H5MS1G62MFP Series Document Title 1Gbit (4Bank x 16M x 16bit) MOBILE DDR , / Jul. 2008 2 Mobile DDR SDRAM 1Gbit (64M x 16bit) H5MS1G62MFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle MODE RERISTER , (Low Power DDR SDRAM ) Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address (Row


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PDF 64Mx16bit) 16bit) H5MS1G62MFP page22) 00Typ. H5MS1G62 H5MS1G62MFP-J3M h5ms1g hynix mcp ap die hen mcp DDR400 H5MS1G62MFP-K3M
2008 - H5MS5122DFR

Abstract: H5MS5122DFR-J3M DDR333 DDR400 h5ms H5MS5132DFR
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Specification of 512Mb (16Mx32bit) Mobile , 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark , Mobile DDR SDRAM 512Mbit (16M x 32bit) H5MS5122DFR Series / H5MS5132DFR Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle MODE RERISTER , (Low Power DDR SDRAM ) Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplexed Address (Row


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PDF 512Mbit 512Mb 16Mx32bit) 512Mbit 32bit) H5MS5122DFR H5MS5132DFR 32bits) H5MS5122DFR-J3M DDR333 DDR400 h5ms
2008 - Not Available

Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit (4Bank x 2M x 32bits) MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - , licenses are implied. Rev 1.1 / May. 2008 1 Mobile DDR SDRAM 256Mbit (8M x 32bit) HY5MS5B2ALFP Series FEATURES SUMMARY ● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , Standard regulation (Low Power DDR SDRAM ) ● Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP


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PDF 256Mbit 256MBit 32bits) LPDDR266/200 32bit)
2008 - H5MS5162

Abstract: h5ms H5MS5162DFR
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb (32Mx16bit) Mobile , use of circuits described. No patent licenses are implied. Rev 1.1 / May 2008 1 Mobile DDR SDRAM , Preliminary Preliminary 1.1 May 2008 Rev 1.1 / May 2008 2 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series 11 FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address


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PDF 512Mbit 512Mb 32Mx16bit) 512Mbit 16bit) H5MS5162DFR 16bits) DDR333 DDR400 H5MS5162 h5ms
2008 - h5ms1g22

Abstract: No abstract text available
Text: 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb (32Mx32bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.1 / May 2008 1 Mobile DDR SDRAM 1Gbit (32M x , / May 2008 2 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series FEATURES SUMMARY ● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , Standard regulation (Low Power DDR SDRAM ) ● Mobile DDR SDRAM INTERFACE - x32 bus width -


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PDF 32Mx32bit) 32bit) H5MS1G22MFP H5MS1G32MFP h5ms1g22
2008 - Not Available

Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/ Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , Mobile DDR SDRAM 512Mbit (16M x 32bit) HY5MS7B2BLF(P) Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus , mode is a feature supported by Mobile DDR SDRAM . - Keep to the JEDEC Standard regulation INITIALIZING


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PDF 512Mbit 512MBit 32bits) LPDDR333 32bit)
2008 - LPDDR200

Abstract: HY5MS7B6BLFP
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit (4Bank x 8M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , patent licenses are implied. Rev 1.3 / Jun. 2007 1 Mobile DDR SDRAM 512Mbit (32M x 16bit) HY5MS7B6BLF(P) Series 11 FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x16 bus width: HY5MS7B6BLFP - Multiplexed Address


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PDF 512Mbit 512Mbit 16bits) LPDDR266 16bit) 00Typ. LPDDR200 HY5MS7B6BLFP
2007 - Not Available

Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , 1.1 / Apr. 2007 1 11 Mobile DDR SDRAM 512Mbit (16M x 32bit) HY5MS7B2BLF(P) Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR , FBGA CLOCK STOP MODE - Clock stop mode is a feature supported by Mobile DDR SDRAM . - Keep to the JEDEC


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PDF 512Mbit 512MBit 32bits) LPDDR333 32bit)
DDR222

Abstract: DDR266 DDR333 EMD28164PA EMD28164PA-60 EMD28164PA-75 EMD28164PA-90
Text: EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Document Title 128M: 8M x 16 Mobile DDR SDRAM , office. 1 Rev 1.0 EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM 128M : 8M x 16bit Mobile DDR , Rev 1.0 EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Table 2: Pad Description Symbol Type , 16 Mobile DDR SDRAM Device Operation Simplified State Diagram Power On Power applied , : 8M x 16 Mobile DDR SDRAM Electrical Specifications Table 3: ABSOLUTE MAXIMUM RATINGS Parameter


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PDF EMD28164PA 133MHz 125MHz 111MHz 100MHz 83MHz 40MHz DDR222 DDR266 DDR333 EMD28164PA EMD28164PA-60 EMD28164PA-75 EMD28164PA-90
512M

Abstract: DDR266 DDR332 EMD12324P EMD12324P-60 EMD12324P-75
Text: Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Document Title 512M: 16M x 32 Mobile , office. 1 Rev 0.0 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM 512M : 16M x 32bit Mobile DDR SDRAM FEATURES 1.8V power supply, 1.8V I/O power LVCMOS compatible with multiplexed , EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Table 2: Pad Description Symbol Type Descriptions , Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Device Operation Simplified State Diagram


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PDF EMD12324P 32bit 133MHz 125MHz 111MHz 100MHz 512M DDR266 DDR332 EMD12324P EMD12324P-60 EMD12324P-75
DDR266

Abstract: DDR332 EMD56164P EMD56164P-60 EMD56164P-75
Text: Preliminary EMD56164P 256M: 16M x16 Mobile DDR SDRAM Document Title 256M: 16M x 16 Mobile , office. 1 Rev 0.0 Preliminary EMD56164P 256M: 16M x 16 Mobile DDR SDRAM 256M : 16M x 16bit Mobile DDR SDRAM FEATURES · 1.8V power supply, 1.8V I/O power · LVCMOS compatible with , Rev 0.0 Preliminary EMD56164P 256M: 16M x 16 Mobile DDR SDRAM Table 2: PAD DISCRIPTION , x16 Mobile DDR SDRAM Device Operation Simplified State Diagram Power On Power applied


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PDF EMD56164P 16bit 133MHz 125MHz 111MHz 100MHz DDR266 DDR332 EMD56164P EMD56164P-60 EMD56164P-75
2001 - K4M56163PI

Abstract: DDR266 DDR333 60FBGA SDRAM16MX16
Text: K4X56163PI - L(F)E/G Mobile DDR SDRAM 16Mx16 Mobile DDR SDRAM 1. FEATURES · VDD/VDDQ = 1.8V , 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 5. FUNCTIONAL BLOCK DIAGRAM CK, CK LWE I , Register WE -5- DM October 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 6. Package , 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 7. Input/Output Function Description Symbol , connection is present. -7- October 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 8. Functional


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PDF K4X56163PI 16Mx16 K4M56163PI DDR266 DDR333 60FBGA SDRAM16MX16
2001 - samsung CL21

Abstract: K4X1G323PC K4X1G323PC-7 K4X1G323 CL21 CL31 DDR266 DDR333 row decoder
Text: K4X1G323PC - L(F)E/G Mobile DDR SDRAM 32Mx32 Mobile DDR SDRAM 1. FEATURES · VDD/VDDQ = 1.8V , 2007 K4X1G323PC - L(F)E/G Mobile DDR SDRAM 5. FUNCTIONAL BLOCK DIAGRAM CK, CK LWE I , Register WE -5- DM Sept 2007 K4X1G323PC - L(F)E/G Mobile DDR SDRAM 6. Package , 0.55 z -6- - e - - 0.10 Sept 2007 K4X1G323PC - L(F)E/G Mobile DDR SDRAM , Mobile DDR SDRAM 8. Functional Description Figure 1. State diagram POWER APPLIED DEEP POWER


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PDF K4X1G323PC 32Mx32 samsung CL21 K4X1G323PC-7 K4X1G323 CL21 CL31 DDR266 DDR333 row decoder
2006 - DDR SDRAM Controller look-ahead

Abstract: DDR SDRAM Controller mobile ddr
Text: Mobile DDR SDRAM Controller Core Product Highlights Block Diagram · High memory throughput , Supports all standard mobile DDR SDRAM chips Bank Management Bank Management cke ras_n Queue , Customization and Integration services available Mobile DDR SDRAM Device(s) Refresh Control Clock , Mobile DDR SDRAM configurations. The core accepts commands using a simple local interface and translates them to the command sequences required by Mobile DDR SDRAM devices. The core also performs all


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PDF
2009 - H5MS2562

Abstract: H5MS2562JFR hynix mcp H5MS2562JFR-J3M DDR370 16M X 32 SDR SDRAM H5MS256
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile , DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR , described. No patent licenses are implied. Rev 1.2 / July. 2009 2 Mobile DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM , ) Mobile DDR SDRAM INTERFACE CAS LATENCY - Multiplexed Address (Row address and


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PDF 256Mbit 256Mb 16Mx16bit) 256Mbit 16bits) 16bit) H5MS2562JFR 00Typ. H5MS2562 hynix mcp H5MS2562JFR-J3M DDR370 16M X 32 SDR SDRAM H5MS256
2014 - taylor

Abstract: No abstract text available
Text: AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks GENERAL DESCRIPTION The , -4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks PIN CONFIGURATION Alliance Memory, Inc., 551 , Rev1-4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks INPUT / OUTPUT FUNCTION , Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks FUNCTIONAL BLOCK DIAGRAM Alliance Memory, Inc., 551 Taylor , -4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks SIMPLIFIED STATE DIAGRAM CKEH : Clock Enable


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PDF AS4C32M16MD1 AS4C32M16MD1 Rev1-4Jan2014 60-Ball taylor
2009 - hynix mcp

Abstract: DDR370 H5MS2532JFR H5MS2
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Specification of 256Mb (8Mx32bit) Mobile , DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit (4Bank x 2M x 32bits) MOBILE DDR , implied. Rev 1.2 / Apr. 2009 2 Mobile DDR SDRAM 256Mbit (8M x 32bit) H5MS2622JFR Series H5MS2532JFR Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM - Double data , STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM ) Mobile DDR SDRAM


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PDF 256Mbit 256Mb 8Mx32bit) 256MBit 32bits) 32bit) H5MS2622JFR H5MS2532JFR hynix mcp DDR370 H5MS2
2008 - H5MS2562JFR

Abstract: H5MS2 h5ms2562jfr-j3m H5MS2562
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile , DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM , DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x16 bus width - , Mobile DDR SDRAM . - Keep to the JEDEC Standard regulation INITIALIZING THE MOBILE DDR SDRAM - Occurring


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PDF 256Mbit 256Mb 16Mx16bit) 256Mbit 16bits) 16bit) H5MS2562JFR 00Typ. H5MS2 h5ms2562jfr-j3m H5MS2562
2008 - H5MS1G22

Abstract: h5ms1g H5MS1G22MFP H5MS1G32MFP hynix mcp
Text: 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb (32Mx32bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.2 / Jun. 2008 1 Mobile DDR SDRAM 1Gbit (32M x , Preliminary Rev 1.2 / Jun. 2008 2 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplexed Address (Row address and


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PDF 32Mx32bit) 32bit) H5MS1G22MFP H5MS1G32MFP page23) 100mA 120mA 450uA 500uA H5MS1G22 h5ms1g hynix mcp
DDR RAM 512M

Abstract: DDR266 DDR332 EMD12164P EMD12164P-60 EMD12164P-75
Text: Preliminary EMD12164P 512M: 32M x16 Mobile DDR SDRAM Document Title 512M: 32M x 16 Mobile , office. 1 Rev 0.0 Preliminary EMD12164P 512M: 32M x 16 Mobile DDR SDRAM 512M : 32M x 16bit Mobile DDR SDRAM FEATURES 1.8V power supply, 1.8V I/O power LVCMOS compatible with multiplexed , EMD12164P 512M: 32M x 16 Mobile DDR SDRAM Table 2: Pad Description Symbol Type Descriptions , Preliminary EMD12164P 512M: 32M x 16 Mobile DDR SDRAM Device Operation Simplified State Diagram


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PDF EMD12164P 16bit 133MHz 125MHz 111MHz 100MHz DDR RAM 512M DDR266 DDR332 EMD12164P EMD12164P-60 EMD12164P-75
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