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Part Manufacturer Supplier Stock Best Price Price Each Buy Part
MX-9301 OMRON Corporation Avnet - $349.19 $282.39
MX-9301 OMRON Industrial Automation Sager - $323.40 $292.60
MX9301 OMRON Industrial Automation Allied Electronics & Automation - $253.16 $253.16

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MX9301 datasheet (3)

Part Manufacturer Description Type PDF
MX93011A Macronix International APPLICATION NOTE [K1 VERSION] Original PDF
MX93011AFC Macronix International Digital signal processor Original PDF
MX93011AFC Macronix International DSP Controller for DAM (Digital Answering Machine) Scan PDF

MX9301 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
768KHZ

Abstract: MX93011 MX93011A X321 mxic dsp instruction set
Text: IWKIC MX9301 1 A CONTENT I.0 FEATURES 1.1 DIFFERENCE BETWEEN MX93011 and MX93011A 2.0 , pins PQFP 1.1 DIFFERENCE BETWEEN MX93011 AND MX93011A 1. external memory wait state: I/o register(8) MX93011 0 1 1 1 1 MMSIZE SRAMWAIT MMWAIT 2 1 1 1 ROMWAIT 0 1 MX93011A 0 1 1 1 1 1 1 1 MMSIZE , register: MX93011 0 0 0 0 MX93011A 4 3 2 1 0 3.internal ROM: MX93011 18Kx16 MX93011A 32Kx16 4 , INFORMATION 1 ■vpgc MX93011A 1.0 FEATURES • 16-bit, 46.5ns instruction cycle, up to 21 MIPS DSP


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PDF MX9301 MX93011 MX93011A 16-bit, ap93011A MX93Q11A 100-PIN 768KHZ MX93011A X321 mxic dsp instruction set
2001 - 322267

Abstract: MX93111 IPT84 MX93111 FC MX93011C
Text: MX93111 MX93111 DATA SHEET CONTENT 1 INTRODUCTION 1.1 FEATURE 1.2 DIFFERENCE BETWEEN MX93011C AND MX93111 2 3 4 6 9 9 10 13 18 23 28 34 35 36 44 47 49 50 2 PIN 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 3.4 4.1 4.2 4.3 4.4 PIN OUT FOR 128 PIN PQFP MX93111 PIN DESCRIPTIONS PIN TYPE ABBREVIATION PINS SUMMARY BY PIN TYPE MULTIPLEX PINS DATA UNIT MEMORY MAP AND ADDRESSING MODES PROGRAM FLOW CONTROL UNIT , DIFFERENCE between MX93011C and MX93111 MX93011C INTERNAL RAM SIZE 2K Words Bank0 : 0x0000 ~ 0x03FF(1K


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PDF MX93111 MX93111 MX93011C CA95131 322267 IPT84 MX93111 FC
1998 - MX93011

Abstract: ED11 ED12 ED13 MX93011A de441 OPT16-OPT18 macronix audio dsp mxic dsp instruction set
Text: MX93011A CONTENT 1.0 FEATURES 1.1 DIFFERENCE BETWEEN MX93011 and MX93011A 2.0 FUNCTION BLOCK , data bit interface support. · 0.6u Single 5V supply, 100 pins PQFP 1.1 DIFFERENCE BETWEEN MX93011 AND MX93011A 1. external memory wait state: I/o register(8) MX93011 7 0 6 1 MMSIZE , :16x16 MX93011A :32x16 stack pointer register: MX93011 MX93011A 3.internal ROM: MX93011 , 10.0 AC TIMING AND CHARACTERISICS 11.0 ORDER INFORMATION 12.0 PACKAGE INFORMATION 1 MX93011A


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PDF MX93011A MX93011 16-bit, 21MIPS MX93011A ED11 ED12 ED13 de441 OPT16-OPT18 macronix audio dsp mxic dsp instruction set
2001 - MX93132

Abstract: OPT19 mx93111 10k sip resister MXIC DSP ADD mxic dsp instruction set
Text: MX93132 MX93132 DATA SHEET CONTENT 1 INTRODUCTION 1.1 FEATURE 1.2 DIFFERENCE BETWEEN MX93011C AND MX93132 2 3 2 PIN 2.1 2.2 2.3 2.4 2.5 2.6 PIN OUT FOR 128 PIN PQFP MX93132 PIN DESCRIPTIONS PIN TYPE ABBREVIATION PINS SUMMARY BY PIN TYPE MULTIPLEX PINS I/O PORT INTERNAL , 128 2 Ver 0.02, December 22, 2000 MX93132 1.2 DIFFERENCE between MX93011C and MX93132 MX93011C MX93132 2K Words Bank0 : 0x0000 ~ 0x03FF(1K) Bank1 : 0x0400 ~ 0x07FF(1K) 0X0800 2.5K


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PDF MX93132 MX93132 MX93011C CA95131 OPT19 mx93111 10k sip resister MXIC DSP ADD mxic dsp instruction set
ICE ICC3

Abstract: 600fh 7400h MX93011 MX9691 circuit LED sequential turn signal 6 volt 6016h 601EH HD15 macronix dsp
Text: bit as well as 16 bit transfer on host bus. DSP core · High performance MX93011 DSP (21Mips) core , buffer manager, integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and , MX93011 DSP. The internal DSP is disabled. These pins include internal pull-up resistors. In normal mode , drived to high. In ICE de bugging mode, this signal is input, asserted by external MX93011 DSP. The , debug ging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled


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PDF MX9691 20MB/ ICE ICC3 600fh 7400h MX93011 MX9691 circuit LED sequential turn signal 6 volt 6016h 601EH HD15 macronix dsp
mx9691

Abstract: No abstract text available
Text: €¢ High performance MX93011 DSP (21 Mips) core. • 4KB Internal RAM(direct access). • 2KB , flash memory. The MX9691 combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP c o , CYH.CYL registers. In ICE debugging mode, these address are input,asserted by external MX93011 DSP. The , signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. ■■5 , MX93011 DSP. The internal DSP is disabled. RD# 65 I/O In normal mode, this signal is output


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PDF MX9B91 20MB/sec. ha-iocs16) MX9691 mx9691
EAD0-EAD14

Abstract: 89 04c2 ED11 ED12 ED13 ED15 MX93011A
Text: INDEX MX93011A APPLICATION NOTE [K1 VERSION] 6.0 FUNCTIONAL DESCRIPTIONS DAM BIOS The MX93011A-K1 , MX93011A APPLICATION NOTE [K1 VERSION] MESSAGE RECORDING AND STORAGE The MX93011A-K1 BIOS provides a , RAS\ 93 OPT18 37 DWR\ 92 INT1\ 39 MX93011A-K1 DRD\ 91 NMI\ 40 38 CAS , , etc. (see DAM BIOS format) ARAM MANAGEMENT The MX93011A-K1 BIOS uses ARAM as the storage device for message data. ARAM types supported by the MX93011A-K1 BIOS are as follows : 1. 2. 3. 4. 5


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PDF MX93011A MX93011A CA95131 EAD0-EAD14 89 04c2 ED11 ED12 ED13 ED15
PCMCIA ATA FLASH CARD

Abstract: 74640 6002H interfacing of RAM and ROM with 8088 8088 memory interface SRAM a13493 HD11 MX93011 MX9691A 6018H
Text: as 16 bit transfer on host bus. DSP core · High performance MX93011 DSP (21Mips) core. · 4KB , buffer manager, integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and , , these ad dress are input,asserted by external MX93011 DSP. The internal DSP is disabled. These pins , is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus , external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal


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PDF MX9691A 20MB/ PM0539 -100mA 100mA PCMCIA ATA FLASH CARD 74640 6002H interfacing of RAM and ROM with 8088 8088 memory interface SRAM a13493 HD11 MX93011 MX9691A 6018H
Not Available

Abstract: No abstract text available
Text: , High-speed CMOS technology. • 5 Vo It ± 10% or 3.3Volt ± 5%. DSP core • High performance MX93011 , MX93011 DSP core, and a complete host interface for both the PC Card ATA and True IDE standard. The , . In ICE-debugging mode,these address are input, asserted by DSP ICE(external MX93011 DSP). And the , DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a , mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is


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PDF MX9691L 20MB/sec. addres601 PM0546 -100mA 100mA
6016h

Abstract: 6009H macronix dsp 7400h 74640 ic 74640
Text: bus. DSP core · High performance MX93011 DSP (21 Mips) core. · 4KB Internal RAM(direct access). · 2KB , and buffer manager, inte grated MX93011 DSP core , and a complete host inter face for both the PC Card , ,asserted by external MX93011 DSP. The internal DSP PCE# 67 I/O is disabled. These pins include internal , external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. DCE# 68 I/O In , signal is drived to high. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP


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PDF MX9691 6016h 6009H macronix dsp 7400h 74640 ic 74640
TC58V32FT

Abstract: ssd controller "SSD Controller" AS 108-120 macronix mxic dsp TC5816FT KM29N32000 PCMCIA SRAM Card MX29F1610 8088 memory interface SRAM
Text: · DSP core · High performance MX93011 DSP (21Mips) core. · 4KB Internal RAM(direct access). · , buffer manager, integrated MX93011 DSP core, and a complete host interface for both the PC Card ATA and , ,these address are input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled , ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is , ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is


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PDF MX9691L 20MB/sec. PM0546 JUL/02/1999 TC58V32FT ssd controller "SSD Controller" AS 108-120 macronix mxic dsp TC5816FT KM29N32000 PCMCIA SRAM Card MX29F1610 8088 memory interface SRAM
1997 - MX-1610

Abstract: intel 28f200 db86082 mx1610 intel 80586 db86082b MXIC flash disk controller MX28F002 ssd controller MX26C1024A
Text: No file text available


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PDF MX26C512A MX26C1000A MX26C1024A MX25L4004A MX29F1610 MX26C512A, 512K-bit MX26C512A MX9691 MX-1610 intel 28f200 db86082 mx1610 intel 80586 db86082b MXIC flash disk controller MX28F002 ssd controller MX26C1024A
Not Available

Abstract: No abstract text available
Text: €¢ High performance MX93011 DSP (21 Mips) core. • 4KB Internal RAM(direct access). • 2KB Internal , MX93011 DSP core , and a complete host inter­ face for both the PC Card ATA and ATA standard. trol , registers. In ICE debugging mode, these ad dress are input,asserted by external MX93011 DSP. The internal , is drived to high. In ICE de bugging mode, this signal is input, asserted by external MX93011 DSP , signal is drived to high. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP


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PDF MX9691 -100mA 100mA
1998 - MX9691

Abstract: 74640 HD15 MX93011 ICE ICC3
Text: bit as well as 16 bit transfer on host bus. DSP core · High performance MX93011 DSP (21Mips) core , , integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and ATA standard , debugging mode, these ad dress are input,asserted by external MX93011 DSP. The internal DSP is disabled , , this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin , , asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit


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PDF MX9691 20MB/ 100mA MX9691 74640 HD15 MX93011 ICE ICC3
MX93011

Abstract: No abstract text available
Text: well as 16 bit transfer on host bus. DSP core · High performance MX93011 DSP (21 Mips) core. · 4KB , manager, integrated MX93011 DSP core, and a complete host interface for both the PC Card ATA and True IDE , DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. These pins include , signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time , ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is


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PDF MX9691L 20MB/sec. MX93011
2002 - MXIC flash disk controller

Abstract: macronix mxic dsp MX93011 HD11 MX51L9692 MXIC sequential
Text: control for Host reset signal. DSP core: · High performance MX93011 DSP core. · 2KW Internal Direct


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PDF MX51L9692 256Mbit 64Mbit/128Mbit/256Mbit/512Mbit PM0935 MXIC flash disk controller macronix mxic dsp MX93011 HD11 MX51L9692 MXIC sequential
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