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LTC2632-LMI8#TRPBF Linear Technology IC 8-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter
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MTTL and MECL Avionics Digital AN532 Datasheets Context Search

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MC4044

Abstract: MTTL mecl mttl MC12013 648 ANALOG MC12020 MC12012 MC12000 MC4024 MC12002
Text: 648 648 648 646 648 648 648 648 MECL MECL MTTL MTTL MECL MECL MECL MECL MTTL MECL MECL MECL MTTL MTTL , , frequency division, filtering, and voltage-controlled signal generation. In addition, the choice of circuits , high speed is required. The MC12000 series circuits will operate at either —5.0 V or —5.2 V, and translators are included where needed so that all functions are compatible. FUNCTIONS AND CHARACTERISTICS , Voltage-Controlled Multivibrator Dual Voltage-Controlled Multivibrator Phase-Frequency Detector Digital Mixer


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PDF MC12000 MC1658 MC4024 MC4044 MC12000 MC12002 MC12012 MC12013 MC12014 MC12020 MC4044 MTTL mecl mttl MC12013 648 ANALOG MC12020 MC12012 MC4024 MC12002
MC1600

Abstract: MC1603 MC1604 MC4024 MECL III Series MC1602 MC1601 mecl mttl MC1648 MC1650
Text:  MECL III MC1600 Series MC1600 Series (-30°C to -85°C) The requirement for digital systems , subnanosecond propagation delays — MECL III. MECL III circuit design is similar to that used is the popular MECL 10,000 family. In the MECL III line, as well as MECL 10,000, advanced processing techniques are employed and the capability for driving low-impedance terminated lines is provided. MECL III is recommended , 648 648 648 648 MECL MECL MTTL MTTL MECL MECL MECL MECL MTTL MECL MECL MECL MTTL MTTL 225 150 30


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PDF MC1600 MC1658 MC4024 MC4044 MC12000 MC12002 MC12012 MC12013 MC12014 MC1603 MC1604 MC4024 MECL III Series MC1602 MC1601 mecl mttl MC1648 MC1650
MC10525L

Abstract: MC10507 MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102
Text: and control signals between the MECL section and saturated logic sections of digital systems. The , dc levels are MECL 10,000 in and Schottky TTL, or MTTL out. This device has an input common mode , logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability


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PDF lsu37 MC10525L MC10507 MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102
MC10616

Abstract: MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102 mecl logic
Text: interfacing data and control signals between the MECL section and saturated logic sections of digital systems , of 10 MTTL loads. The dc levels are MECL 10,000 in and Schottky TTL, or MTTL out. This device has an , logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability


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mecl logic

Abstract: MC10124P MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102 C101
Text: interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The MC10124 has MTTL compatible inputs, and MECL complementary open-emitter outputs that allow use as , logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability


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PDF SO-12 mecl logic MC10124P MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102 C101
MC10524L

Abstract: MC1010 MC10516 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 NTC+10+1116
Text: and control signals between a saturated logic section and the MECL section of digital systems. The MC10524 has MTTL compatible inputs, and MECL complementary open-emitter outputs that allow use as an , logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability


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mc75113

Abstract: mc75107 MC74107 MC75107L MC3453A MC3450 MC14435 MC10116 application MC10194 MC3486
Text: logic level. This function may be performed by various digital and linear 3 FIGURE 6 — MC75107 Line , 's specifically designed as line receivers that combine linear and digital techniques. These IC's use linear , common digital logic families, such as TTL, CMOS, MECL , etc. An example of a line receiver is the , transmission of digital data. Where noise appears and how it influences the system will depend largely on the , necessarily the end of the line. Figure 23 describes a MECL line driver1^ and receiver using gates. This


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PDF AN-708A MC1405-MC14435 MC696 AN-781, MCI0194 1PHXB566-Â B470B AN708A/D AN708A/D mc75113 mc75107 MC74107 MC75107L MC3453A MC3450 MC14435 MC10116 application MC10194 MC3486
1997 - MC12013

Abstract: MC12011 MC12013P MC12011P MC12014 MC12009P MC12009 Mot prescaler MC4044 MC4016B
Text: , there is a buffered clock input and MECL bias voltage source. · MC12009 480 MHz ( 5/6), MC12011 550 MHz ( 8/9), MC12013 550 MHz ( 10/11) · MECL to MTTL Translator on Chip B · · · · · B B MECL PLL COMPONENTS DUAL MODULUS PRESCALER SEMICONDUCTOR TECHNICAL DATA MECL and MTTL Enable , test, and the voltage indicated applied to the other input(s) of the same type ( i.e., MECL or MTTL ). , ( MTTL V CC ), Pin 16 (V CC ), and ground Pin 8 (V EE ). When using ­5.2 V supply, ground Pin 1 (V CCO


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PDF MC12009/D MC12009 MC12011 MC12013 MC12014 MC12009 MC12011 12009/D MC12013 MC12013P MC12011P MC12009P Mot prescaler MC4044 MC4016B
2008 - EH 137 pulse generator

Abstract: MC12014 ML12509 ML12511 ML12513 divide-by-10 pulse generator
Text: Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. · ML12509 480 MHz (÷5/6), ML12511 550 MHz (÷8/9), ML12513 550 MHz (÷10/11) · MECL to MTTL Translator on Chip · MECL and MTTL Enable Inputs · 5.0 or ­5.2 V Operation* · Buffered Clock Input - Series Input RC Typ , Pin 1 (VCCO), Pin 6 ( MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using ­5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL VCC), and Pin 16 (VCC) and apply ­5.2 V to Pin 8 (VEE). If the


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PDF ML12509 ML12511 ML12513 MC12014 ML12509 ML12511 ML12513 EH 137 pulse generator MC12014 divide-by-10 pulse generator
C101

Abstract: MC10507 MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102
Text: logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability , Quad MTTL to MECL Translator M C10124 MC 1 0524 3.5 380 620,648,650 Quad MECL to MTTL Translator M , DIAGRAMS (continued) [-TRANSLATORS- MC10124 MCI 0525 Quad MTTL to MECL Translator (14) lO-dö) 11 - PD


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PDF 100-ohm C101 MC10507 MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102
Not Available

Abstract: No abstract text available
Text: interface with the 12514 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. · 600 M Hz (Typ) Toggle Frequency · 12511 (+8/9) · MECL to MTTL Translator on Chip · MECL and MTTL Enable Inputs · + 5.0 or - 5.2 V Operation * · Buffered Clock Input Series Input RC Typ, 20 , ) Clock Til Vbb Ï U El MECL ] 2 ] E2MECL ] ï ] E3MECL 70] E4 MTTL E [I H E (T 7] E5 MTTL LOGIC DIAGRAM 51 n t o v - r r 51 Q to Vjt MECL MECL MTTL MTTL E2 E3 E4 E5 OPEN 51 n t o v -


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PDF 12511/BXAJC
1998 - MC12013P

Abstract: MC10131 16 PIN ic 810 MC4016 MC1648 MC12014 MC12013 MC12009 MC10109 MC12011
Text: MECL to MTTL Translator on Chip MECL and MTTL Enable Inputs SEMICONDUCTOR TECHNICAL DATA 5.0 or , the MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias , ( MTTL V CC ), and Pin 16 (V CC ) and apply ­5.2 V to Pin 8 (V EE ). If the translator is not required , 9 E5 MECL mAdc Tstg 6 MTTL Output Vdc Output Source Current Continuous Surge , MTTL E4 10 MECL E3 11 C C MECL E2 12 MECL E1 13 C Recommended Circuitry For ac coupled


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PDF MC12013/D MC12013 MC12014 MC12013P MC10131 16 PIN ic 810 MC4016 MC1648 MC12013 MC12009 MC10109 MC12011
Not Available

Abstract: No abstract text available
Text: ), ML12011 550 MHz (÷8/9) MECL to MTTL Translator on Chip MECL and MTTL Enable Inputs 5.0 or –5.2 V , Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. • • â , ), Pin 16 (VCC), and ground Pin 8 (VEE). When using –5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL , 175 TA –30 to 85 °C n 70 5 MTTL VCC 6 MTTL Output 7 11 E3 MECL 10 , Q1 D C Q1 Q2 C D MTTL E4 10 MECL to MTTL Translator Q3 MECL E3 11


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PDF ML12009 ML12011 MC12009, MC12011 MC12014 ML12009 ML12011
2005 - pulse generator

Abstract: EH 137 pulse generator Pulse generator circuit divide by 5 divide-by-10 ML12513 ML12511 ML12509 MC12014 LANSDALE SEMICONDUCTOR
Text: Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. · ML12509 480 MHz (÷5/6), ML12511 550 MHz (÷8/9), ML12513 550 MHz (÷10/11) · MECL to MTTL Translator on Chip · MECL and MTTL Enable Inputs · 5.0 or ­5.2 V Operation* · Buffered Clock Input - Series Input RC Typ , Pin 1 (VCCO), Pin 6 ( MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using ­5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL VCC), and Pin 16 (VCC) and apply ­5.2 V to Pin 8 (VEE). If the


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PDF ML12509 ML12511 ML12513 MC12014 ML12509 ML12511 ML12513 pulse generator EH 137 pulse generator Pulse generator circuit divide by 5 divide-by-10 MC12014 LANSDALE SEMICONDUCTOR
2008 - MC1648

Abstract: MC1648 "cross reference" ML12011 ML12009 MC12014 MC12011P MC12011D MC12009P MC12009D MC12009
Text: MTTL Translator on Chip MECL and MTTL Enable Inputs 5.0 or ­5.2 V Operation* Buffered Clock Input - , addition, there is a buffered clock input and MECL bias voltage source. · · · · · · · 16 1 , using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 ( MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using ­5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL VCC), and Pin 16 (VCC) and apply , VBB 13 E1 MECL 12 E2 MECL 4 (+) ­65 to 175 TA ­30 to 85 °C n 70 5 MTTL


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PDF ML12009 ML12011 MC12009, MC12011 MC12014 ML12009 ML12011 MC1648 MC1648 "cross reference" MC12014 MC12011P MC12011D MC12009P MC12009D MC12009
Mc10216

Abstract: motorola 10116 MC10115 MC10110 MC1011 MECL 10000 series MC10105 MC10103 MC10102 MC10128
Text: logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability , Quad MTTL to MECL Translator M C10124 MC 1 0524 3.5 380 620,648,650 Quad MECL to MTTL Translator M , DIAGRAMS (continued) [-TRANSLATORS- MC10124 MCI 0525 Quad MTTL to MECL Translator (14) lO-dö) 11 - PD


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PDF 10O-Strobe 50-ohm MC10129 t7-14- Mc10216 motorola 10116 MC10115 MC10110 MC1011 MECL 10000 series MC10105 MC10103 MC10102 MC10128
1998 - MC12011P

Abstract: MC12011 MC12011D MC12014 MC1648 MC4044 MC12009 MC12009D MC12009P
Text: · · B B MECL to MTTL Translator on Chip MECL PLL COMPONENTS DUAL MODULUS PRESCALER MECL and MTTL Enable Inputs 5.0 or ­5.2 V Operation* SEMICONDUCTOR TECHNICAL DATA Buffered , , there is a buffered clock input and MECL bias voltage source. · MC12009 480 MHz ( 5/6), MC12011 550 MHz , ), Pin 6 ( MTTL V CC ), Pin 16 (VCC ), and ground Pin 8 (V EE ). When using ­5.2 V supply, ground Pin 1 (V CCO ), Pin 6 ( MTTL V CC ), and Pin 16 (VCC ) and apply ­5.2 V to Pin 8 (V EE ). If the translator


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PDF MC12009/D MC12009 MC12011 MC12014 MC12009 MC12011 MC12011P MC12011D MC1648 MC4044 MC12009D MC12009P
10116

Abstract: MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102 C101
Text: logic functions and the 2.0 ns propagation delay make MECL 10,000 a versatile family for data handling and processing systems. Circuit design with MECL 10,000 is unusually convenient. The differential , outputs. MECL III is directly compatible with MECL 10,000, and can be used to extend the speed capability , Quad MTTL to MECL Translator M C10124 MC 1 0524 3.5 380 620,648,650 Quad MECL to MTTL Translator M , DIAGRAMS (continued) [-TRANSLATORS- MC10124 MCI 0525 Quad MTTL to MECL Translator (14) lO-dö) 11 - PD


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PDF 50-ohm 10116 MC10115 MC10114 MC10110 MC1011 MC10106 MC10105 MC10103 MC10102 C101
1998 - MC12013

Abstract: MC12011 MC1648 MC12014 MC12011P MC12011D MC12009P MC12009D MC12009 MC4044
Text: a buffered clock input and MECL bias voltage source. · MC12009 480 MHz ( 5/6), MC12011 550 MHz ( 8/9) · · · · · · B B MECL to MTTL Translator on Chip MECL PLL COMPONENTS DUAL MODULUS PRESCALER MECL and MTTL Enable Inputs 5.0 or ­5.2 V Operation* SEMICONDUCTOR TECHNICAL , ) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO ), Pin 6 ( MTTL V CC ), Pin 16 (V CC ), and ground Pin 8 (V EE ). When using ­5.2 V supply, ground Pin 1 (V CCO ), Pin 6 ( MTTL V CC ), and Pin 16


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PDF MC12009/D MC12009 MC12011 MC12014 MC12009 MC12011 MC12013 MC1648 MC12011P MC12011D MC12009P MC12009D MC4044
mc12013

Abstract: MC12009 MC12011 mecl mttl MC12011P motorola 12014
Text: ), MC12013 550 MHz (-r 10/11) · MECL to MTTL Translator on Chip MCI 2009 MC12011 MCI 2013 MECL PLL COMPONENTS DUAL MODULUS PRESCALER SEMICONDUCTOR TECHNICAL DATA · MECL and MTTL Enable Inputs · 5.0 or - 5 , MECL to MTTL Trans lator 7 Ô MTTL Out D 01 D 02 D 03 C r 1k C r s js 04 Toggle Flip Flop * - C 04 C MECL to MTTL Trans lator - Recommended Circuitry For ac , Toggle Flip Flop C 04 MECL to MTTL Trans lator C r 1k C r C IV ßB T l4 P u ll-d o w


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PDF MC12009 MC12011 MC12013 MC12013) MC10131 mecl mttl MC12011P motorola 12014
motorola 12514

Abstract: No abstract text available
Text: clock input and MECL bias voltage source. · · · · · · · · 600 MHz (Typ) Toggle Frequency 12511 (+8/9) MECL to MTTL Translator on Chip MECL and MTTL Enable Inputs + 5.0 or - 5.2 V Operation * Buffered Clock , GND GND 51 n to 51 51 v jt |T 1] E5 MTTL LOGIC DIAGRAM MECL MECL MTTL MTTL E2 E3 E4 E5 , ( V c c o ) .Pin 6 ( MTTL V c c ). Pin 16 ( V c c ) ' and ground Pin 8 (Vee)- When using -5 .2 V supply, ground Pin 1 (V c c o ) ' p 'n ®( MTTL V c c )' and Pin 16 ( V c c ) and *PPly 5 2 V to Pin 8 (Vee)- H ,he


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PDF
EH 137 pulse generator

Abstract: No abstract text available
Text: Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. • ML12509 480 MHz (÷5/6), ML12511 550 MHz (÷8/9), ML12513 550 MHz (÷10/11) • MECL to MTTL Translator on Chip • MECL and MTTL Enable Inputs • 5.0 or –5.2 V Operation* • Buffered Clock Input â , supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 ( MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using –5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL VCC), and Pin 16 (VCC) and apply –5.2 V to Pin


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PDF ML12509 ML12511 ML12513 MC12014 ML12509 ML12511 ML12513 EH 137 pulse generator
1998 - MC12011

Abstract: MC12009 MC1648 MC12014 MC12011P MC12011D MC12009P MC12009D MC4044 MC4016B
Text: a buffered clock input and MECL bias voltage source. · MC12009 480 MHz ( 5/6), MC12011 550 MHz ( 8/9) · · · · · · B B MECL to MTTL Translator on Chip MECL PLL COMPONENTS DUAL MODULUS PRESCALER MECL and MTTL Enable Inputs 5.0 or ­5.2 V Operation* SEMICONDUCTOR TECHNICAL , ) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO ), Pin 6 ( MTTL V CC ), Pin 16 (V CC ), and ground Pin 8 (V EE ). When using ­5.2 V supply, ground Pin 1 (V CCO ), Pin 6 ( MTTL V CC ), and Pin 16


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PDF MC12009/D MC12009 MC12011 MC12014 MC12009 MC12011 MC1648 MC12011P MC12011D MC12009P MC12009D MC4044 MC4016B
2005 - mc4044

Abstract: MC1648 "cross reference" mc4016 dip MC12014 MC12011P MC12011D MC12011 MC12009P MC12009D MC12009
Text: MTTL Translator on Chip MECL and MTTL Enable Inputs 5.0 or ­5.2 V Operation* Buffered Clock Input - , addition, there is a buffered clock input and MECL bias voltage source. · · · · · · · 16 1 , using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 ( MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using ­5.2 V supply, ground Pin 1 (VCCO), Pin 6 ( MTTL VCC), and Pin 16 (VCC) and apply , E1 MECL 12 E2 MECL 4 (+) ­65 to 175 TA ­30 to 85 °C n 70 5 MTTL VCC


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PDF ML12009 ML12011 MC12009, MC12011 MC12014 ML12009 ML12011 mc4044 MC1648 "cross reference" mc4016 dip MC12014 MC12011P MC12011D MC12011 MC12009P MC12009D MC12009
MC12060

Abstract: sine wave crystal controlled oscillator MC12061 MC12560 MC12561 MC12060-MC12560 2sc 1116 JIDC
Text: usual power supply pin bypass capacitors). Translators are provided internally for MECL and MTTL outputs , - - - - 8,9,10 'Devices will meet standard MECL logic levels using VE £ - -5.2 Vdc and Vqq - 0. O MC 12060, MC 12560 (continued) MC 12061, MC 12561 FIGURE 6 - AC CHARACTERISTICS - MECL AND MTTL , translators convert these sine wave outputs to levels compatible with MECL and /or MTTL . Series mode crystals , . Complementary MECL 3. Single Ended MTTL L SUFFIX CERAMIC PACKAGE CASE 620 P SUFFIX PLASTIC PACKAGE CASE 648


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PDF MC12060-MC12560 MC1206MMC12561 MC12060/12560 MC12061/12561 MC12060/12560 MC12061/12561 MC12560, MC12060, HP8552B/53B MC12060 sine wave crystal controlled oscillator MC12061 MC12560 MC12561 2sc 1116 JIDC
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