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2011 - samsung* lpddr2* pop package

Abstract: 152-Ball PoP MT46H64M16LF cross Micron LPDDR2 MT46H64M16LF
Text: Preliminary 1Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H64M16LF ­ 16 Meg x 16 x 4 banks MT46H32M32LF ­ 8 Meg x 32 x 4 banks MT46H32M32LG ­ 8 Meg x 32 x 4 banks Features · VDD/VDDQ = 1.70­1.95V · Bidirectional data strobe per byte of data (DQS) · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Differential clock inputs (CK and CK#) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs


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PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 09005aef84812cd1 samsung* lpddr2* pop package 152-Ball PoP MT46H64M16LF cross Micron LPDDR2 MT46H64M16LF
2009 - Not Available

Abstract: No abstract text available
Text: No file text available


Original
PDF MT46H64M16LF MT46H32M32LF 60-ball 90-ball 168-ball 09005aef83d9bee4
2009 - LPDDR2 SDRAM micron

Abstract: 1GB-x16 ELPIDA lpddr smd marking code T2N LPDDR2 SDRAM elpida 152-Ball Dual LPDDR2 micron lpddr2 samsung lpddr samsung* lpddr2* pop package
Text: 1Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H64M16LF ­ 16 Meg x 16 x 4 banks MT46H32M32LF ­ 8 Meg x 32 x 4 banks MT46H32M32LG ­ 8 Meg x 32 x 4 banks Features · VDD/VDDQ = 1.70­1.95V · Bidirectional data strobe per byte of data (DQS) · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Differential clock inputs (CK and CK#) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 09005aef83d9bee4 LPDDR2 SDRAM micron 1GB-x16 ELPIDA lpddr smd marking code T2N LPDDR2 SDRAM elpida 152-Ball Dual LPDDR2 micron lpddr2 samsung lpddr samsung* lpddr2* pop package
2011 - Not Available

Abstract: No abstract text available
Text: 1Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive Low-Power DDR SDRAM MT46H64M16LF – 16 Meg x 16 x 4 banks MT46H32M32LF – 8 Meg x 32 x 4 banks MT46H32M32LG – 8 Meg x 32 x 4 banks Features Options • VDD/VDDQ – 1.8V/1.8V • Configuration – 64 Meg x 16 (16 Meg x 16 x 4 banks) – 32 Meg x 32 (8 Meg x 32 x 4 banks) • Addressing – JEDEC-standard – JEDEC reduced page size • Plastic "green" package – 60-ball VFBGA (8mm x 9mm) 1 – 90-ball VFBGA (8mm x 13mm


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 60-ball 90-ball 168-ball 09005aef84812cd1
2009 - ELPIDA mobile dram LPDDR2

Abstract: LPDDR2 SDRAM micron samsung lpddr LPDDR2 SDRAM elpida 152-Ball PoP samsung* lpddr2* pop package MT46H64M16LF smd marking code T2N ELPIDA lpddr samsung* lpddr2* pop
Text: 1Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H64M16LF ­ 16 Meg x 16 x 4 banks MT46H32M32LF ­ 8 Meg x 32 x 4 banks MT46H32M32LG ­ 8 Meg x 32 x 4 banks Features · VDD/VDDQ = 1.70­1.95V · Bidirectional data strobe per byte of data (DQS) · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Differential clock inputs (CK and CK#) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 09005aef83d9bee4 ELPIDA mobile dram LPDDR2 LPDDR2 SDRAM micron samsung lpddr LPDDR2 SDRAM elpida 152-Ball PoP samsung* lpddr2* pop package MT46H64M16LF smd marking code T2N ELPIDA lpddr samsung* lpddr2* pop
2009 - 1GB-x16

Abstract: ELPIDA lpddr samsung lpddr infineon power cycling LPDDR2 SDRAM samsung MT46H64M16LF cross
Text: No file text available


Original
PDF MT46H64M16LF MT46H32M32LF 09005aef83d9bee4 1GB-x16 ELPIDA lpddr samsung lpddr infineon power cycling LPDDR2 SDRAM samsung MT46H64M16LF cross
2009 - Not Available

Abstract: No abstract text available
Text: No file text available


Original
PDF MT46H64M16LF MT46H32M32LF 60-ball 90-ball 168-ball 09005aef83d9bee4
2011 - Not Available

Abstract: No abstract text available
Text: 1Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive Low-Power DDR SDRAM MT46H64M16LF – 16 Meg x 16 x 4 banks MT46H32M32LF – 8 Meg x 32 x 4 banks MT46H32M32LG – 8 Meg x 32 x 4 banks Features Options • VDD/VDDQ – 1.8V/1.8V • Configuration – 64 Meg x 16 (16 Meg x 16 x 4 banks) – 32 Meg x 32 (8 Meg x 32 x 4 banks) • Addressing – JEDEC-standard – JEDEC reduced page size • Plastic "green" package – 60-ball VFBGA (8mm x 9mm) 1 – 90-ball VFBGA (8mm x 13mm


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 60-ball 90-ball 168-ball 09005aef84812cd1
2011 - Not Available

Abstract: No abstract text available
Text: 1Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H64M16LF – 16 Meg x 16 x 4 banks MT46H32M32LF – 8 Meg x 32 x 4 banks MT46H32M32LG – 8 Meg x 32 x 4 banks Features Options • VDD/VDDQ – 1.8V/1.8V • Configuration – 64 Meg x 16 (16 Meg x 16 x 4 banks) – 32 Meg x 32 (8 Meg x 32 x 4 banks) • Addressing – JEDEC-standard – JEDEC reduced page size • Plastic "green" package – 60-ball VFBGA (8mm x 9mm) 1 – 90-ball VFBGA (8mm x 13mm) 2 • PoP


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 60-ball 90-ball 168-ball 09005aef84812cd1
2009 - wfbga

Abstract: 1GB-x16 152-Ball PoP MT46H64M16LF
Text: 1Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H64M16LF ­ 16 Meg x 16 x 4 banks MT46H32M32LF ­ 8 Meg x 32 x 4 banks MT46H32M32LG ­ 8 Meg x 32 x 4 banks Features · VDD/VDDQ = 1.70­1.95V · Bidirectional data strobe per byte of data (DQS) · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Differential clock inputs (CK and CK#) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 09005aef83d9bee4 wfbga 1GB-x16 152-Ball PoP MT46H64M16LF
2009 - smd marking code T2N

Abstract: ELPIDA lpddr 1GB-x16 152-Ball PoP MT46H64M16LF
Text: 1Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H64M16LF ­ 16 Meg x 16 x 4 banks MT46H32M32LF ­ 8 Meg x 32 x 4 banks MT46H32M32LG ­ 8 Meg x 32 x 4 banks Features · VDD/VDDQ = 1.70­1.95V · Bidirectional data strobe per byte of data (DQS) · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Differential clock inputs (CK and CK#) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data


Original
PDF MT46H64M16LF MT46H32M32LF MT46H32M32LG 09005aef83d9bee4 smd marking code T2N ELPIDA lpddr 1GB-x16 152-Ball PoP MT46H64M16LF
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