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MP1496SGJ-Z Monolithic Power Systems Switching Regulator, Current-mode, 500kHz Switching Freq-Max, PDSO8, TSOT-23, 8 PIN
MP1496DJ-LF-Z Monolithic Power Systems Switching Regulator, Current-mode, 500kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MO-193BA, TSOT-23, 8 PIN
MP1496-0B0 LAIRD PLC FERRITE PLATE 38MMX38MMX2MM
MP1496-000 LAIRD PLC FERRITE EMI PLATE 38MMX38MMX2MM
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MP1496SGJ-P Monolithic Power Systems IC REG BUCK ADJ 2A SYNC
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Catalog Datasheet MFG & Type PDF Document Tags
2013 - LFB095051-000

Abstract: M/UPS FERRITE
Text: No file text available


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2012 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF MP1496 500kHz MP1496 TSOT23-8
2002 - J-STD-020A

Abstract: 150MIL DS1077L DS1077LX60
Text: ) SEL0 EN0 PDN 0 INTERNAL OSCILLATOR Enable Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 , and values of prescaler P0 (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A , SEL0 1 EN0 1 0M1 0 0M0 0 1M1 0 MSB 1M0 0 first data byte LSB DIV1 0 x , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See


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PDF DS1077L 87kHz 666MHz DS1077Lx-40 000MHz 87kHz DS1077Lx-50 09kHz DS1077Lx-60 J-STD-020A 150MIL DS1077L DS1077LX60
2002 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM DS1077L Figure 1 SEL0 EN0 PDN 0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A multifunctional input pin that can be , SDA and SCL pins. MUX WORD MSB Name Default setting * 0 PDN1 0 PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077L 87kHz 666MHz 150mil 118mil DS1077Lx-40 000MHz DS1077Lx-50
2002 - J-STD-020A

Abstract: 150MIL DS1077L
Text: Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE "N" DIVIDER , P0 (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A multifunctional input pin that , EN0 1 0M1 0 0M0 0 1M1 0 MSB 1M0 0 first data byte LSB DIV1 0 x x x , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See


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PDF DS1077L 87kHz 666MHz DS1077Lx-40 000MHz 87kHz DS1077Lx-50 09kHz DS1077Lx-60 J-STD-020A 150MIL DS1077L
2002 - 150MIL

Abstract: DS1077L J-STD-020A
Text: Enable Select MCLK DIV1 Power-Down 0M1 0M0 1M1 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE "N" DIVIDER , P0 (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A multifunctional input pin that , EN0 1 0M1 0 0M0 0 1M1 0 MSB 1M0 0 first data byte LSB DIV1 0 x x x , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See


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PDF DS1077L 87kHz 666MHz DS1077Lx-40 000MHz 87kHz DS1077Lx-50 09kHz DS1077Lx-60 150MIL DS1077L J-STD-020A
2002 - DS1085

Abstract: DS1085Z-10 DS1085Z-25 DS1085Z-50 J-STD-020A
Text: DIAGRAM 0M0 0M1 1M0 1M1 OVERVIEW A block diagram of the DS1085 is shown in Figure 1. The , 0M0 and 0M1) (see Table 2). Power Supply Ground A multifunction control input pin that can be , NAME * PDN1 PDN0 SEL0 EN0 0M1 0M0 1M1 1M0 Default 0 0 0 1 1 0 0 0 0 Setting *This bit must , determined by the values of EN0 and SEL0 (see Table 2). 0M0 , 0M1, 1M0, 1M1 (Default Setting = 0) These , of 21 DS1085 Table 7a. PRESCALER P0 DIVISOR M SETTINGS 0M1 0M0 0 0 0 1 1 0 1 1


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PDF DS1085 133MHz 133MHz 150mil) DS1085-25 DS1085-10 DS1085-50 DS1085 DS1085Z-10 DS1085Z-25 DS1085Z-50 J-STD-020A
2002 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM DS1077L Figure 1 SEL0 EN0 PDN 0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A multifunctional input pin that can be , SDA and SCL pins. MUX WORD MSB Name Default setting * 0 PDN1 0 PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077L 87kHz 666MHz 150mil 118mil DS1077Lx-40 000MHz DS1077Lx-50
2001 - Not Available

Abstract: No abstract text available
Text: request. 1 of 17 042801 DS1077 BLOCK DIAGRAM 1077 Figure1 SEL0 EN0 PDN 0 Select MCLK DIV1 0M1 0M0 1M1 , 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX OUT0 Power Down CONTROL LOGIC (TABLE 1) Enable INTERNAL , CTRL0 and values of Prescaler P0 (mode bits 0M1 & 0M0 ). (Refer to Table 1) CONTROL PIN 0 (CTRL0) A , via the SDA and SCL pins. MUX WORD msb Name Default seeting * 0 PDN1 0 PDN0 0 SEL0 1 EN0 1 0M0 0 , ignored. If DIV1=0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits


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PDF DS1077 133MHz 250ns 1250ns DS1077Z-100
2001 - Not Available

Abstract: No abstract text available
Text: Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX MCLK Power-Down CONTROL LOGIC (TABLE 1 , determined by the control register settings for CTRL0 and values of prescaler P0 (mode bits 0M1 and 0M0 ). , * 0 PDN1 0 PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB 1M0 0 DIV1 0 x x x x LSB x x , , 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See Table


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PDF DS1077L 87kHz 666MHz 150mil 118mil DS1077Lx-40 000MHz DS1077Lx-50 00unless
2002 - J-STD-020A

Abstract: DS1077 DS1077Z-100 122kHz
Text: MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE "N" DIVIDER P1 PRESCALER (M , control register settings for CTRL0 and values of Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). , * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077 133MHz DS1077x-133 333MHz DS1077x-125 000MHz DS1077x-120 DS1077x-100 J-STD-020A DS1077 DS1077Z-100 122kHz
2002 - DS1077

Abstract: DS1077Z-100 J-STD-020A
Text: MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE "N" DIVIDER P1 PRESCALER (M , control register settings for CTRL0 and values of Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). , * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077 133MHz DS1077x-133 333MHz DS1077x-125 000MHz DS1077x-120 DS1077x-100 DS1077 DS1077Z-100 J-STD-020A
2009 - M/UPS FERRITE

Abstract: No abstract text available
Text: No file text available


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PDF MP0315-200 M/UPS FERRITE
S2001

Abstract: steward catalog 28S2001
Text: PRINT FORMAT ADD DETAILS. UPDATE Z SPECS 09/28/01 JRK PROJECT/PART NUMBER: 28S2001 — 0M0 REV G PART


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PDF WEIGHT/1000 E4991A 6092A-Test 28S2001 S2001 S2001 steward catalog 28S2001
Arnold

Abstract: Arnold Magnetics
Text: L8 'ON ' 0M0 REV. DESCRIPTION S.O. BY DATE CONFIDENTIALITY NOTICE Important: This information is Confidential Information of Group Arnold. By accepting receipt of this Confidential Information, the Recipient agrees not to disclose this Confidential Information to any other party and to use this Confidential Information only to produce parts for Group Arnold. The Recipient recognizes that release of this Confidential Information to any individual or entity not employed by or directly owned by the Recipient Is


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MP1496-000

Abstract: HM1400-300 MM0650-100 mm0650 MP0760-100 HP1040 mp1040 MP1496 M/UPS FERRITE
Text: No file text available


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PDF MP1040-100 HP1040-100 SIP-BRO-DISKPLATE-0208 MP1496-000 HM1400-300 MM0650-100 mm0650 MP0760-100 HP1040 mp1040 MP1496 M/UPS FERRITE
2007 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM DS1077L Figure 1 SEL0 EN0 PDN 0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A multifunctional input pin that can be , SDA and SCL pins. MUX WORD MSB Name Default setting * 0 PDN1 0 PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077L 87kHz 666MHz 150mil 118mil DS1077Lx-40 000MHz DS1077Lx-50 DS1077LU-40+
2007 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM 1077 Figure1 SEL0 EN0 PDN0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). Control Pin 0 (CTRL0)-A multifunctional input pin that , . MUX WORD MSB Name * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB LSB 1M0 , divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to


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PDF DS1077 133MHz 150mil 118mil DS1077x-133 333MHz DS1077x-125 000MHz 21-0036J DS1077U-120/T
2002 - Not Available

Abstract: No abstract text available
Text: EN0 PDN0 INTERNAL OSCILLATOR Enable Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 , and values of Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). Control Pin 0 (CTRL0)—A , EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB LSB 1M0 DIV1 - - - - - 0 0 x x x x x x first , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8 (see


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PDF DS1077 133MHz DS1077x-133 333MHz DS1077x-125 000MHz DS1077x-120 DS1077x-100
2002 - Not Available

Abstract: No abstract text available
Text: ) SEL0 EN0 PDN 0 INTERNAL OSCILLATOR Enable Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 , CTRL0 and values of prescaler P0 (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) – A , SEL0 1 EN0 1 0M1 0 0M0 0 1M1 0 MSB 1M0 0 first data byte LSB DIV1 0 x , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See


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PDF DS1077L 87kHz 666MHz DS1077Lx-40 000MHz 87kHz DS1077Lx-50 09kHz DS1077Lx-60
2002 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM 1077 Figure1 SEL0 EN0 PDN0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). Control Pin 0 (CTRL0)-A multifunctional input pin that , . MUX WORD MSB Name * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB LSB 1M0 , divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to


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PDF DS1077 133MHz 150mil 118mil DS1077x-133 333MHz DS1077x-125 000MHz DS1077 DS1077-133
2007 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM 1077 Figure1 SEL0 EN0 PDN0 Select DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS P1 PRESCALER (M DIVIDER) PROGRAMMABLE "N" DIVIDER OUT1 0M1 0M0 DIV1 P0 PRESCALER (M DIVIDER) MUX , Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). Control Pin 0 (CTRL0)-A multifunctional input pin that , . MUX WORD MSB Name * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB LSB 1M0 , divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to


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PDF DS1077 133MHz 150mil 118mil DS1077x-133 333MHz DS1077x-125 000MHz DS1077U-120/T DS1077U-133
2006 - 150MIL

Abstract: DS1077L J-STD-020A
Text: ) SEL0 EN0 PDN 0 INTERNAL OSCILLATOR Enable Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 , and values of prescaler P0 (mode bits 0M1 and 0M0 ). (See Table 1.) CONTROL PIN 0 (CTRL0) ­ A , SEL0 1 EN0 1 0M1 0 0M0 0 1M1 0 MSB 1M0 0 first data byte LSB DIV1 0 x , . 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See


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PDF DS1077L 87kHz 666MHz DS1077Lx-40 000MHz 87kHz DS1077Lx-50 09kHz DS1077Lx-60 150MIL DS1077L J-STD-020A
10-PIN

Abstract: 15930j
Text: ARRAYS / " RSN14925 7-DIODE ARRAY 1JSfO 14-PIN PACKAGE ^ ©-M-O ©-W-© 0-M-0 ©-M-© ©-H-© Â


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PDF 15930J 14-pin N/RSN15930 JRSN15932 WSN15944 /pSN15945 RSN14097 16-DtODE 10-PIN
2003 - DS1077

Abstract: DS1077Z-100 J-STD-020A
Text: MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE "N" DIVIDER P1 PRESCALER (M , control register settings for CTRL0 and values of Prescaler P0 (mode bits 0M1 & 0M0 ) (see Table 1). , * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB , 0 (default) the N divider functions normally. 0M1, 0M0 , 1M1, 1M0 (bits) These bits set the


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PDF DS1077 133MHz DS1077x-133 333MHz DS1077x-125 000MHz DS1077x-120 DS1077x-100 DS1077 DS1077Z-100 J-STD-020A
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